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<kempaj@yahoo.com> wrote in message news:1109878145.397950.47950@l41g2000cwc.googlegroups.com... > > > > Hi Jesse, > > > > Thanks for the quick response. I will try your suggestion to get the > .ptf > > going. > > > > On that topic, is there an easy way to change the timing requirements > for > > the SRAM that is used on the eval board? I use equivalent devices on > my > > board, but may want to use slower versions once the design is > complete. i.e. > > I would like to keep my sysclk as high as possible, but have the > option of > > using slower SRAM. Do I have to create an interface to user defined > logic to > > use SRAM that is the same as the eval board, but slower? It would be > nice if > > I could change the timing requirements in a .ptf file like we have > discussed > > for the LAN91C111. > > > > Thanks in advance, > > > > sja > > Hi sja, > > Well the intent with the product is to have you create an interface via > the Component Editor (new SOPC Builder 4.2 feature), or previously, the > "Interface to User Logic". Both of these tools allow you to specify > which signals you want to export to the outside world, which are shared > if using a tri-state bus, setup/wait/hold timing, etc. > > However if you're the adventurous sort, then as you've seen modifying > the source files is another option (the component editor/interface to > user logic basically creates similar files for you). In the case of the > SRAM components in the Nios II dev kit, the timing figures in the > class.ptf file are actually over-written by a perl script (mk_sram.pl), > same folder as the class.ptf for those components, which is run at > system-generation time. The reason behind this is that it allowed us to > fine-tune SRAM timing depending on your system's clock speed... the > script source is pretty easy to follow. If you take this route, I would > save your changes in a separate component folder with separate 'class' > name in the class.ptf file & separate entries in the SOPC Builder GUI > (also in the class.ptf), that way your custom SRAM will show up > independent of the one for the dev. kit...again though, that is what > the Component Editor is for. > > Jesse Kempa > Altera Corp. > jkempa at altera dot com > Hi Jesse, Thanks again for the quick response. I'll have a look at the perl script, but it sounds like the Component Editor is the way to go. You have been most helpful. sjaArticle: 80326
Internal contention creates local currents that are higher than normal, and - in some situations- can overstress the transistors or the interconnect. Metal migration used to be a concern, but is far less so with copper metal today. Anyhow, it is always scary to exercise something that was not meant to be exercised, especially when you have a couple of hundred million of these things on a chip. Why risk anything? Life is too short and too precious to worry about things that are avoidable... Peter AlfkeArticle: 80327
"Marc Randolph" <mrand@my-deja.com> writes: > The bottom of the following page seems to imply you all are correct, > although I'll warn you, it's huge (now 3 CD's). > > http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp Hmmm... I have a BaseX license, but even though I'm logged in to the web site, the only thing I see available for download at the bottom of that page under "Full Releases" is Webpack 6.3i. EricArticle: 80328
Fernando Peral wrote: > I want to use ATMEL ATF750 with ABEL, but i cant find a tool. > ¿is there any way? > > thanks When Synario/Abel was taken over by Xilinx, the tool flow was de-emhasised at Atmel. For the ATF750 family, their Atmel WinCUPL is quite close to Abel, and they have app notes showing both codes. The 750 only has 20 macrocells, and 22 io's, so it is not much work to port Abel code, if that was why you specifically targeted Abel. -jgArticle: 80329
comparchfpga@yahoo.com wrote: > Hi, > > there was a thread with the same topic here: > > http://groups.google.de/groups?hl=de&lr=&selm=885a4a4a.0412030423.4f6b7e7c%40posting.google.com > > In addition to this I would like to know if it is possible Yes > and advisable NO > to make an FPGA hot by intentionally creating contention within the FPGA.Article: 80330
Eric Smith wrote: > "Marc Randolph" <mrand@my-deja.com> writes: > >>The bottom of the following page seems to imply you all are correct, >>although I'll warn you, it's huge (now 3 CD's). >> >>http://www.xilinx.com/xlnx/xil_sw_updates_home.jsp > > > Hmmm... I have a BaseX license, but even though I'm logged in to the web > site, the only thing I see available for download at the bottom of that > page under "Full Releases" is Webpack 6.3i. > > Eric Snap. And yet I'm sure that I saw the 7.1 release there when I visited a day or so ago. I think Xilinx changed the link... Ah well. I've just ordered the EDK and was hoping to get both XST and EDK working at 7.1 :-) Simon.Article: 80331
Ok, my boss gave me the wrong code. The correct one is: ... INT5 := 1; ... It makes sense now.Article: 80332
I just watched the V4 crosstalk talk by Dr. Johnson. It was extremely informative. I've never heard him talk, before. He's really quite a good teacher. I wasn't sure what to expect, as I find his book a little jumbled. I was pleasantly surprised, however. His description of how most of the intra-package crosstalk is due to magnetic coupling, and not merely the voltage deltas caused by di/dt through a particular L nor capacitive coupling due to dv/dt, was quite a surprise. The demonstration of the relative directions of the voltage swings (between aggressor and victim) made this very clear and convincing. One thing I would have loved to have seen were the same tests (or simulations) with drive strengths bigger than 4mA/fast. In our designs, we typically need a mixture of LVCMOS 12mA fast and SSTL2_II, with about 200 I/O toggling together -- which makes for very noisy/jittery V2 and V2-Pros. Anyway, good job, Xilinx. BobArticle: 80333
Dear all, This may sound stupid to ask, but I am very frustrating now as my deadline is approaching. I want to make use of the VGA generator example on www.xess.com. How could I write/read data to the specific address of the SRAM? I would have to have a SRAM controller that writes and reads data to the SRAM? How should that be implemented in VHDL? What else do I need? I am planning to hard code the data to SRAM. Thank you very much!!!Article: 80334
I'm using the right clock pins (if I understand the data sheet correct)! ... and this is the behaviour I don't understand :-( Manfred "Peter Sommerfeld" <psommerfeld@gmail.com> schrieb im Newsbeitrag news:1109868595.866357.224240@g14g2000cwa.googlegroups.com... > Hi Manfred, I'm not familiar with Apex too much but I know on Stratix > certain PLL can ONLY be instatiated with certain dedicated clock pins, > ie. the PLL # has to match the clock pin, otherwise a no-fit occurs. I > suspect this is your problem. Check the Apex docs, or swap the clock > pins that feed your PLLs. > > HTH, Pete >Article: 80335
Why not use the the personality module connector? These are described in the user guides http://www.xilinx.com/products/boards/ml310/current/pcb/sch/ug068.pdf For example, PM2 (pg 65 of the users guide) has 39 LVDS pin pairs that can also be used as 78 single ended pins, so more than the 50 you are looking for. The PCI is directly connected to the FPGA but the ALi south bridge, the PCI2PCI bridge, the Ethernet, and two PCI slots are sitting on that bus making it difficult to use for anything else than PCI. - Peter Wing Fong Wong wrote: > To those that are familiar with this board, > I need about 50 or so digital io lines with a max bit rate of about 1Mb > per second. I was considering using the PCI slot, but since I don't really > want to build a full PCI compliant board, I was wondering whether if it is > possible to comfigure as I want? Secondly are the data and address line > directly connected to the FPGA, it seem to appear so the the block diagram > but there seems to be a lot of passive components around the slots. >Article: 80336
you can download xilinx sdram controller here- ftp://ftp.xilinx.com/pub/applications/xapp/xapp134_vhdl.zip and tune it to your requirement.Article: 80337
Hallo at first thank you for replay @Andrea Sabatini yes, all the libraries were there. But he sais that there are note there :-( @Moti Cohen I tried your tip. The errors were there but another ones. Now he find not the packages which were defined in my testbench. Then i do somethink, but i don't know what, and the simulator runs :-) But after i do this "simulate post-translate VHDL model". And now the "simulate behavioral model" runs too. Many Thanks !!!!Article: 80338
I've been involved in a tool for software development for just these sort of architectures. It turns out that the hardware design of Transputer-style connected multiprocessors is relatively simple, but the software development can be a challenge. The good news is that with all on-chip communication, you can exploit parallelism that board-level multiprocessors can't. Have a look at http://www.cmpware.com/ for more info. (This is aimed at ASIC folks, but FPGAs work, too. In fact, NIOS I, NIOS II and microblaze models are already available). -- Steve -- 3/3/05Article: 80339
Dear Goran, it is more clear now. Thank you! SergioArticle: 80340
Dear all, I'm using a Virtex2-Pro with a multiprocessor system based on the MicroBlaze processor. My interest is in a comparison of several bus architectures, and for these reasons I need a methodology to perform such tests. I can simulate my whole system with modelsim, and then analize the waveforms of the OPB bus, but I think it is not the powerful way. What other methodologies can you suggest me? For example I know that SeamLess-FPGA (Mentor-Graphics) has a "Performance Analysis" feature but unfortunately for now it supports only the PowerPC. The MicroBlaze version will be ready not before the Q3 of this year. Thank you! SergioArticle: 80341
Peter Ryser <peter.ryser@xilinx.com> wrote: > Why not use the the personality module connector? These are described in > the user guides > http://www.xilinx.com/products/boards/ml310/current/pcb/sch/ug068.pdf > > For example, PM2 (pg 65 of the users guide) has 39 LVDS pin pairs that > can also be used as 78 single ended pins, so more than the 50 you are > looking for. > > The PCI is directly connected to the FPGA but the ALi south bridge, the > PCI2PCI bridge, the Ethernet, and two PCI slots are sitting on that bus > making it difficult to use for anything else than PCI. > > - Peter > > > And are the PM ports suited to low speeds( less than 1Mb per second)? -- Wing Wong.Article: 80342
I have a doubt. when I create a signal like this: signal abc std_logic_vector(3 downto 0); after, when I write: abc <= abc + 1; if abc was 000, now which is? 001 or 100 ???? Many Thanks MarcoArticle: 80343
Carsten wrote: > Jens .. reconsider the Digilent .... > > If you go there , select the starterkit , click add to chart you get > opportunity to select/upgrade to the new 2 boards they have. > > Upgrade to a S3-400 for $20 > Upgrade to a S3-1000 for $50 > > Wish the S3-1000 was there when i bought from Xilinx You are not the first to suggest a bigger FPGA. Since I'm new to FPGA development, I'm not sure, how many gates are necesseary. What kind of device did you build, which did not fit into an S3-200? How many gates would the Microblaze require, just as an example? JensArticle: 80344
Hi Sergio, What do you want to measure? Göran sergio.tota wrote: > Dear all, > > I'm using a Virtex2-Pro with a multiprocessor system based on the > MicroBlaze processor. > > My interest is in a comparison of several bus architectures, and for > these reasons I need a methodology to perform such tests. > > I can simulate my whole system with modelsim, and then analize the > waveforms of the OPB bus, but I think it is not the powerful way. > > What other methodologies can you suggest me? > > For example I know that SeamLess-FPGA (Mentor-Graphics) has a > "Performance Analysis" feature but unfortunately for now it supports > only the PowerPC. > The MicroBlaze version will be ready not before the Q3 of this year. > > Thank you! > > Sergio >Article: 80345
I have a spartan 3 starter kit board. I need to generate a clock of 1,5MHz. It has an analog oscillator at 50Mhz. What should I do? I thought to multiply 50Mhz for 3 then divide for 100, but in what way I can realize that? Now, as clock signal I have BUS2IP_CLK, from OPB BUS. In what way I can connect to analog oscillator? Many Thanks MarcoArticle: 80346
"Gabor" <gabor@alacron.com> wrote in message news:<1109889767.823586.126100@z14g2000cwz.googlegroups.com>... > Falk Brunner wrote: > > "Richard Thompson" <nospam@nospam.com> schrieb im Newsbeitrag > > news:sqva219fvdhe8j9omvmpknfl2kl7ijrvkl@4ax.com... > > > > > >After all, what is a RS-FF good for nowadays?? > > > > > > The same things that it has always been good for. For a cost of 2 > > > gates, it gives you a memory. It doesn't need a clock. It remembers > an > > > event until you have time to deal with it. It's ideal for > handshaking, > > > and for communicating between different clock domains. Can you name > > > any other digital circuit which is so versatile, at such a small > cost? > > > Even if you ignore the 'cost', as you might do in an FPGA > > > implementation? > > > > Uhhh? COST??? C'mon. In a FPGA, a handfull of Flipflops is always > free. So > > why asking for trouble and doing stone age handshakes when there are > proven > > solutions using standard methods (here, D-FlipFlops)? I wouldnt waste > a > > nanosecond thinking of RS-FlipFlops made of gates. > > Speaking of cost, is a LUT less costly than a flip-flop? In Xilinx > Virtex parts, a LUT can be 16 flip-flops sometimes. Besides if you > want both gate outputs from your cross-coupled NAND gates you need > 2 LUTs. > > Another thing to wonder about, is whether changing a single > LUT input creates the same output transition as with the implemented > gates. For example if the output is the same for both states of the > switched input, a gate will never glitch, but will the LUT glitch? > This may depend on the implementation of the output multiplexer. > > > > > Regards > > Falk Although this is not directly related to the current SR latches discussion, let me expose a problem that forced me to define a VHDL equivalent of the good old 7474 flip-flop made with NAND gates and a set of KEEP attributes on the signals. Although it may be questionable to do so, once you try to synthetize a flip-flop with such an expression as "If Rising_Edge(Signal_In) Then ...", where Signal_In is not supposed to be a general clock at all, the synthesis tool generally reserves a global clock chain and buffer for just that purpose. This may be a real problem if the number of times you want to do that (because for instance you need to have a very quick reaction on the rising edge of a signal) gets significant vs the number of available GCLK nets and buffers. Pardon me if I am presently missing a very simple way to tell the tool "Please do not use one of your GCLK resources", but I am not a very frequent user of VHDL and had no chance to go to any advanced seminar of any kind. A solution to that problem ? Please answer if you are aware of some.Article: 80347
Ah, you have to try and work in powers of two! How accurate do you need the clock to be?? You could just divide by 32... Giving 1.5625 MHz. Ben "Marco" <marcotoschi@email.it> wrote in message news:ee8c67f.-1@webx.sUN8CHnE... > I have a spartan 3 starter kit board. > > I need to generate a clock of 1,5MHz. > > It has an analog oscillator at 50Mhz. > > What should I do? > > I thought to multiply 50Mhz for 3 then divide for 100, but in what way I can realize that? > > Now, as clock signal I have BUS2IP_CLK, from OPB BUS. > > In what way I can connect to analog oscillator? > > Many Thanks MarcoArticle: 80348
Neo wrote: > you can download xilinx sdram controller here- > ftp://ftp.xilinx.com/pub/applications/xapp/xapp134_vhdl.zip > and tune it to your requirement. Well, it would take a lot of tuning to access SRAM with an SDRAM controller. ;-) Kolja SulimmaArticle: 80349
I need to perform an operation to calculate ram address. I have created a RAM with core generator, and added to my project. Using this command: address <= alfa + beta * gamma; When I make synthesis I receive an error message. address what kind of type shuold be? I have declared it as: std_logic vector. Is it correct? Many Thanks Marco
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