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vax, 9000 wrote: > Hi list, > I don't have ethernet connection though I do have an ethernet card > installed. My computer can boot either with linux or win XP. I have dial > up connection under linux only. I downloaded ALTERA software version 4.2 > (yeah, overnight dialup), obtained the license (with an arbitrary ethernet > number), and copied the files to windows partition and installed. > The problem is now that under XP, when I run the software it does not > think the license is a valid one. My question is whether I really need > ethernet connection under XP to run ALTERA. If I obtain another license > with the correct ethernet card number I have, will this license be valid > when I don't really have ethernet connection? > Too tired today to do the experiment. I will appreciate it if you have a > quick answer. Otherwise I will have to do the experiment and report the > result here. Thanks to those who replied. I today obtained under linux a new license file using the correct ethernet card mac number, and the license file works correctly under XP. vax, 9000 > > vax, 9000Article: 81126
Mike Treseler wrote:
> vax, 9000 wrote:
>
>> 5. The software gives warnings about latches. I use latches for input
>> registers ("if HOST_WR='0' then REG <= HOST_DATA"). Do I need to change
>> them into clocked registers ("if HOST_WR'event and HOST_WR='1' then
>> REG<=HOST_DATA")?
>
> Yes, but consider using the same clock for all of your registers.
> Use the D and CE inputs for logic.
I did this to most of the circuit including the state machines. But there is
one place that this rule does not apply, that is when I use a slow host CPU
bus to write to some configuration registers in the FPGA.
Wait, maybe it applies. like this,
process (HOST_WR)
begin
if HOST_WR'event and HOST_WR='1' then
if HOST_CS = '0' then
REG <= HOST_DATA;
end if;
end if;
end process;
I just want to know whether this is better than the following approach,
HOST_CS_WR <= HOST_WR or HOST_CS;
process (HOST_CS_WR)
begin
if HOST_CS_WR'event and HOST_CS_WR='1' than
REG<= HOST_DATA;
end if;
end process;
Is there a well-known best approach to this problem? It might look trivial
to some but I am really confused. Now I have 10 such registers, then which
approach is better? Thanks.
vax, 9000
>
>> I see no advantage of clocked register here, since my
>> target FPGA's cell has both async input pin and clock pin.
>
> I expect that you will someday.
>
> -- Mike Treseler
Article: 81127
Hi..
I dunno If I am correct or not..But what I think is that u r
having path problems I guess...
--
Parag Beeraka
Article: 81128Herb T wrote: > Where to find Tutorials for using Xilinx FPGA? > How to learn about Xilinx FPGAs, use ISE 6.3i and EDK 6.3i tools? Start the software. In the menu, find Help -> Tutorial. Then follow the tutorial step by step. No need to read data sheet, since you are not working on somehow difficult work for a software guy, such as, designing system, evaluating whether the chip fits your need, designing off chip logic, interfacing the chip, designing PCB... vax, 9000 > > Folks, > I am trying to learn how to program Spartan II (XC2S100-5PQ208C) and > Spartan 3 (XC3S400-4PQ208C) Xilinx FPGAs. I looked at the data sheets > for these parts, and the more I do the more mystified I get. I have > never done this before. I come from a software background, but have > dabbled in hardware a little. I would like to learn how to program, > design, and add external hardware to FPGAs. What is the best way to go > about this? > > I have looked at some of the documents related to ISE and EDK, but have > not been able to understand a great deal because of the different > terminology and concepts they use (e.g. OPB v2.0 bus, Slices, Pulse > Width Modulation). These ideas have little meaning to me having never > seen them before. I did see the training classes on the web, but don't > have $20K to shell out to take them all, being a broke chump and all. > > Anyway I have the ISE and EDK 6.3i tools, and have been trying to read > the documentation, but again I have the same issues. > > Based on these descriptions, about how long does it take to write > simple VHDL programs that work, or become fluent enough to know a good > design from a chip fryer? > > Thanks, > -HTArticle: 81129
Paul Leventis wrote: > Our DSE guys are equally confused. Things are working fine for us... > > For us to be able to completely debug your issues we need see your > design, or at least the full DSE output logs (*.dse.rpt) with the > -debug flag on. I'd be happy to, but pardon my ignorence, can I set the -debug though the gui? Here's how the it looks when it stops: http://numba-tu.com/DSE.png > We tried using seeds in the form n1-n2 and it seemed to work fine for > us on 4.2 SP1. Maybe you can try separating your seeds with commas in > case there is something weird there. I my case I've never touched it and it's at the default value: 3 5 7 11 > Another possibility is that your > base compile has an error or no-fit, which causes compilation to halt > in a similar way to what you describe. Not the case AFAICT. I compile the project before launching DSE (it appears I have too). I'll send you (personally) a link to the whole directory in case it's helpful (any comments or questions most welcome). Thanks, TommyArticle: 81130
I think the basic idea is that if you have a 51-tap FIR filter, for example, you need to do 51 multiplies per sample. The two extremes of the size/speed options are: 1. Use one multiplier 51 times sequentially. 2. Use 51 multipliers in parallel. #1 is ~51 times smaller that #2, but #2 operates 51 times faster that #1. I didn't read the paper, but that's the classic tradeoff. "anup" <anuphosh@yahoo.com> wrote in message news:1111108957.746307.323560@g14g2000cwa.googlegroups.com... > Hi Eric, > > Thank you for your response. I guess I did not frame my question > properly. Your answer actually strengthens my doubt. According to what > you said, by using more pipeline stages, you can increase the sampling > speed. > > But I read this article, where they use more resources to make use of > the parallelism in the application (FIR filters), and reduce the > latency. But they claimed that the sampling speed is also increased. My > doubt is that, even in the original design (with fewer resources), you > can achieve higher sampling speed by pipelining the design. > > One relation I see between "more resources" and "sampling speed" is > that you need fewer pipeline stages to achieve higher sampling speed. > For example, consider this computation: > > Y = Y + A[i]*X[i]; > > Assume that I have only 2 adders. I can implement this as > > Y1 = A[i]*X[i] + A[i+1]*X[i+1]; | Y = Y + Y1 > > Assume that it takes 10 ns to do (A[i]*X[i] + A[i+1]*X[i+1]); > Therefore, without pipelining the adder, I can achieve sampling of 200 > million samples per second. > > Now suppose, I have 4 adders, I can do > > Y1 = A[i]*X[i] + A[i+1]*X[i+1]; | | > | Y' = Y1 + Y2 | Y = Y + Y' > Y2 = A[i+2]*X[i+2] + A[i+3]*X[i+3]; | | > > Now I can achieve a sampling of 400 million samples per second. > > The original system (with 2 adders) can also achieve the same sampling > speed, if the adder is pipelined. I guess that if there is a limit on > the amount of pipelining that you can do, adding more resources is the > way to increase sampling speed. (I am trying to answer my own question > here) > > Anyways, thanks for your help. > > -Anup >Article: 81131
Robert Monsen wrote: > Sea Squid wrote: >> I found PP is unable to drive such LEDs, which needs 20mA, but what is >> the converter chip I shall order? >> >> Thanks >> > > Look here: > > http://www.logix4u.net/parallelport1.htm > > There is a schematic for doing exactly what you want to do. > > (comp.arch.fpga?) Off the top of my head I would say a 500-1K Ohm resistor in series, and the schematic here is using 1K. If you try to connect directly without a resistor it will work but you could harm your PC. gtoomeyArticle: 81132
there was an author with name 'ray andraka' wrote a paper on this topic. his company is called andraka consulting. "anup" <anuphosh@yahoo.com> wrote in message news:1111108957.746307.323560@g14g2000cwa.googlegroups.com... > Hi Eric, > > Thank you for your response. I guess I did not frame my question > properly. Your answer actually strengthens my doubt. According to what > you said, by using more pipeline stages, you can increase the sampling > speed. > > But I read this article, where they use more resources to make use of > the parallelism in the application (FIR filters), and reduce the > latency. But they claimed that the sampling speed is also increased. My > doubt is that, even in the original design (with fewer resources), you > can achieve higher sampling speed by pipelining the design. > > One relation I see between "more resources" and "sampling speed" is > that you need fewer pipeline stages to achieve higher sampling speed. > For example, consider this computation: > > Y = Y + A[i]*X[i]; > > Assume that I have only 2 adders. I can implement this as > > Y1 = A[i]*X[i] + A[i+1]*X[i+1]; | Y = Y + Y1 > > Assume that it takes 10 ns to do (A[i]*X[i] + A[i+1]*X[i+1]); > Therefore, without pipelining the adder, I can achieve sampling of 200 > million samples per second. > > Now suppose, I have 4 adders, I can do > > Y1 = A[i]*X[i] + A[i+1]*X[i+1]; | | > | Y' = Y1 + Y2 | Y = Y + Y' > Y2 = A[i+2]*X[i+2] + A[i+3]*X[i+3]; | | > > Now I can achieve a sampling of 400 million samples per second. > > The original system (with 2 adders) can also achieve the same sampling > speed, if the adder is pipelined. I guess that if there is a limit on > the amount of pipelining that you can do, adding more resources is the > way to increase sampling speed. (I am trying to answer my own question > here) > > Anyways, thanks for your help. > > -Anup > > Eric Smith wrote: > > "anup" <anuphosh@yahoo.com> writes: > > > I am confused about this. According to me, if you pipeline the > design, > > > you can achieve the sampling speed you want. I can see how using > more > > > resources, you can achieve shorter latency, but the sampling speed > > > should not be affected. There is probably something I am missing > here. > > > > Adding pipelining is usually done to reduce the cycle time > (increasing > > the clock rate) while also increasing the latency. > > > > Suppose you wanted to build a floating-point multiply-and-add > > unit. Perhaps if you make it fully combinatorial, it takes > > 100 ns for each cycle. You can process ten million samples per > > second, and the latency is 100 ns. > > > > Suppose instead you break it up into a pipeline with a combinatorial > > multiplier, a pipeline register, and a combinatorial adder. Suppose > the > > multiplier and adder each take 60 ns separately, and the pipeline > > register setup and clock-to-output-valid time adds 10 ns. Now your > > latency (full operatin time) is 130 ns, which is longer. But your > > sample clock can be as fast as 70 ns, so you can process over > fourteen > > million samples per second. > > > > Now suppose you internally pipeline the actual adder and the > multiplier. > > Perhaps each have three stages that take 20 ns each, and you still > have > > 10 ns of delays for combined setup and clock-to-output-valid time of > the > > pipeline registers. Now you have a latency of 170 ns, which is > longer > > yet. But your sample clock can now be 30 ns, so you can process over > > thirty million samples per second. > > > > Note that the times used in this example are probably not > representative > > of real times for any actual system. > > > > Eric >Article: 81133
pasacco wrote: > The implementation will looks like above. > > uBLAZE1 uBLAZE2 > | | > MMU (switch) MMU (switch) > | | > |---------------------OPB--------------------------| > | | > BRAM 1 (16kB) BRAM 2 (16kB) > > The assembly programmer should see the memory as 32 KB global memory. > The role of MMU will be to translate the address and decides which (one > of both) memory should be accessed. It does not matter the address > range of each memory. I need some help. Thankyou very much for some > hint on how to realize this.... > Hi, This picture shows the connections, thanks. So you want them so see this memory differently. uBlaze1 - BRAM1 0x0000-0x3fff - BRAM2 0x4000-0x7fff uBlaze2 - BRAM2 0x0000-0x3fff - BRAM1 0x4000-0x7fff Is this the address map that you want? GöranArticle: 81134
John wrote:
> I'd like to see a unified Verilog C language which looks like either &
> both but with most of the useless stuff thrown out, ie a cycle/event C
> with Verilogs expressiveness that is synthesizeable when using that
> syntax and not when using the C syntax.
So would I. Do you have any examples of how that would look?
How about the Timogriffer-C model where all computation goes infinitely
fast, but the program can wait for the next clock edge, eg. something
like (thought experiments)
input int rst:1;
output int led:8;
counter()
{
for (;;) {
if (rst)
led = 0;
else
++led;
WAIT;
}
}
Another example, a FIFO
input wren:1, rden:1;
input wd;
output rd;
output full:1;
int fifo[32], rp:5, wp:5;
run_fifo()
{
for (;;) {
if (rst) {
rp = 0; wp = 1;
} else {
par {
if (rden) rd = fifo[rp++];
if (wren) fifo[wp++] = wd;
}
full = wp == rp;
empty = wp == rp+1;
}
WAIT;
}
}
The par {} construct is inspired by Handel-C, but Handel-C has a very
odd model where there's essentially an implicit WAIT after each
statement, thus making it very hard and unnatural to describe
non-trivial circuits that happens between two clock edges.
Of course this example doesn't make up of bit extract, concatenation,
and replication, but there's no reason it couldn't be there.
Or did you have something else in mind?
Tommy
Article: 81135
Hello,
I am doing my thesis on Xilinx ML310 board. My target is to
realise the real-time image processing. First I have to find the port
where I can input the captured data. I am going to use the usb port on
MD1535D+ south bridge. To access this south bridge I need to access
the PCI bus since it is connected to the PCI. I have installed the
PCI v3.0 logicore but when I create a project, I can't find this PCI
v3.0 logicore to add into my project. Does anyone know how to access
this PCI v3.0 logicore?
Much appreciate for your kindly help!
Article: 81136Hi, I'm thinkin go of designing a heating/cooling system with VHDL and need to interface my Spartan 3 board to a real temp sensor. Does anyone have an idea of how I can do this? Thanks!!Article: 81137
On Thu, 17 Mar 2005 14:57:23 +0800, "Sea Squid" <Sea.Squid@hotmail.com> wrote: >I want to experiment the parallel port with eight LEDs tied to >a cut parallel port cable, then send instructions with Visual Basic >to create some patterns. Is there any danger to my laptop? > >Thanks. > > > Have a look at http://www.boondog.com I also recommend Paul Bergsman's book "Controlling Your World With Your PC" ISBN 1-878707-15-9Article: 81138
more <fengmingxin_714@hotmail-dot-com.no-spam.invalid> wrote: > Hello, > > I am doing my thesis on Xilinx ML310 board. My target is to > realise the real-time image processing. First I have to find the port > where I can input the captured data. I am going to use the usb port on > MD1535D+ south bridge. To access this south bridge I need to access > the PCI bus since it is connected to the PCI. I have installed the > PCI v3.0 logicore but when I create a project, I can't find this PCI > v3.0 logicore to add into my project. Does anyone know how to access > this PCI v3.0 logicore? > > Much appreciate for your kindly help! > Hey, I doing pretty much the same thing, image processing on the ML310! Unlike you, I decided to use the personality module connectors. The connectors appear to connect directly to the FPGA. Its simpler to use that than USB, unless of course your data source is being streamed via USB then its a whole different story. As a side not does anyone know where I can get Tyco's Z-Dok connectors that are used in the ML310? I need the recepticals. -- Wing Wong.Article: 81139
On Thu, 17 Mar 2005 14:57:23 +0800, "Sea Squid" <Sea.Squid@hotmail.com> wrote: >I want to experiment the parallel port with eight LEDs tied to >a cut parallel port cable, then send instructions with Visual Basic >to create some patterns. Is there any danger to my laptop? > >Thanks. > > > I highly recommend a book by Paul Bergsman "Controlling THe World With Your PC" ISBN 1-878707-15-9 Also,have a look at http://www.boondog.com .Article: 81140
Does anybody happen to have the BSDL files for Qualcomm MSM (CDMA mobile station modem chips) : MSM3000,MSM3100,MSM5000,MSM5105,MSM5200,MSM5500,MSM6000,MSM6025,MSM6050,MSM6100,MSM6150,MSM6200,MSM6225,MSM6250,MSM6255,MSM6275,MSM6280,MSM6300,MSM6500,MSM6550,MSM6600,MSM6700,MSM6800,MSM7000,MSM7200,MSM7500,MSM7600 ? I would appreciate it very much if you could share them with me. I can send you any of the EIA/TIA standards listed on this web page : http://jupiter.drw.net/mercedes/telecom/index.files/English/english.html My e-mail : usenet1@superbank.ru Alexander Firsov (Moscow, Russia). Tel. +7-095-7294659Article: 81141
rgebru wrote: > Hi, > > I'm thinkin go of designing a heating/cooling system with VHDL and > need to interface my Spartan 3 board to a real temp sensor. Does > anyone have an idea of how I can do this? > > Thanks!! There are several temperature sensors with i2c interface. They should easily be connected to your board. http://www.google.de/search?hl=en&q=i2c+temperature+sensor JensArticle: 81142
"Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:1111083250.701659.304200@o13g2000cwo.googlegroups.com... > Hi Doug, Tommy: > > > Strange. > > Our DSE guys are equally confused. Things are working fine for us... > > For us to be able to completely debug your issues we need see your > design, or at least the full DSE output logs (*.dse.rpt) with the > -debug flag on. > > We tried using seeds in the form n1-n2 and it seemed to work fine for > us on 4.2 SP1. Maybe you can try separating your seeds with commas in > case there is something weird there. Another possibility is that your > base compile has an error or no-fit, which causes compilation to halt > in a similar way to what you describe. > > Regards, > > Paul Leventis > Altera Corp. > Paul, I submitted a mysupport SR two weeks ago and I am waiting for some support to help me out here. (SR#10490208) I attached lots of reports and my design. I talked to one of the engineers at mysupport late yesterday and they said they are now bumping it up to the higher level engineers. Any help you can provide will be greatly appreciated. I was not aware of the -debug flag. I will attempt to run DSE with this flag on and get another update to the mysupport engineers. Also, my design does fit. There is no "no-fit" error. That would at least produce an error message. In my case there is no error message. Thanks for your help Paul, DougArticle: 81143
"Tommy Thorn" <foobar@nowhere.void> wrote in message news:423A707D.1030808@nowhere.void... > Paul Leventis wrote: > > Our DSE guys are equally confused. Things are working fine for us... > > > > For us to be able to completely debug your issues we need see your > > design, or at least the full DSE output logs (*.dse.rpt) with the > > -debug flag on. > > I'd be happy to, but pardon my ignorence, can I set the -debug though > the gui? > > Here's how the it looks when it stops: http://numba-tu.com/DSE.png > > > We tried using seeds in the form n1-n2 and it seemed to work fine for > > us on 4.2 SP1. Maybe you can try separating your seeds with commas in > > case there is something weird there. > > I my case I've never touched it and it's at the default value: 3 5 7 11 > > > Another possibility is that your > > base compile has an error or no-fit, which causes compilation to halt > > in a similar way to what you describe. > > Not the case AFAICT. I compile the project before launching DSE (it > appears I have too). > > I'll send you (personally) a link to the whole directory in case it's > helpful (any comments or questions most welcome). > > Thanks, > Tommy Tommy, I took a look at how it looks when it stops for you, and that is the same thing that I see, except my compile time is more like 2-4 hours. DougArticle: 81144
Hello Greg, >>>So I made a simple test file, only 1 line, type boolean, between 2 >>>Gateways. I can generate the ISE project. In ISE I try to implement, but >>>the 2 signal names of the gateways cannot be found. >>> >>> > >When you double-click on an output gateway, does "Translate into >Output Port" have a checkmark by it? If not, then the port, and >everything connected to it, is removed by the optimizer. > > > the checkmark is set, but nevertheless it doesn't work. In the generate process there is no error message. But in ISE the synthesizing process stops with errors: ERROR:Xst:1370 - Line 6: Signal name gin2 not found in design. ERROR:Xst:1370 - Line 7: Signal name gout1 not found in design. ERROR:Parsers:11 - Encountered unrecognized constraint while parsing. ERROR:Xst:1341 - XCF parsing failed ERROR: XST failed But I can see the "optimized" circuit in RTL-viewer. Very strange, there are 8 input and 8 output data lines, in between 8 D-FFS FDE. In Simulink I have only one line type boolean. When I change line type to 1 bit unsigned integer, it changes nothing. I don't know what to do. Regards, WinfriedArticle: 81145
Hi, I am using JTAG Cable IJC-2 from Memec and Xilinx Platform Studio (Xilinx EDK 6.3 Build EDK_Gmm.12.3+1) to program subj. Typically in the morning, the programming fails constantly until it suddenly works after an hour or two. When it then works, it keeps working. For that reason i beleive my code is OK. ;-) When it does not work, i get this error: --- INFO:iMPACT:580 - '2':Checking done pin ....done. '2': Programming terminated, Done did not go high. Elapsed time = 21 sec. --- I tried to change port type on my LPT-port to all possible modes. I shortened the cable between JTAG module and board to approx. 5 cm, using a ribbon cable with GND between all wires. I can provoke the error by unplugging the board from the PSU for about 5 mins. But I can't seem to find a way to get it working again - other than swinging the cat by its tail and then it suddenly works. I hope that someone in here have any bright ideas. :) The entire log from Xilinx Platform Studio is pasted here, if needed: --- (Console Log) PM_SPEC -- Xilinx path component is <C:/EDK> Project Opened. At GMT date and time: 2005:3:18:10:30:41 Command bash -c "cd /xygdrive/c/Xilinx/Workshops/MB1000_Web_Server_Design_EDK63/MB1000_Web_Server/; /usr/bin/make -f system.make download; exit;" Started... ********************************************* Downloading Bitstream onto the target board ********************************************* impact -batch etc/download.cmd PM_SPEC -- Xilinx path component is <C:/EDK> // *** BATCH CMD : setMode -bs // *** BATCH CMD : setCable -port auto AutoDetecting cable. Please wait. No resources. No resources. Connecting to cable (USB Port). Cable connection failed. Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 6.2.2.2. LPT base address = 0378h. ECP base address = FFFFFFFFh. Cable connection established. // *** BATCH CMD : identify Identifying chain contents ....Version is 0010 '1': : Manufacturer's ID =Xilinx xc2v1000, Version : 2 INFO:iMPACT:1777 - Reading C:/Xilinx/virtex2/data/xc2v1000.bsd... INFO:iMPACT:501 - '1': Added Device xc2v1000 successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- Version is 0000 '2': : Manufacturer's ID =Xilinx xc18v04, Version : 0 INFO:iMPACT:1777 - Reading C:/Xilinx/xc18v00/data/xc18v04.bsd... INFO:iMPACT:501 - '1': Added Device xc18v04 successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- done. Elapsed time = 0 sec. // *** BATCH CMD : identifyMPM Elapsed time = 0 sec. // *** BATCH CMD : setAttribute -position 2 -attr configFileName -value "implementation/download.bit" '2': Loading file 'implementation/download.bit' ... done. INFO:iMPACT:501 - '2': Added Device xc2v1000 successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- ---------------------------------------------------------------------- // *** BATCH CMD : program -p 2 Validating chain... Boundary-scan chain validated successfully. '2':Programming device... '2': Reading status register contents... INFO:iMPACT:2146 - Status register values: INFO:iMPACT - 0011 0000 0001 0000 0000 0000 0000 0000 done. INFO:iMPACT:579 - '2': Completed downloading bit file to device. INFO:iMPACT:580 - '2':Checking done pin ....done. '2': Programming terminated, Done did not go high. <----- Elapsed time = 21 sec. ---------------------------------------------------------------------- ---------------------------------------------------------------------- make: *** [download] Error 1 Done. ---Article: 81146
Marc,
DDC stand for Down Digital Convertor (DSP core)
Aurash
Marc Randolph wrote:
>Nemesis wrote:
>
>
>>Mentre io pensavo ad una intro simpatica "Jim George" scriveva:
>>
>>
>>
>>>>Hi everyone,
>>>>I'm going to buy Xilinx ISE Foundation, I'd like to know if this
>>>>
>>>>
>package
>
>
>>>>contains also IP cores like DDC, FFT and so on.
>>>>It seems that the "LogiCore" IPs should be shipped within ISE
>>>>Foundations, am I right?
>>>>
>>>>
>>>Yes, ISE Foundation comes with Coregen.
>>>
>>>
>>Thanks, I'm still trying to found a complete list of the IP shipped
>>
>>
>with
>
>
>>ISE. I found at least on LogiCore IP wich is not given for free (the
>>
>>
>PCI
>
>
>>IP).
>>
>>
>
>Howdy,
>
> I looked everywhere I could think of and could not find a list of
>which cores cost money and which are included with Core gen.
>
>I don't know what DDC is (did you mean DCT, in which case there are 1-D
>and 2-D DCT's included). There are a number of different FFT's
>included with Coregen as well.
>
>Good luck,
>
> Marc
>
>
>
--
__
Article: 81147Hi henrik I am not sure but is this got something to do with the DONE pin not going high. I dont know abt platform studio but then with Project navigator there is a setting which drives the done pin high that is if the done pin in the circuit is not connected to a pullup resistor. Hope this helps.Article: 81148
Aurelian Lazarut wrote: > Marc, > > DDC stand for Down Digital Convertor (DSP core) Ahhh, yes - thank you. RF is a little out of my field... my telecom experience revolves around wireline and fiber, so to stops a little short of the base-stations. And thank you to Stephan Neuhold for pointing out where Xilinx has put up a comprehensive list of their cores online. Have fun, MarcArticle: 81149
Szukam sposobu implementacji kolejki fifo o dlugosci 512 bajtów .... jak sie do tego zabrac??
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