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<aosik5@gmail.com> wrote in message news:1112127765.083272.105280@z14g2000cwz.googlegroups.com... > hello, I'm about to layout a circuit for a pcb that includes the Xilinx > spartan II-e and external circuitry (simple interface elements), I was > wondering if anyone has laid out a PCB using the chip, because I know > there are a lot of capacitors and resistors and other elements that are > on the development board, and I am not sure what needs to be transfered > and what doesn't.. > > George Firstly, re read your question. How do you expect a sensible answer with the minute amount of detail you provide ! Anyway, it is better to understand what is going on than copy blindly. Lets play 'twenty questions'. Do you know what a ground plane is ? Do you understand what is meant by decoupling - what are all those capacitors and resistors for anyway ? How many layers will your pcb have ? What is your clock speed ? How will your chosen clock speed affect your layout ? Have you simulated your design - do you know whether it will meet your timing constraints with the pinout you are about to commit to ? What are you interfacing to - how long and what type of interconnects are used ? There are lots of articles and Application Notes on topics like these - read and enjoy ! DaveArticle: 81676
I'm a Verilog guy and your question is for VHDL - it would be great if a VHDL guy gould give the proper code snippets. The question is addressed in general: "genlock" <genlocks@gmail.com> wrote in message news:1112131201.352597.22410@g14g2000cwa.googlegroups.com... > Yes the decimal number is a constant value. For the example of division by 1.36, multiplying by (2^24/1.36) and taking the 24 MSbits of the result, you get an "effective" division. If you generate the "reciprical integer multiplier" from real literals and do a type conversion to std_logic_vector, the multiply would follow as a simple multiply. Then just shift or select the upper bits and you have your result. > What do you mean by embedded multipliers? The modern FPGAs tend to have multipliers as part of the logic fabric. You're using ISE so my expectation is you're using a Virtex(-E)Virtex-II(Pro), Virtex-4, Spartan-II(E), or Spartan-3/3L/3E. These should all have multipliers if memory serves me right. Check the data sheets. > Is there a VHDL code available for that or how do we go about coding > one. I'd like to see someone on this newsgroup provide you a snippet to do (roughly) what I suggest. If you wanted Verilog, it'd be something like result[23:0] <= In[23:0] * ((1<<24)/1.36 + 0.5) >> 24; but I haven't used real variables in my code much if at all. I think this would synthesize. > I dont need a clock for this one. > > ThankyouArticle: 81677
Hi, Thanks for the schematic. So do you have application notes on how to interface with this sram? Is there a module in your FPGA design that interface with this sram? Thanks, AnnArticle: 81678
mmkumar@gmail.com wrote: > hi, > in ise, the console window says "synthesis completed" but in the > process for source, it still shows a question mark instead of an > exclamatory mark(excla.. mark for synthesis complete).ans when u click > sysnthesis report , it start the synthesis process all over again..if > any one knows,pls let me know. > > ~Mack. Normally the synthesis only re-starts if the source has changed or the flow did not finish. One possible cause has been discussed here before. If at least some of your source files are not on the same computer you use for synthesis, the file system dating can cause ISE to think the source is newer than your most recent build.Article: 81679
Can you explain this logic that you have mentioned in more detail? I am using Xilinx ISE and when I try doing any division or multiplication, it keeps showing an error as follows: / can not have such operands in this context. ERROR: XST failed a)What I am trying to do is first convert the 24 bit vector to an integer. b)Then figure out a method to divide this integer by 1.36 that gives the result as an integer c)This integer is converted back to a 24 bit vector Any idea about how this division (b)can be performed? ThankyouArticle: 81680
In article <1112136150.388063.56450@g14g2000cwa.googlegroups.com>, genlock <genlocks@gmail.com> wrote: >Can you explain this logic that you have mentioned in more detail? > >I am using Xilinx ISE and when I try doing any division or >multiplication, it keeps showing an error as follows: > > / can not have such operands in this context. Why not just use the explicit number 12336188, with a comment that it's the nearest integer to 2^24/1.36? TomArticle: 81681
No, but... You can Synthesis the project from the command line. Create a batch file. a) run your mif creator. b) run Quartus (-sh I believe) c) run programmer Note Quartus returns ErrorLevels unlike ISE. Read the Scripting manual (its new with 4.2?) And document it, so that when it breaks someone else can fix it for you. ;D Cheers "Gary Pace" <xxx@yyy.com> wrote in message news:PKf2e.41588$Ux.8035@tornado.texas.rr.com... > Hi y'all : > > We create our .mif files by running a custom analysis program on a set of > data files. > > I'd like to include this in the compile process. > > Whilst I can find interfaces to various EDA tools, I can't find a "just run > this program prior to compilation" option > > Is this possible ? > > Thanks > Gary > >Article: 81682
Thanks. "Martin Riddle" <martinriddle@hotmail.com> wrote in message news:ism2e.34230$ed6.26341@trndny06... > No, but... > You can Synthesis the project from the command line. > > Create a batch file. > a) run your mif creator. > b) run Quartus (-sh I believe) > c) run programmer > > Note Quartus returns ErrorLevels unlike ISE. Read the Scripting manual > (its new with 4.2?) > > And document it, so that when it breaks someone else can fix it for you. > ;D > > Cheers > > "Gary Pace" <xxx@yyy.com> wrote in message > news:PKf2e.41588$Ux.8035@tornado.texas.rr.com... >> Hi y'all : >> >> We create our .mif files by running a custom analysis program on a set of >> data files. >> >> I'd like to include this in the compile process. >> >> Whilst I can find interfaces to various EDA tools, I can't find a "just >> run >> this program prior to compilation" option >> >> Is this possible ? >> >> Thanks >> Gary >> >> > >Article: 81683
Preben wrote: > Jeremy Stringer wrote: > > Post-map also takes care of some delays - but which ones. > I can't use the post place and route, cause I can't count on this, when > I don't simulate the whole design since the routing will not be correct? I'd make the assumption that it would probably just take the delays from the actual logic into account, without routing delay - for instance, the combinatorial delays through X many luts. Post place-and-route is probably worth it still, as it will give you some idea of routing delays - the only accurate simulation is that of the final product though. Basically, there is no guarantee of how the design will be finally routed - you might change something, and the design will then be routed differently. There are ways to mitigate this, if it's really necessary (RPMs, directed routing etc). What are you trying to do? (Do you actually need a full simulation with all the extra timing information?) JeremyArticle: 81684
Matt Klein wrote:
> 1) He did not make quote experimental results as yielding almost =
identical
> static power for Virtex-4 and Stratix II. If you look carefully at =
all
> actual bench measurements of total power for various designs, which =
were
> presented. They have total power (at 25 C). They all show a =
significant
> advantage for Virtex-4 (look at the DC i.e. zero frequency data points =
in
> the slides).
We measured static power, and it is in line with the typical values =
predicted by the power estimators, so both the Stratix II and Virtex4 =
devices measured were reasonably typical. The 25 C ambient temperature, =
typical silicon results for static power show a small static power =
advantage for Virtex4. The advantage is about 40 mW for the LX25 vs. =
the 2S15, and about 180 mW for the LX25 vs. the 2S30.
The more important comparison is the worst-case silicon, 85 C junction =
temperature total power comparison. For that comparison, we have to =
rely on the power estimators of Xilinx & Altera, since we can't buy tens =
of thousands of Xilinx units across multiple wafers and lots to create a =
worst-case silicon model. That comparison again shows a small static =
power advantage for Virtex4: from 0 W to 690 mW, depending on the =
device you're comparing.
See http://www.techonline.com/community/ed_resource/webcast/37595 to =
view the whole NetSeminar on archive.
=20
> Here's the error. Xilinx doesn't have a multiplier on Vccaux power of =
2.5
> (we have never stated this publically or privately). We have stated a =
2.5x
> multiplier ONLY on Vccint power for typical to worse case. There is =
no
> scaler applied to Vccaux power, because the number is the Xilinx tools =
is
> in fact quite invariable over process.=20
That does not match what we're seeing in the customer base. We're often =
visiting the same customers as Xilinx, and we see customers being =
advised to multiply Vccint by 2.5X (matching your comment above), but we =
also see Xilinx advising Vccaux worst-case leakage is 2X to 2.5X =
(depends on which customer you ask) typical.
In any case, the worst-case silicon, 85 C static power comparison is not =
affected dramatically by which multiplier we use for Vccaux, and the =
total power comparison (static + dynamic + IO) is of course affected =
even less. The table below summarizes the power consumption for the =
2S180 vs. the LX200 for 3 different Vccaux typical to worst-case =
multiplier assumptions.
Comparisons below: worst-case silicon, junction Temp =3D 85 C, typical =
utilization 200 MHz design, equivalent Virtex4 & Stratix II utilization =
(see NetSeminar for details)
=20
Static Dynamic + IO Total Power
2S180 5.46 W 8.5 W 14 W
LX200 (Vccaux =3D 2.5X typical) 5 W 11.3 W 16.3 W
LX200 (Vccaux =3D 2X typical) 4.79 W 11.3 W 16.1 W
LX200 (Vccaux =3D typical) 4.38 W 11.3 W 15.7 W
So you can see, the overall power comparison doesn't move much, and even =
the static power comparison only moves moderately, no matter what Vccaux =
multiplier is used.
=20
> This error in using the 2.5x multiplier on Vccaux results in the =
Xilinx
> Virtex-4 having the originally stated huge advantage in Static Power
> compared to Stratix-II, both in typical and worst case.
I addressed this question in the NetSeminar. There are two problems =
with the Xilinx white paper that makes this claim.
1. It neglects to add Vccaux static power to the Virtex4 static power, =
but a significant part (for typical silicon 21% to 40%, depending on the =
device density) of the Virtex4 static power comes from Vccaux. =20
2. It compares one Stratix II device to one Virtex4 device. However, =
process variation results in a tremendous variation in static power from =
the best-case leakage device (higher than spec'd Vt, longer than Spec'd =
channel) to the worst-case leakage device (lower than spec'd Vt, shorter =
than spec'd channel). It is common to see worst-case to best-case =
silicon vary in static power by 3X to 5X (the exact value depends on the =
steps you took in design & layout to create process-variation reducing =
structures, and exactly how good your process control is). Hence =
comparisons on single units aren't very useful -- at best they produce =
inconclusive data, and at worst they are very susceptable to =
manipulation, if you are willing to search for a low-leakage device from =
one vendor and a high leakage from the other.
The Xilinx white paper actually states that the Stratix II device =
measured is worse than typical silicon, while the Virtex4 is better than =
typical. So the white paper itself makes clear that it suffers from =
this "silicon selection" issue.
Instead of measuring a single unit to determine static power, you have =
to rely on the worst-case spec of each manufacturer, and that is what I =
did in the NetSeminar.
Vaughn Betz
Altera
[v b e t z (at) altera.com]
Article: 81685Good to see another EAGLE user. What are you doing with this board, may I ask? b r a d @ a i v i s i o n . c o m > Are you looking for a schematic? If so try > http://www-user.rhrk.uni-kl.de/~alles/fpga/euterpe.pdf > > This schematic shows you how you can connect a standard synchronous SRAM > to the Spartan3. > > Matthias AllesArticle: 81686
ann wrote: > Hi, Thanks for the schematic. So do you have application notes on how to interface with this sram? Is there a module in your FPGA design that interface with this sram? Thanks, Ann You can get an sdram interface on Lattice's website. It can target to a low cost EC fpga. http://www.latticesemi.com/products/devtools/ip/refdesigns/sdr_sdram.cfm TeoArticle: 81687
When I choose Distribute Memory -> Depth 2048 -> Width 64 -> ROM -> LUT based, and my .coe file contains only 1500 words, what will ISE do during the P&R? Will it save the 548 words or implement them with zeros anyhow? My FPGA has ample LUT remaining, but little BRAM. I need to plug in some more data which is meant to be put in the BRAMs. Where is the place I can store these data?Article: 81688
John_H wrote: > It would be coded this way because someone doesn't know what they're > doing. The blocking assignment (=) rather than the non-blocking > assignment (<=) is a flag that the person writing the code is green, > the assignment of dout_en in different always blocks suggests they > don't even know what they're trying to do. > > This, of course, is only an opinion from someone exposed constantly > to professional designs. Thanks for taking the time to reply. The code was taken from the test bench for the opencores IDE controller. And I'm very quickly beginning to concurr with your assessment of the author of the testbench. I started expanding on the bench to add my own tests, only to be frustrated with my inability to read from the simulated device. I was stumped because the existing tests, which read from the simulated device, all pass. On closer inspection I find that values read from the simulated device actually contain 'ZZZZ' in the lower 16 bits. All the existing tests use an inequality test to verify the data read back after a write, which of course fails the condition if one operand contains ZZZZ and the errors are never flagged. The testbench passes even though it can't read any data from the device. So as far as I, admittedly a verilog newbie, can tell, the testbench is completely useless. Would love somebody to prove me wrong!?! Regards, MarkArticle: 81689
Are you using the UP3? I use it with a Win2k machine on serial port COM1 and it works fine. Make sure you put the JTAG connector into the right plug and select the correct device. Cheers, Chris Jos? Luiz Martins wrote: > Hi folks, > > > I'm facing one problem that is driving me crazy... > > The error is the following: > > Error: JTAG ID code specified in JEDEC STAPL Format File does not > match any valid JTAG ID codes for device. > > I'm using one ALtera University Program with ByteBlaster MV Cable on a > Windows XP machine. > > This is my first project in FPGA... I read almost everithing about > ByteBlaster and Quartus II configuration, and nope... > > My cable is installed, and everytinh else... > > Thank you very much in advance. > > > JL MartinsArticle: 81690
Hi everyone,
I am using a demo board from Memec whose clock source is given to one
of the input PINS of the FPGA.
I have to generate two clocks of different frequency from this input
clock source. I am using two DCM's for these.
When i give the input clock to both the DCMs there is an error during
implementing the design which says one input clock cannot drive two
DCM's or something like that.
So i tried giving the output of one of the DCM's to the input of
another DCM.
Even then it gives an error during the implementation stage. Both the
error cases are mentioned below.
This problem has been addressed before in this group without any
possible solution. But it has been a long time. So i was thinking
anyone has come up with an idea. I have also opened a webcase with
Xilinx.
The first case is when the input clock is given as an input to both the
DCM's
The second case is when the output clock of the DCM is given as an
input to the second DCM.
case1
ERROR:LIT - IPAD symbol "clkin" is driving more than one loads. IPAD
can only drive a single IBUF or two IBUFDS.
If you are using a BUF instead of an IBUF, it may have been
simplified, please use an explicit IBUF instead.
Errors found during logical drc.
case2
ERROR:NgdBuild:455 - logical net 'CLK0_OUT' has multiple drivers. The
possible
drivers causing this are:
pin O on block dcm_33_CLK0_BUFG_INST with type BUFG,
pin PAD on block CLK0_OUT with type PAD
ERROR:NgdBuild:466 - input pad net 'CLK0_OUT' has illegal connection.
Possible
pins causing this are:
pin O on block dcm_33_CLK0_BUFG_INST with type BUFG
Thanks and regards
Article: 81691Jim Wu wrote: > "Hendra" <u1000393@email.sjsu.edu> wrote in message > > There are two ways to synthesize a memory in an FPGA. One is to use > > verilog's reg as you suggested, the other one is to use Vendor Specific > > Primitive. Using verilog's reg is the most portable one. It works with > > all FPGAs with little or no modification. But it takes valuable space > > in your FPGA logic that otherwise can be used for other purposes. > > Most of the synthesis tools are able to infer dedicated RAM blocks. With XST, how do I know that my code is synthesized to a RAM made from the logic, or RAM made from the dedicated RAM blocks? HendraArticle: 81692
"Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca> wrote in message news:<MY2dnZv1k4xi59TfRVn-3Q@rogers.com>... > > What about using mif-files (memory initialization files) ? > > The MegaRAM cannot be initilialized in the hardware. > > - Paul So are they used for simulation only ?Article: 81693
"ALuPin" <ALuPin@web.de> schrieb im Newsbeitrag news:b8a9a7b0.0503292309.7b8558ee@posting.google.com... > "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca> wrote in message news:<MY2dnZv1k4xi59TfRVn-3Q@rogers.com>... > > > What about using mif-files (memory initialization files) ? > > > > The MegaRAM cannot be initilialized in the hardware. > > > > - Paul > > > So are they used for simulation only ? ROTFL ! ROTFL ! that would a real nice to way to add new features to FPGA - simulation only FPGA primitives! what an opportunity for those marketing guys that would be! AnttiArticle: 81694
genlock wrote:
> Can you explain this logic that you have mentioned in more detail?
>=20
> I am using Xilinx ISE and when I try doing any division or
> multiplication, it keeps showing an error as follows:
>=20
> / can not have such operands in this context.
> ERROR: XST failed
>=20
> a)What I am trying to do is first convert the 24 bit vector to an
> integer.
>=20
> b)Then figure out a method to divide this integer by 1.36 that gives
> the result as an integer
>=20
> c)This integer is converted back to a 24 bit vector
>=20
> Any idea about how this division (b)can be performed?
>=20
> Thankyou
>=20
If you're using ISE you can always have a look into the Language=20
Templates (the icon with the light bulb on it).
The following code will do the trick:
signal product : std_logic_vector(47 downto 0);
signal mult_in : std_logic_vector(23 downto 0);
constant const_val : std_logic_vector(23 downto 0) :=3D X"the divisor";
--snip--
process (clk)
begin
if rising_edge(clk) then
product <=3D mult_in * const_val;
end if;
end process;
To make sure you're inferring hardware multipliers you have to set the=20
correct synthesize properties for that.
The value of the perfect constant could probably be a discussion in=20
itself but I would probably multiply by 47 (i.e. 2F hex) and then do a 6 =
bit right shift after the multiplication:
prod_out <=3D product(41 downto 18);
This method does not divide exactly by 1.36, but pretty close: 1.362.
Correct me if I'm totally wrong...
--=20
-----------------------------------------------
Johan Bernsp=E5ng, xjohbex@xfoix.se
Research engineer
Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems
www.foi.se
Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------
Article: 81695Congratulation!!!! Please send me a copy of your C Compiler for PicoBlaze. Thank you very much, TonyArticle: 81696
Please let me know what kind of test I can do for you. I requested a copy of your C Compiler for PicoBlaze but forgot to give you my email address: tonyphan3000@yahoo.com, Thanks again,Article: 81697
I'm new to math function on FPGA, but I need to calculate exp(-x) with a Spartan3 in fixed point 16bit numbers. How can i do that? What's the best way? Can someone help me?[size=24:ae1f1145a8][/size:ae1f1145a8]Article: 81698
"tonyphan" <tonyphan35@hotmail-dot-com.no-spam.invalid> schrieb im Newsbeitrag news:jKKdnS9z1s29w9ffRVn_vg@giganews.com... > Congratulation!!!! Please send me a copy of your C Compiler for > PicoBlaze. > Thank you very much, > Tony > you are person number n+x that asks the author of that C compiler for an copy, so far I know no one who has received that c compiler so far. I have asked as well loooong time ago, the author did not care to respond at all. :( if you want to beta test then there is a partially working high level compiler for picoblaze http://gforge.openchip.org/projects/picoblazic/ the source codes of the compiler itself will be made public as well very soon AnttiArticle: 81699
"design" <vasus_ss@yahoo.co.in> wrote in message news:1112163854.757392.208930@o13g2000cwo.googlegroups.com... > > case1 > ERROR:LIT - IPAD symbol "clkin" is driving more than one loads. IPAD > can only drive a single IBUF or two IBUFDS. > If you are using a BUF instead of an IBUF, it may have been > simplified, please use an explicit IBUF instead. > Errors found during logical drc. > Dear Design, Having trouble living up to your name, I see. Why not do what the error message tells you? The ISE software authors went to all that trouble to write 'please use an explicit IBUF instead' and then you go and ignore them. ;-) Cheers, Syms.
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