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Hi Antti, not that I want to push PicoBlaze ;-) (I think with it's limited code-space, programming in C does not make much sense..., you could use ERIC5...), but to be fair I wanted to let you know that I got my copy some time ago. Maybe you should write Francesco a direct e-mail. (No, don't ask me, you will not get it ;-), it is his software). Regards, Thomas www.entner-electronics.com "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:d2dnf3$vn1$05$1@news.t-online.com... > "tonyphan" <tonyphan35@hotmail-dot-com.no-spam.invalid> schrieb im > Newsbeitrag news:jKKdnS9z1s29w9ffRVn_vg@giganews.com... >> Congratulation!!!! Please send me a copy of your C Compiler for >> PicoBlaze. >> Thank you very much, >> Tony >> > > you are person number n+x that asks the author of that C compiler for an > copy, so far I know no one who has received that c compiler so far. I have > asked as well loooong time ago, the author did not care to respond at all. > :( > > if you want to beta test then there is a partially working high level > compiler for picoblaze > > http://gforge.openchip.org/projects/picoblazic/ > > the source codes of the compiler itself will be made public as well very > soon > > Antti > >Article: 81701
I sent Francesco a dírect email loooong time ago. There was no response from him :( Antti "Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag news:424a6f56$0$19574$91cee783@newsreader02.highway.telekom.at... > Hi Antti, > > not that I want to push PicoBlaze ;-) (I think with it's limited code-space, > programming in C does not make much sense..., you could use ERIC5...), but > to be fair I wanted to let you know that I got my copy some time ago. Maybe > you should write Francesco a direct e-mail. (No, don't ask me, you will not > get it ;-), it is his software). > > Regards, > > Thomas > > www.entner-electronics.com > > "Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag > news:d2dnf3$vn1$05$1@news.t-online.com... > > "tonyphan" <tonyphan35@hotmail-dot-com.no-spam.invalid> schrieb im > > Newsbeitrag news:jKKdnS9z1s29w9ffRVn_vg@giganews.com... > >> Congratulation!!!! Please send me a copy of your C Compiler for > >> PicoBlaze. > >> Thank you very much, > >> Tony > >> > > > > you are person number n+x that asks the author of that C compiler for an > > copy, so far I know no one who has received that c compiler so far. I have > > asked as well loooong time ago, the author did not care to respond at all. > > :( > > > > if you want to beta test then there is a partially working high level > > compiler for picoblaze > > > > http://gforge.openchip.org/projects/picoblazic/ > > > > the source codes of the compiler itself will be made public as well very > > soon > > > > Antti > > > > > >Article: 81702
Your problem is being caused because you are trying to drive two IBUFG's from the same pad. IBUFG's are special clock buffers that are connected directly to certain FPGA dedicated clk pins to provide a very low delay path to a DCM. Since there is a dedicated connection between the pin and the IBUFG, it is impossible to drive two IBUFG's from the same pin (this seems to be what you are attempting to do). The solution is to use only one IBUFG and use the output from this to drive the two different DCM's. Cheers SamArticle: 81703
> Well, I have read all of your posts, and everyone elses too. The problem > is one of clarity of communications. Good that you know that everyone read them all. I for sure could not make that statement. > > Xilinx produces an XC3000 family, and XC3000A family, an XC3100 family > and an XC3100A family (and many others too). My point about clarity is > that your original article says XC3000, another article says XC3000A, > and finally with actual partnumbers it turns out XC3100A. Very good point!! The part in question is an XC3190A. But, I have also tried some tests with the non A devices as well. When I first opened the call with the hotline I provided them with all of the details but did not even think about it in my original posts. > Are all the devices on all the boards XC3100A? It matters, as the various > familys had slightly different config logic. Yes, all of the parts are the same on this board. All the XC3190A. > >"The note to your link suggests that setting Reset high for > 6us then > >setting it and the Prog/Done pin low for > 6us will bring the device > >back to the clear configuration state. Looking at the loader code, > >this is pretty much what is being done on every load. > > "pretty much" is not clear. I measured 7.5uS. Also note where I ran some tests at 10uS. All greater than minimum. While I don't think I posted it, I even tried a test where I held reset for well over a second. > You are dealing with a tough problem. It is rare, difficult to reproduce, > and in an area (configuration) in which almost every designer has at least > at one time had problems, some times intermittent, sometimes easy to > repeat. The experience has been that except in extremely rare situations > the problem has been traced back to something outside the FPGA. Good enough. > I understand your frustration, you've been at this for over 2 weeks, and > no magic bullet yet. LOL. Not looking for any magic. > In the fault mode you have described, the D/P is permanently low. > For this situation, assuming that the device is in slave serial mode, Which they all are.Article: 81704
Comments inline below... Basic summary is you need to think more like
hardware and less like software.
genlock (genlocks@gmail.com) wrote:
: Can you explain this logic that you have mentioned in more detail?
: I am using Xilinx ISE and when I try doing any division or
: multiplication, it keeps showing an error as follows:
: / can not have such operands in this context.
: ERROR: XST failed
: a)What I am trying to do is first convert the 24 bit vector to an
: integer.
: b)Then figure out a method to divide this integer by 1.36 that gives
: the result as an integer
: c)This integer is converted back to a 24 bit vector
Synthesis tools (ISE's XST etc.) use typecodes (and hence typecode
conversions) as a queue to how to implement something (e.g. signed or
unsigned multiply.) XST doesn't implement divides (other than by powers
of 2:-) full stop, so converting to a type where it's obvious to you
won't help the syn tool produce hardware. (It might work in simulation
though.)
Remember inside the FPGA you are working with signals made of bits, and
only bits, so something like 1.36 is a bit meaningless. As others have
said just multiply by the reciprocal of the divisor. Below is an untested
code snippet to demonstrate how to do this in VHDL.
signal input : std_logic_vector(23 downto 0);
signal recip : std_logic_vector(23 downto 0);
signal mult_res: std_logic_vector(47 downto 0);
signal div_res : std_logic_vector(23 downto 0);
recip <= conv_std_logic(2^24 * 1 / 1.36) -- not sure this is the right
-- conv_blah function
-- Note that the calculation is
-- evaluated at synthesis time
mult_res <= input * recip -- assuming unsigned input
div_res <= mult_res(47 downto 24) -- there's a .5 bit rounding
-- error here for some results
Cheers,
Chris
: Any idea about how this division (b)can be performed?
: Thankyou
Article: 81705
Peter Alfke (alfke@sbcglobal.net) wrote:
: Eric, why do you want to use many small FPGAs in bad packages, when you
: could reduce your device count by a factor 8 and use a package that
: guarantees better signal integrity?
Peter,
Not the OPs reason by the looks of things, but I can see one
advantage in more smaller chips over fewer larger chips in the related
area.
Modular reconfiguation of number crunching black boxes! The synthesis
times for large chip designs tend to be quite at odds with the timescales
software people are used to, and pretty much preculde run time modifiable
RC acceleration in more than speciallised "We know all options in advance"
capacities.
The number of times I've heard different vendors in the area say "... our
product converts this number crunching to edif/vhdl/... in seconds. Then
we set the Xilinx tools off and go to the pub."
I realise there is support from Xilinx for reconfigurability on a sub chip
modular scale, but as I understand it it is reliant on the emulated
tristate bus feature lacking in new devices.
I suspect the first vendor to come up with a decent approach for sane HDL
-> Bitstram toolflows on a sub chip modular scale will be very attractive
to the HW acceleration / RC folks.
Also I could imagine the reduced PAR etc. times for being able to
partition a chip and only re-syn+PAR parts of it would make interactive
testing / debugging a lot more of an 'interactive' experience :-)
Finally it would provide people with a way of breaking very very memory
hungry PAR runs into more managable (and parallelisable!) jobs. Obviously
the module boundries need to be carefully thought out.
Okay I guess the reconfigurable computing world isn't that big for Xilinx
sales *yet...*
(This is of my Dear Santa note :-)
Cheers,
Chris
: Spartan-3 has lower performance than Virtex-II, and the TQ144 is
: probably the worst available package from a signal-integrity point of
: view.
: I would use a few Virtex-II devices ( perhaps eight 2V2000 or two
: 2V6000 chips), and avoid most of the interconnect hassles that you
: mentioned. "Keep most of the routing on chip!"
: If this is a university research project, contact Xilinx University
: Support. They can be quite helpful...
: Peter Alfke, Xilinx Applications
: Eric wrote:
: > Hello! I'm trying to build a 20-FPGA (spartan-3s, XC3S400-TQ144s)
: board
: > for a class project to investigate the use of FPGA arrays for
: accelerating
: > scientific competition. The idea was to have a 66 MHz 16-bit
: > single-ended shared TX bus sending 125 MBps to each FPGA, and a
: shared 66
: > MHz 16-bit data aggregation bus where a bus controller would poll
: each
: > FPGA sequentially to place its output data onto that bus.
: >
: > After discussions with some signal-integrity-leery friends, I'm no
: longer
: > convinced that a 12"x12" 20 IC board at 66 Mhz with single-ended
: buses is
: > such a good idea. I've been reading the various datasheets on doing
: LVDS
: > and DDR signaling. Multidrop LVDS is still a bit tricky, evidently,
: but to
: > cut down on trace number I might be able to go to 125 MHz DDR 4-pair
: LVDS
: > for the TX bus; the problem I'm having is with the data aggregation
: bus.
: >
: > Could the aggregate data bus be structured in a similar manner, with:
: > a.) all FPGAs connected to the 4 DDR LVDS pairs?
: > b.) a single master, with a separate output enable line to each of
: the 20
: > FPGAs
: >
: > Such that when FPGA n is output-enabled, it would drive it's m
: nibbles of
: > data onto the output aggregation bus. But this would require FPGA n
: to
: > drive its pins within 4 ns; this sounds nearly impossible.
: >
: > Are there any common solutions I'm missing? One thought was to
: aggregate
: > all of the data from the FPGAs via dedicated serial links and do
: clock
: > recovery at the bus master; this would require recovering 20 separate
: > clocks, alas, and with the spartan 3s we don't have quite that many
: DCMs.
: >
: > An obvious solution is "do an IBIS simulation, duh" but we don't
: > have access to the sort of high-end signal integrity simulation
: software
: > that this would require.
: >
: > Can anyone with spartan-3 serial interconnect experience offer
: > suggestions as to how to make this work, either through different
: > LVDS configurations or interconnect topolgies?
: >
: > Thanks for any advice you
: > can give,
: > ...Eric
Article: 81706We are programming an FPGA (Spartan2E) via a CPLD in Slave-Serial-Mode. The CPLD loads the bitfile from FLASH and writes it to the FPGA. When we are programming a bitfile into an FPGA without "MicroBlaze" via CPLD, the programming is always successful, after programming the DONE-Pin goes high and the application is running. Now our problem: when programming a bitfile including "MicroBlaze" via CPLD, the DONE-Pin fails to go high after programming. The INIT-Pin is always HIGH, after switching on or after releasing the PROG-Pin. In both cases we use the same process properties. Btw: when programming the same bitfile via JTAG (CCLK is changed to JTAG-Clock), no problems occur. Did anybody else had this problem before? Did anybody else programmed a bitfile (containing a "MicroBlaze") to the FPGA without using JTAG?Article: 81707
"MM" <mbmsv@yahoo.com> schrieb im Newsbeitrag news:3b00erF69vuouU1@individual.net... > Please bear with me, I am just learning how to use EDK... It seems nice, but > sort of self-contained. All of the examples and documentation show how to > create a processor based system from start to generating a *.bit file, which > is great, but what if I need to have some other unrelated logic in the FPGA? 1) create a user logic EDK core and add the connections in the XPS/EDK or 2) use the EDK generated system as submodule in ISE project AnttiArticle: 81708
Please bear with me, I am just learning how to use EDK... It seems nice, but sort of self-contained. All of the examples and documentation show how to create a processor based system from start to generating a *.bit file, which is great, but what if I need to have some other unrelated logic in the FPGA? What should my tool flow be in that case? Also, how do I approach a project (from the tool flow viewpoint) with more than one processor core? Thanks, /MikhailArticle: 81709
"C.Jesko" <c.jesko@avt-ilmenau.de> schrieb im Newsbeitrag news:ee8d106.-1@webx.sUN8CHnE... > We are programming an FPGA (Spartan2E) via a CPLD in Slave-Serial-Mode. The CPLD loads the bitfile from FLASH and writes it to the FPGA. > > When we are programming a bitfile into an FPGA without "MicroBlaze" via CPLD, the programming is always successful, after programming the DONE-Pin goes high and the application is running. > > Now our problem: when programming a bitfile including "MicroBlaze" via CPLD, the DONE-Pin fails to go high after programming. The INIT-Pin is always HIGH, after switching on or after releasing the PROG-Pin. > > In both cases we use the same process properties. Btw: when programming the same bitfile via JTAG (CCLK is changed to JTAG-Clock), no problems occur. > > Did anybody else had this problem before? the only thing that can be the issue is that there are some different bitgen options for the designs, the "microblaze" in your design can not cause any problems there must be some other thing that is configured differently in the bitstream > Did anybody else programmed a bitfile (containing a "MicroBlaze") to the FPGA without using JTAG? sure, on many different boards AnttiArticle: 81710
MM wrote: > Please bear with me, I am just learning how to use EDK... It seems nice, but > sort of self-contained. All of the examples and documentation show how to > create a processor based system from start to generating a *.bit file, which > is great, but what if I need to have some other unrelated logic in the FPGA? > What should my tool flow be in that case? You can choose to make it a completely self contained EDK project, and I have done one project that way. But I have since moved to embedding the processor/EDK portion in a plain old VHDL project and compiling that with ISE, which I guess Xilinx calls a "ProjNav" implementation flow. I mainly find this a little easier during the design and simulation portion of the project, which is of course the longest phase of a project. EDK adds another layer of stuff to deal with, and I eventually found it to be a minor annoyance, but that is probably just a personal preference. The one thing I found important to do for this approach was that I implemented a generic register interface for EDK, which allows me to implement the actual registers outside of EDK. Without that step, every time I created a new register with new inputs/outputs, I basically had to rerun EDK. Now, I rarely run the EDK compile, since almost everything I am changing during the design phase is outside the EDK portion.Article: 81711
On Wed, 30 Mar 2005 07:53:08 -0800, C.Jesko <c.jesko@avt-ilmenau.de> wrote: >We are programming an FPGA (Spartan2E) via a CPLD in Slave-Serial-Mode. The CPLD loads the bitfile from FLASH and writes it to the FPGA. > >When we are programming a bitfile into an FPGA without "MicroBlaze" via CPLD, the programming is always successful, after programming the DONE-Pin goes high and the application is running. > >Now our problem: when programming a bitfile including "MicroBlaze" via CPLD, the DONE-Pin fails to go high after programming. The INIT-Pin is always HIGH, after switching on or after releasing the PROG-Pin. > >In both cases we use the same process properties. Btw: when programming the same bitfile via JTAG (CCLK is changed to JTAG-Clock), no problems occur. > >Did anybody else had this problem before? > >Did anybody else programmed a bitfile (containing a "MicroBlaze") to the FPGA without using JTAG? I don't think the problem is Microblaze, since you were successful programming via JTAG. Very good that you did this test. My guess is that the two bitstreams are different lengths. You are probably writing data to the FPGA from your CPLD in multiples of the width of your FLASH. For the succesful bitstream, the bitstream actually ends 4 or more bits from the end of the last word of the FLASH, so you are generating 4 or more extra clocks beyond the last actual data bit. Your failing bistream ends much closer to the end of whatever the last word from the FLASH is. There is a requirement that you supply about 4 more clocks after the end of the bitstream tosequence the startup state machine. One of your bitstreams is doing this (by luck), and the other isn't (less lucky). I assume you have something in the FLASH that tells the CPLD howmany words to fetch and serialize. The simple solution is to add 1 more word of all '1' bits to the end of the bitstream, and tell the CPLD to send 1 more word worth of data. Please write back with the following info: The length of the two bitstreams. The width of the FLASH. Where the bitstream ends in the two different FLASH images. Philip Philip Freidin FliptronicsArticle: 81712
andpaoli wrote:
> I'm new to math function on FPGA, but I need to calculate exp(-x) with
> a Spartan3 in fixed point 16bit numbers. How can i do that?
Depends on what is the range of parameters. Your statement
"fixed point 16bit numbers" doesn't help much, because it doesn't
specify any particular encoding -- is it 8 bits for the integral part
and 8 bits for fractions or only 16 bits of fraction, which describe
a number in the range of (-1,1) or something else?
> What's the best way?
As I said, it depends.
Best regards
Piotr Wyderski
Article: 81713Hi Piotr, "Piotr Wyderski" <wyderskiREMOVE@ii.uni.wroc.pl> wrote in message news:d24gh5$27f$1@news.dialog.net.pl... > Hello, > > how do I extend buses in Quartus Schematic Editor? > Say, for instance, there is an input "phase_offset[23..0]" > and a component which expects a 32-bit wide vector. > I would like to map phase_offset to the upper 24 bits > of the vector and hardwire the remaining bits to 0. Maybe this is not the best way.. but it works!! Draw a bus line and give it a name, for example "a[7..0]". then connect this bus to a GND. Now on the input of the component which expects the 32bit vector you can have a bus line named "phase_offset[23..0],a[7..0]" Hope it works for you too, let me know if I wasn't clear enough. Christos dot Zamantzas at CERN dot chArticle: 81714
For anyone interested in using the Xilinx JTAG Interface as a General-Purpose Communication Port see http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm and also http://www.s3group.com/design_expertise/fpga/gnat/ for an example (as is) design for the Spartan-3 Starter Kit Regards BobArticle: 81715
"bob allen" <bob.allen@s3group.com> schrieb im Newsbeitrag news:d2elp8$urq$1@reader01.news.esat.net... > For anyone interested in using the Xilinx JTAG Interface as a General-Purpose Communication Port see > http://www.xilinx.com/publications/xcellonline/xcell_53/xc_jtag53.htm > > and also > http://www.s3group.com/design_expertise/fpga/gnat/ > for an example (as is) design for the Spartan-3 Starter Kit > > Regards > Bob YES, the GNAT is nice thing too, but my very small idea was using some JTAG pins as 'plain vanilla' inputs for the FPGA, so you can add a push-button to TCK pin and check the push button from FPGA. You are referencing to an IP core that is controlled by host PC to provide virtual IO similar to Virtual IO in the ChipScope thats different thing, much more interesting but just different thing AnttiArticle: 81716
HI: In my FPGA design, I have a serial port for monitoring service. The question is, how can I re-program the flash memory XC18V01 from FPGA serial port using only the JTAG bus. Thank so much.Article: 81717
<aarodriguez@amper.es> schrieb im Newsbeitrag news:1112204146.293742.275160@z14g2000cwz.googlegroups.com... > HI: > > In my FPGA design, I have a serial port for monitoring service. The > question is, how can I re-program the flash memory XC18V01 from FPGA > serial port using only the JTAG bus. > > Thank so much. > the 18v01 programming docs have neve been released so far :( what you can do is 1) if you have a processor in FPGA with decent c compiler you can recompile the xsvfplayer c code for the processor and use it program the serial rom, but you would also need quit a bit of external ram 2) implement a serial to jtag 'gateway' that converts the seial port into bit toggle of the jtag, then modify the xsvfplayer and make it to use the serial port and your own protocol, in this case the host PC will play the xsvf and send the data to control the jtag pins over serial port 3) you can look at the impact generated .SVF files and re engineer the commands needed to reflash the 18v02 and imlement your own programming algorithm anttiArticle: 81718
I see two potential problems with what you are trying to do. 1. As mentioned before you can only drive one IBUF/IBUFG from a Pad. 2. Outputs of two DCMs from same reference clock can have a phase offset. I am not sure of your application but something that you need to be aware of if you are using Virtex2 devices. samir design wrote: > Hi everyone, > I am using a demo board from Memec whose clock source is given to one > of the input PINS of the FPGA. > I have to generate two clocks of different frequency from this input > clock source. I am using two DCM's for these. > When i give the input clock to both the DCMs there is an error during > implementing the design which says one input clock cannot drive two > DCM's or something like that. > So i tried giving the output of one of the DCM's to the input of > another DCM. > Even then it gives an error during the implementation stage. Both the > error cases are mentioned below. > > This problem has been addressed before in this group without any > possible solution. But it has been a long time. So i was thinking > anyone has come up with an idea. I have also opened a webcase with > Xilinx. > The first case is when the input clock is given as an input to both the > DCM's > The second case is when the output clock of the DCM is given as an > input to the second DCM. > > case1 > ERROR:LIT - IPAD symbol "clkin" is driving more than one loads. IPAD > can only drive a single IBUF or two IBUFDS. > If you are using a BUF instead of an IBUF, it may have been > simplified, please use an explicit IBUF instead. > Errors found during logical drc. > > case2 > > ERROR:NgdBuild:455 - logical net 'CLK0_OUT' has multiple drivers. The > possible > drivers causing this are: > pin O on block dcm_33_CLK0_BUFG_INST with type BUFG, > pin PAD on block CLK0_OUT with type PAD > ERROR:NgdBuild:466 - input pad net 'CLK0_OUT' has illegal connection. > Possible > pins causing this are: > pin O on block dcm_33_CLK0_BUFG_INST with type BUFG > Thanks and regardsArticle: 81719
> > > There are two ways to synthesize a memory in an FPGA. One is to use > > > verilog's reg as you suggested, the other one is to use Vendor > Specific > > > Primitive. Using verilog's reg is the most portable one. It works > with > > > all FPGAs with little or no modification. But it takes valuable > space > > > in your FPGA logic that otherwise can be used for other purposes. > > > > Most of the synthesis tools are able to infer dedicated RAM blocks. > > With XST, how do I know that my code is synthesized to a RAM made from > the logic, or RAM made from the dedicated RAM blocks? The synthesis report will tell you if the tool inferred RAM. Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chipsArticle: 81720
I may be able to help you if you can send me the pinout (ucf). (use my private email below) Jim jimwu88NOOOSPAM@yahoo.com (remove capital letters) http://www.geocities.com/jimwu88/chips <wpiman@aol.com> wrote in message news:1112110943.504959.158890@o13g2000cwo.googlegroups.com... > Chipscope will be something we use after we verify clocks/reset and > what not. Right now I just want to print up a big sheet so the techs > can do some simple probing. I played with pace but didn't get anywhere. >Article: 81721
Hi.... I am a student of MS Systems Engineering, I have been assigned a project titled as "FPGA Based Field Controller(PID)". Currently I am in a study phase, I would be thankful if some of you send me some literature or papers that describes that how PID controllers can be implemented on FPGA. Looking for your positive response.....Umair SiddiquiArticle: 81722
Hi, I am generally interested in SDR with FPGA. Does anybody know some nice projects or where to find good information about it? Any experiences would be appreciated too. Maybe there is somebody involved with the SCA/JTRS (joint tactical radio system) here in the Newsgroup :) regards, BenjaminArticle: 81723
Brad Smallridge schrieb: > Good to see another EAGLE user. > > What are you doing with this board, may I ask? I just wanted to gain experience in PCB designing with it. If you want to know more detailed what I did with this board so far have a look at http://www-user.rhrk.uni-kl.de/~alles/fpga/ MatthiasArticle: 81724
ann schrieb: > Hi, Thanks for the schematic. So do you have application notes on how to interface with this sram? Is there a module in your FPGA design that interface with this sram? Thanks, Ann I don't have any application notes about it. When you use the EDK of Xilinx you can use the generic SRAM core. But it's not very difficult to write an own SRAM controller, you only need the data sheet of the SRAM.. Matthias
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