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>Well, at this point it's all about experimentation. This is for a class on >parallelism and supercomputing (beowulfs and the like) and I've wanted to >build some arrays of FPGA-based hardware for a while. There are some >applications for which floating point is unnecessary (signal processing, >crypto, etc), and also it seems that at least single-precision FP might be >possible (I also want to address that). I'd suggest picking a particular problem and working through far enough so that you can estimate the speedup relative to a simple PC or DSP chip. That way you can find the hot spots in your design and/or see if the economics make sense. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 81626
lecroy7200@chek.com wrote: <Snip> > In this last test I wanted to try and decouple the CORE that was being > loaded into the device. For this test, all that was done was to cycle > the supply. I used a 5mS off time and cycled at 100Hz. Using the > spectrum analyzer I monitored the 16MHz clock. After about 10 minutes > of testing, the oscillator had failed to start. I probed the remaining > devices and found that three others also had failed to start. This is multiple devices on one board, or multiple boards being cycled ? > I then > started to increase the off time using the one-shot mode. I noted that > at about 200mS - 250mS two of the devices oscillators restarted. The > third device took more than a second of off time before starting. Sounds like you now have a reasonably rapid means of entering the suspect state, and some numbers on Trec. ( which probably also varies with temperature... ) Is 5ms enough time to exit pgm load mode, or is this test removing Vcc before the Load state engine has finished ? This does sound like a 'sticky trigger' test, in that any of the ~60,000 power cycles that causes an upset, will not clear on the next cycle, as that Toff is < Trec. -jgArticle: 81627
"vax, 9000" <vax9000@gmail.com> schrieb im Newsbeitrag news:d2at3p$qqs$1@charm.magnus.acs.ohio-state.edu... > GT wrote: > > > Thanks for the info. > > What is correct current limiting resistor size to use? > > Thank you > > > > Let's say that the voltage drop on LED is 1V, the FPGA/CPLD output voltage > is 0.3V, and the LED current is 5 mA. The resistor would be (3.3-1-0.3)V/5 > mA=0.4 kOhm > > vax, 9000 its sometimes also ok to use no resistor by selecting proper IO drive level and using approp PWM to control the LED overage current. A suitable 4Bit PWM ip core consumes 1 Xilinx LUT and 1 Flip Flop http://gforge.openchip.org/projects/xilcores/ source code is available from the above project downloads AnttiArticle: 81628
Antti Lukats wrote: > Hi > > http://wiki.openchip.org/index.php/OpenChip:FpgaFreqMeter > > there is prelimary info about Application that turns any FPGA into 8 channel > frequency meter - > all you need is FPGA and download cable (and the Frequency meter SW > application of course) > > initial support is for Xilinx FPGA's only, Altera/Lattice will be added > later Impressive. Can you add to your web pages, a brief overview of the design, covering - Appx MAX Ctr limit, either from SW estimate, or from a bench test (typ), and the LOGIC resources used - Counter performance, typically digits/second for reciprocal Ctrs, or simply gate times and count rates, for the really vanilla ones ? - Output choices - your examples seem to be PC-centric. Any options for LCD module output ( as on some eval PCBs ?) jgArticle: 81629
Antti Lukats wrote: > Hi > <snip> > MAX2 is really nice well its not so much an PLD but more like > Xilinx XC2K reinvented and made flash based ;) anyway it is > really a heavy player on the flash device arena as the other > suppliers Atmel and Lattice are not yet shipping their low-cost > flash FPGAs Lattice do have their first LatticeXP devices, but not the smallest ones. Present press releases have their XP10 around $33 in 1K/now, and ~$16 for 250K/2006 prices. No mention of prices on the smallest XP3. Actel claim to have ProASIC3 prices 'from $1.50', but are less clear on specifics.... Have you looked at the ProASIC3 family / tool flows ? -jgArticle: 81630
hi, in ise, the console window says "synthesis completed" but in the process for source, it still shows a question mark instead of an exclamatory mark(excla.. mark for synthesis complete).ans when u click sysnthesis report , it start the synthesis process all over again..if any one knows,pls let me know. ~Mack.Article: 81631
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:424923d0$1@clear.net.nz... > Antti Lukats wrote: > > > Hi > > > <snip> > > MAX2 is really nice well its not so much an PLD but more like > > Xilinx XC2K reinvented and made flash based ;) anyway it is > > really a heavy player on the flash device arena as the other > > suppliers Atmel and Lattice are not yet shipping their low-cost > > flash FPGAs > > Lattice do have their first LatticeXP devices, but not the > smallest ones. Present press releases have their XP10 > around $33 in 1K/now, and ~$16 for 250K/2006 prices. > No mention of prices on the smallest XP3. And shipping NOW for regular mortals? NO! I guess none of the XP devices are shipping or available. > Actel claim to have ProASIC3 prices 'from $1.50', but are > less clear on specifics.... There will be NO ProAsic3 silicon before SEPT 2005 Not even engineering samples. Dont hope. > Have you looked at the ProASIC3 family / tool flows ? > > -jg > Yes I have tried several times. Scary. Sure sometimes the P&R seems to finish succesfully too. I have tried to compile several projects fro ProAsic+ usually yielding in no fit - I only have APA075 eval board and using free license. So far the only succesful use for ProAsic+ has been the Eric5 CPU demo displaying some Hello on LCD AnttiArticle: 81632
"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag news:4249215b$1@clear.net.nz... > Antti Lukats wrote: > > > Hi > > > > http://wiki.openchip.org/index.php/OpenChip:FpgaFreqMeter > > > > there is prelimary info about Application that turns any FPGA into 8 channel > > frequency meter - > > all you need is FPGA and download cable (and the Frequency meter SW > > application of course) > > > > initial support is for Xilinx FPGA's only, Altera/Lattice will be added > > later > > Impressive. > Can you add to your web pages, a brief overview of the design, covering > - Appx MAX Ctr limit, either from SW estimate, or from a bench test > (typ), and the LOGIC resources used At the moment I only have working proof of concept implementation using plain vanilla non optimized 32 bit gated counters. The max speed estimate could not be accurate as I dont know the target device speed grade - from thumb data the current implementation would support 200MHz on all channels in any decent Xilinx FPGA I might be able to push the max input frequency to the max toggle rate of the fastest on chip flip-flop on some FPGAs and I may also be able to support clock speed beyound that by doing tap-delay line sampling. Also supported will be use of MGT as clock input yielding to max frequency to about little less than 1/2 of the MGT max bitrate. Loading device for application Par from file '3s1500.nph' in environment Device utilization summary: Number of Slices 270 out of 13312 2% Number of BSCANs 1 out of 1 100% Number of BUFGMUXs 8 out of 8 100% > - Counter performance, typically digits/second for reciprocal Ctrs, > or simply gate times and count rates, for the really vanilla ones ? gate time is free from less than 1ms to 10years+ if you want to wait :) hm after doing slight mod to the ipcore what I see when measuring 75MHz with PC as reference (eg absolute measurement) 250ms gate time ppm error toggles between 127..132 1000ms gate time ppm error toggles between 129..131 this was impressive repeat stability when using PC based software controlled gate timing! for ratiometric measurement where one clock input is reference for others the relative max error is worst case +2 clock per measurement > - Output choices - your examples seem to be PC-centric. Any options > for LCD module output ( as on some eval PCBs ?) > > jg The presented approuch is PC centric, or optionally some FPGA board with ucCLinux could use another FPGA as well (in that case the absolute measurement would be even more exact and referenced to the main FPGA clock) The PC based approuch support ANY FPGA (from supported vendor/family) without ZERO knowledge about external connections and requires no reference clock to be present at the FPGA pins. It would not be possible to support the same flexibility on existing eval boards - another approuch would be required, and for you - work in that directions is also partially been done. So FPGA standalone version will also be offered but I would need to setup a 'board support database' and a bunch of scripts to compile the designs for all known boards. AnttiArticle: 81633
Hi, As I am making a PS/2 keyboard vhd , I am looking for scancodes of an azerty keyboard to convert code from keyboard to ascii code. Does anyone know where i can find that because I only found it for qwerty keyboard. Thanks AlexisArticle: 81634
> Yes I have tried several times. Scary. > Sure sometimes the P&R seems to finish succesfully too. > I have tried to compile several projects fro ProAsic+ > usually yielding in no fit - I only have APA075 eval > board and using free license. > > So far the only succesful use for ProAsic+ has been > the Eric5 CPU demo displaying some Hello on LCD > > Antti > Maybe I should mention that the ProAsic+/3 does not support preinitialized memory-blocks (a pity for a flash-based architecture...), so I had to synthesize the program-ROM into logic-tiles for the ERIC5-demo, which is very space consuming. I managed to use about 73% of the tiles, above that the fitting failed. Regarding MAX II: I am missing memory-blocks (RAM) there... BTW: For "real" Actel-designs with ERIC5, the solution is to bootload the program-memory from an external SPI-flash into the internal memory-blocks, or to use them as cache and execute directly from the SPI-flash. Regards, Thomas www.entner-electronics.comArticle: 81635
there is already one in verilog but i wanted to make my own PS2 driver in VHDL "Sea Squid" <Sea.Squid@hotmail.com> a écrit dans le message de news: 4247e7ce$1@news.starhub.net.sg... > Go to Opencores.com > > > > "KCL" <kclo4_NO_SPAM_@free.fr> wrote in message > news:4247e494$0$808$8fcfb975@news.wanadoo.fr... >> Hi, >> As I am making a PS/2 keyboard vhd , I am looking for scancodes of an > azerty >> keyboard to convert code from keyboard to ascii code. Does anyone know > where >> i can find that because I only found it for qwerty keyboard. >> >> Thanks >> >> Alexis >> >> > >Article: 81636
"Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag news:42494101$0$19210$91cee783@newsreader02.highway.telekom.at... > > Yes I have tried several times. Scary. > > Sure sometimes the P&R seems to finish succesfully too. > > I have tried to compile several projects fro ProAsic+ > > usually yielding in no fit - I only have APA075 eval > > board and using free license. > > > > So far the only succesful use for ProAsic+ has been > > the Eric5 CPU demo displaying some Hello on LCD > > > > Antti > > > > Maybe I should mention that the ProAsic+/3 does not support preinitialized yes the init of ProAsic+ and ProAsic3 is a very pity thing :( > memory-blocks (a pity for a flash-based architecture...), so I had to > synthesize the program-ROM into logic-tiles for the ERIC5-demo, which is > very space consuming. I managed to use about 73% of the tiles, above that > the fitting failed. hm then you have seen the same as me, if the utilization goes over 50% chances to get succesful fit get lower and lower, that was the scary thing for me. > Regarding MAX II: I am missing memory-blocks (RAM) there... yes they are missing a register file takes lots of resources. but a small 8 bit SRAM that loads init bootloader from UFM would be nice option for softcore cpu implementation > BTW: For "real" Actel-designs with ERIC5, the solution is to bootload the > program-memory from an external SPI-flash into the internal memory-blocks, > or to use them as cache and execute directly from the SPI-flash. > > Regards, > > Thomas > > www.entner-electronics.com > Hi Thomas you have promised ERIC5 evaluation in MARCH 2005 there isnt much days left if you are about to keep that promise! AnttiArticle: 81637
Not that I do not appreciate everyones help in this matter, but I have received several PMs included from Xilinx tech support asking if I have tried the following: - Bring the DONE/PROGB pin low - Hold RESETB low fot at least 6 us - Start the re-configuration I am not sure if some people are not able to read the entire thread and that is the cause. The following are from my first and fourth posts: "Pulling the XC3000's reset low for 10us has no effect. ... The only way to reprogram the part is to power down the IC. " "The note to your link suggests that setting Reset high for > 6us then setting it and the Prog/Done pin low for > 6us will bring the device back to the clear configuration state. Looking at the loader code, this is pretty much what is being done on every load. The Reset normally idles high and it along with the Program pin are pulled low for 7.5us. I verified this as well. Doing this does not make the device exit this strange mode. So far, the only thing that seems to clear it from this state is a hard power down."Article: 81638
> > Hi Thomas > > you have promised ERIC5 evaluation in MARCH 2005 there isnt much days left > if you are about to keep that promise! > > Antti > > Hey, we are in FPGA business here, you should know marketing ;-) As you say, there are still some days left... In fact I am just working on that eval-stuff. The first download will be for the Nios-Cyclone-Kit, a second is planed for the Spartan-3-Starter-Kit. The hardware will be fixed, but you will be able to write and download your own software onto the board. There will be no eval-download for Actel, as the ProAsicPlus-Kit has no RS-232 (I do not think that people will start soldering a RS-232-adapter, just to test-drive ERIC5). Regards, Thomas www.entner-electronics.com P.S.: Of course, I'll try to keep my promise!Article: 81639
"Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag news:42495f4b$0$13468$91cee783@newsreader01.highway.telekom.at... > > > > Hi Thomas > > > > you have promised ERIC5 evaluation in MARCH 2005 there isnt much days left > > if you are about to keep that promise! > > > > Antti > > > > > > Hey, we are in FPGA business here, you should know marketing ;-) As you say, > there are still some days left... > > In fact I am just working on that eval-stuff. The first download will be for > the Nios-Cyclone-Kit, a second is planed for the Spartan-3-Starter-Kit. The > hardware will be fixed, but you will be able to write and download your own > software onto the board. There will be no eval-download for Actel, as the > ProAsicPlus-Kit has no RS-232 (I do not think that people will start > soldering a RS-232-adapter, just to test-drive ERIC5). > > Regards, > > Thomas > > www.entner-electronics.com > > P.S.: Of course, I'll try to keep my promise! evaluation fixed to some specific kit are USELESS - really I have 10+ evaluation boards but none of those you mentioned so there will be no evaluation for me. And I am not going to purchase an kit you support just to eval eric5, no way. just my 2 cents. if you really are planning fixed to board-evals you may as well not todo it at all AnttiArticle: 81640
I have a top level schematic includes several macro instants (SDRAM controllers and others stuff) the design target spartan3-1000, speed-4. So far I haven't constraint pin LOC yet, but the SDRAM clock is constrainted at 166 Mhz. It's strange if I let the ISE "auto assign" the Inst. name as XLXI_xxx... for the the macros (specially the sdram controllers) then it pass 166 MHZ easily. If I manually assign the name likes the old style (U1, U2, U3....) then it FAILED the clock constraint, and it is consistent !!! So, the quesion is what's going on...I may learn something here but still dont understand WHY.... Anyone know? please.....Article: 81641
Antti Lukats wrote: <snip> >>Anyone working with SRLs in this sense should be aware: >>the global reset to the Xilinx device could deassert >>asynchronously to different SRLs at different clocks, >>knocking off the needed alignment between the SRLs. <snip> > Hi John, > > I think that isnt a problem (most cases) the SRL are not > connected to global set/reset lines at all, the initial > state is loaded from configuration memory and not dependant > on any delay in set/reset. As the clock is not propagating to > the SRL until all of them are configured then I think they > all will start in proper sync. The only requirement is that > the first CLK pulse comes to all SRL at the same time - if > they CLK inputs are on the same GCLK I think this is always > the case. Besides that Xilinx is using the SRL in seveal > designs that require sync starting and there is nothing > special done. So no worries. But it was a good think to > bring to notice, in some cases this could be and issue. As > example if the SRL shift loop includes flip-flop that use > async reset, etc.. > > Antti <snip> Perhaps the global reset was the wrong signal to pick on. When the chip first comes up, the power-up happens in sequence with global reset, global tristate, and... global enable(?) coming up at specified times relative to the configuration clock. If the global enable is like the global reset, applying asynchronously - then the occasional failure of an SRL-based divider I implemented a couple years ago (3 slices and a carry chain for about a 2^25 divider) could be explained. I only used it to blink some test LEDs so I never bothered to figure out the details but I did see the occasional failure. Because of the known issues with the asynchronous deassertion of the global reset I would think the global deassertion of the global enable would also cause the occasional problem if not designed for. I don't have proof-positive that it's an issue, only an SRL divider that occasionally went bad. - John_HArticle: 81642
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:BSd2e.55060$hA3.6679@trnddc09... > Antti Lukats wrote: > <snip> > > >>Anyone working with SRLs in this sense should be aware: > >>the global reset to the Xilinx device could deassert > >>asynchronously to different SRLs at different clocks, > >>knocking off the needed alignment between the SRLs. > > <snip> > > > Hi John, > > > > I think that isnt a problem (most cases) the SRL are not > > connected to global set/reset lines at all, the initial > > state is loaded from configuration memory and not dependant > > on any delay in set/reset. As the clock is not propagating to > > the SRL until all of them are configured then I think they > > all will start in proper sync. The only requirement is that > > the first CLK pulse comes to all SRL at the same time - if > > they CLK inputs are on the same GCLK I think this is always > > the case. Besides that Xilinx is using the SRL in seveal > > designs that require sync starting and there is nothing > > special done. So no worries. But it was a good think to > > bring to notice, in some cases this could be and issue. As > > example if the SRL shift loop includes flip-flop that use > > async reset, etc.. > > > > Antti > > <snip> > > Perhaps the global reset was the wrong signal to pick on. When the chip > first comes up, the power-up happens in sequence with global reset, > global tristate, and... global enable(?) coming up at specified times > relative to the configuration clock. If the global enable is like the > global reset, applying asynchronously - then the occasional failure of > an SRL-based divider I implemented a couple years ago (3 slices and a > carry chain for about a 2^25 divider) could be explained. I only used > it to blink some test LEDs so I never bothered to figure out the details > but I did see the occasional failure. Because of the known issues with > the asynchronous deassertion of the global reset I would think the > global deassertion of the global enable would also cause the occasional > problem if not designed for. > > I don't have proof-positive that it's an issue, only an SRL divider that > occasionally went bad. > > - John_H hm thats interesting, I wish some Xilinx guys would jump in on this! AnttiArticle: 81643
> > In this last test I wanted to try and decouple the CORE that was being > > loaded into the device. For this test, all that was done was to cycle > > the supply. I used a 5mS off time and cycled at 100Hz. Using the > > spectrum analyzer I monitored the 16MHz clock. After about 10 minutes > > of testing, the oscillator had failed to start. I probed the remaining > > devices and found that three others also had failed to start. > > This is multiple devices on one board, or multiple boards being cycled ? I once again may need to retract this. I have not been able to reproduce the power cycle test results. I am beginning to wonder if there was something flawed in my first attempt. I have been testing multiple boards with multiple devices per board. > > I then > > started to increase the off time using the one-shot mode. I noted that > > at about 200mS - 250mS two of the devices oscillators restarted. The > > third device took more than a second of off time before starting. > > Sounds like you now have a reasonably rapid means of entering the > suspect state, and some numbers on Trec. ( which probably also varies > with temperature... ) Again, temperature does not appear to be a factor. I have done numerious temperature tests and have never seen any corrilation. I am seeing a failure in four days on average. The rapid failure appears to have been a fluke of nature. Just one more random data point. > Is 5ms enough time to exit pgm load mode, or is this test removing > Vcc before the Load state engine has finished ? Again, this is no loading. Just looking at the internal oscillator and watching how long power must be removed before it recovers. Nothing to do with reprogramming the device. > This does sound like a 'sticky trigger' test, in that any of the > ~60,000 power cycles that causes an upset, will not clear on the next > cycle, as that Toff is < Trec. >From what I see, it all is pointing to a problem with the internal oscillator. It would be great if there were a way to probe it to verify what I am seeing with the analyzer.Article: 81644
Thank you Bert ! I did the configuration as detailed on Altera's documentation for this board and nope... I even replaced the current device to another good one. I can detect what device is present, but nothing else. Thank you , JL Martins Bert Cuzeau <_no_spa_m_info_no_underscore_@alse-fr___.com> wrote in message news:<4248ffef$0$1623$636a15ce@news.free.fr>... > Make sure you selected the exact correct device. > OTOMH, some old UP boards have two devices (cpld + fpga) and a switch > to select which one is hooked to the JTag connector... > There is a command to scan the JTag chain. > > > Jos? Luiz Martins wrote: > > > Hi folks, > > > > > > I'm facing one problem that is driving me crazy... > > > > The error is the following: > > > > Error: JTAG ID code specified in JEDEC STAPL Format File does not > > match any valid JTAG ID codes for device. > > > > I'm using one ALtera University Program with ByteBlaster MV Cable on a > > Windows XP machine. > > > > This is my first project in FPGA... I read almost everithing about > > ByteBlaster and Quartus II configuration, and nope... > > > > My cable is installed, and everytinh else... > > > > Thank you very much in advance. > > > > > > JL MartinsArticle: 81645
> > evaluation fixed to some specific kit are USELESS - really > I have 10+ evaluation boards but none of those you mentioned > so there will be no evaluation for me. And I am not going to > purchase an kit you support just to eval eric5, no way. > > just my 2 cents. if you really are planning fixed to board-evals > you may as well not todo it at all > > Antti > > Hmmm... I hoped that I picked two boards that many people have (you really do not have the Digilent S3-board?) I found no other useful solution that is both simple for the customer and protects our IP. Maybe you know one? (Please do not say: "Open Source", I had already this discussion ;-) For Altera, there would be OpenCore plus, but you need to be an AMPP, and it is not easy to become that, so it does not help me. Regards, Thomas www.entner-electronics.comArticle: 81646
UstuiosimaHuslova wrote: > I do not have FPGA experience, and I am not sure if my question make sense. > > Assume that we have a set of C++ code of various set of signal processing, > filtering, decision making, neural network, fuzzy logic etc. > Is it possible to convert (some how) these C++ code to run in FPGA ? > Is there a tool to convert C++ to FPGA code? Also post question to comp.dsp and see what they have to say, they may be more inclined to SW on DSP though. Give more details about required performance. It all depends on your throughput, if its low enough you may well be better off sticking with a PC host, PCs still run circles around DSPs and simple low perf FPGA designs on raw clock freq but the OS will make it hard for it to be in realtime if you have HW IO. If you have some real world signal acquisition from say an A<>D card, then its just a question of who's gonna do the math, as well as who's gonna do the bandwidth shuffle. At some point PCI becomes useless, FPGAs can have enormous bandwidth capabilities but in the end the data usually has to pass to a PC for analysis, storage etc. Also FP has a huge killer effect on FPGAs but is almost free on PCs. I'd suspect you may have some FP in your C code too, if you have, thats your 1st problem to sort out, integerize as much as possible, although that can slow down code on a PC but orders faster/cheaper if you end up in FPGA or DSP. So many choices. johnjakson at usa dot comArticle: 81647
"Thomas Entner" <aon.912710880@aon.at> schrieb im Newsbeitrag news:42496f0b$0$25276$91cee783@newsreader02.highway.telekom.at... > > > > evaluation fixed to some specific kit are USELESS - really > > I have 10+ evaluation boards but none of those you mentioned > > so there will be no evaluation for me. And I am not going to > > purchase an kit you support just to eval eric5, no way. > > > > just my 2 cents. if you really are planning fixed to board-evals > > you may as well not todo it at all > > > > Antti > > > > > Hmmm... > > I hoped that I picked two boards that many people have (you really do not > have the Digilent S3-board?) > > I found no other useful solution that is both simple for the customer and > protects our IP. Maybe you know one? (Please do not say: "Open Source", I > had already this discussion ;-) > > For Altera, there would be OpenCore plus, but you need to be an AMPP, and it > is not easy to become that, so it does not help me. > > Regards, > > Thomas Hi Thomas, yes there is a way. In the matter of fact you could support Eric5 evaluation an all all any FPGA and board without knowing the board connections if you limit the number Eric5 of ports being in used. The solution is completly secure and doesnt require any 3rd party membership programs or licensing. The question is if I tell you how to implement it and even provide some bare bones framework for it, what will there be for me? Hm, once you asked the solution I have in mind thats quite nice solution, well I was thinking about the similar thing for another processor a few hours ago - that was for different purpose but the same approuch would be applicable for Eric5 eval as well. Or in the matter of fact for eval of any softcore processor :) Antti PS Thomas if interested, then we are off channel from now on this topic use antti@truedream.org for direct emailArticle: 81648
? I thought we were going to take this offline, but since you are still posting here (fine with me, by the way): Yes. We found the schematic. We found the hand written note in the margin. Basically what Rob sent you from the hotline. If that doesn't work, then I am afraid we are at the end of our resources to provide help. Changes were later made to the XC4000 so that it did not have this issue. It is caused by a power supply glitch (and made worse if you use the power down mode as well). Remove the glitch, and the problem goes away. Perhaps you just need to add a 1,000 uF capacitor to the power suppy? (or remove one, to prevent the glitch) Time spent on the KNOWN CAUSE (the glitch) would be beneficial (in my opinion). You are unlikely (in fact: never going) to fix the chip. The issue was addressed in later families, and never in the XC3000. If anyone else out there can help, please do. Austin (and the rest of us back here at Xilinx that actually remember the XC3000)Article: 81649
Thomas Entner <aon.912710880@aon.at> wrote: > > > > evaluation fixed to some specific kit are USELESS - really > > I have 10+ evaluation boards but none of those you mentioned > > so there will be no evaluation for me. And I am not going to > > purchase an kit you support just to eval eric5, no way. > > > > just my 2 cents. if you really are planning fixed to board-evals > > you may as well not todo it at all > > > > Antti > > > > > Hmmm... > I hoped that I picked two boards that many people have (you really do not > have the Digilent S3-board?) > I found no other useful solution that is both simple for the customer and > protects our IP. Maybe you know one? (Please do not say: "Open Source", I > had already this discussion ;-) > For Altera, there would be OpenCore plus, but you need to be an AMPP, > and it is not easy to become that, so it does not help me. What about distributing a core with some cycle counter that disables the core after some cycles. I think there was a discussion about this "feature" used by some vendor for distributing evaluation cores. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
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