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Been there, done that,...If you have only one external device (SDRAM) it may be easy to adjust the trace/propagation... The situation get worse when more SDRAMS are ppopulated at different locations on your board. The board then need to be carefully designed and of course a second DLL is a big help too. Refer to xapp132 for details, Regard,Article: 81776
Symon wrote: > data_pins <= out_data when tristate = '0' else (others => 'Z'); > > "Weddick" <weddick@comcast.net> wrote in message > news:AdSdnRNxytxe-dbfRVn-oA@comcast.com... > >>Now in VHDL :) >> >> > I was just about to have to ask this very question. Much obliged.Article: 81777
What do u mean by an explicit number and how did you arrive at this value?Article: 81778
How did you arrive at the value 47 ( 2F hex) for the value 1.36..... What if the number is 1.122 instead?.... Is there a technique to do that.. ThankyouArticle: 81779
Thankyou Chris, Instead of 2^24, we need to plug in the deicmal equivalent of the 24 bit input we have. Is that right And also, recip <= conv_std_logic(2^24 * 1 / 1.36) -- not sure this is the right I am not sure if this would work because it again uses the '/' operator. This cannot be synthesized in XST. ThankyouArticle: 81780
Helpful hint: XC3000-type circuits are sensitive to slightly negative Vcc followed by a fast ramp-up. This might upset the deliberate imbalance in the configuration latches, and might (perhaps) cause a lock-up, although we have no record of this. It is just an enlightened speculation on our part. 15 years ago, the environment was generally slower, but now, especially with ECL ciruits in the vicinity, there might be a chance for such malfunction. Just a guess and a helpful hint. No response is needed, and, please, no insult. Peter AlfkeArticle: 81781
One of the things that has been bothering me through all of this is your
detecting of a 16 MHz clock. The configuration clock for these devices is
nominally 1 MHz, but actually it can range from 500 KHz to 2 Mhz. I am
certain that it does not use a faster clock and then divide it down. So I
have been beating my head about what this 16 MHz is. Well, I just figured
it out.
The baseline family is XC3000
The XC3100 family was a higher performance family
The XC3000A family had some routing enhancements which made use of some
previously dummy bits in the config bitstream.
The XC3100A has both the higher performance of the XC3100 family, and
the routing enhancements of the XC3000A
The XC3000L is a low power derivative of the XC3000A
(FYI, all bitstreams are the same length. Designs compiled for the XC3000
or XC3100, can be used with any of the 4 families. Designs compiled for
the XC3000A or XC3100A, may make use of the dummy bit, and so these
bitstreams can not be used in the XC3000 or XC3100 devices).
The performance enhancement in the XC3100/3100A family is achieved by the
use of on chip charge pumps. These create higher voltages that are used
on selected circuits in the FPGA. These charge pumps use free running
oscillators that are separate from the config oscillator, and are almost
certainly the 16 MHz that you are seeing. There is no way to actually
measure these oscillators, other than what you are doing with the spectrum
analyzer.
Since you are seeing that the 16 MHz is not present in devices that are
not operational, this means that the charge pumps are not all running.
Under this situation, I would expect that the chips would be basically
non operational, and no amount of banging on reset, D/P, or other control
pins is going to help. This is what you have reported.
I don't remember if the problem you are seeing is that devices that
operational, stop operating, without turning the system off, or that
when a system is turned on, sometimes it does not start up correctly.
(Have you ever said this?)
At this point it would seem that either the profile of the powerup
voltages, transients on the power lines while operational, or maybe
negative transients on data lines.
As an example, I have seen DRAMs fail due to excessive undershoot on
a data line, that violates the devices max negative spec. This is
a failure mode different from the well known problem of latchup. I.E.
the device fails, but does not exhibit the high power consumption
associated with latch up.
Philip Freidin
===================
Philip Freidin
philip.freidin@fpga-faq.org
Host for WWW.FPGA-FAQ.ORG
Article: 81782In article <1112290749.838313.314300@l41g2000cwc.googlegroups.com>, genlock <genlocks@gmail.com> wrote: >How did you arrive at the value 47 ( 2F hex) for the value 1.36..... Because 64/47 is nearly 1.36, so multiplying by 47 and dividing by 64 is about the same as dividing by 1.36 >What if the number is 1.122 instead?.... 1.122 is nearly 64/57, so multiplying by 57 and dividing by 64 is about the same as dividing by 1.122 >Is there a technique to do that.. Given X, for example 1.122, work out w = 2^k / X for k from 1 to some conveniently big number, and use the [k,w] pair that makes w nearest to a whole number. eg 1.5678, you try lots of k and find that 2^18 / 1.5678 is almost exactly 167205. This general technique is called fixed-point arithmetic. TomArticle: 81783
Hi early beta version is available for immediate downloads http://gforge.openchip.org/projects/fpgafreqmeter/ this version only supports Xilinx Cable III and Spartan 3 family (all devices) there are several limitations some jtag chain configuration may cause problems. Support for other FPGA (also Altera) will be added in the next releases. There is no info needed about your FPGA board and no ref. clock required, the application configures your FPGA to be a frequency meter - all external signal connected to the global clock inputs can be measured. AnttiArticle: 81784
v_mirgorodsky@yahoo.com wrote: >Hi, ALL! > >Several months ago I did schematic based design, implementing median >image filtering in Altera EP1K30TC144-2. It was running something close >to 150MHz without any explicit constraints, except target clock >frequency. At that time I did not need that much speed, because my >device was providing me data only 60MHz or below. > >Now we are busy with another device, capable to run at 150MHz and we >have XC2VP4 speed grade 6 Xilinx FPGA as a data processing unit within >the device. I rewrote design using VHDL language. During verification, >RTL schematic of synthesized VHDL code was looking exact like schematic >for Altera ACEX-1k device. The only issue was speed. VHDL reincarnation >of median filter was running only 134+MHz. > Xilinx has dedicated carry logic that makes anything with carries (adder, magnitude comparator) much faster. I know Spartan much better than Virtex, so what I know may not apply. But, what I'm wondering is if something you are doing in the schematic is excluding the use of the dedicated carry function. In one design I had to laboriously copy the way a Xilinx library macro used the carry components when I made up a slightly different macro. IIRC it also was a magnitude comparator, but I needed a greater than or equal to function. All I can say is the thing works, but I don't actually understand these carry components, I was just copying the thing pretty blindly. But, the macro synthesizes to a much smaller and faster instance on the Spartan chip when it uses these carry blocks. JonArticle: 81785
Hi, I am using JTAG and BSCAN_SPARTAN3 to scan register contents, but I need a way to disable and enable the BSCAN_SPARTAN3, there isn't an enable or disable pin that I see. Basically in my design, the data read out is always invalid until a point, so before that point, I want to turn BSCAN off. Does anyone know how to do this? Thanks, AnnArticle: 81786
Hi Jose, You need to be more specific. - what mode did you activate ? JTag ? Active serial ? - What exact device are you targeting ? - What device is selected in your project ? - what did the scan chain command "Auto-detect" return ? - Which file (extension) do you use for programming ? - Are you sure you have only one single line in the table ? - What option did you activate on the programmer widow ? - What is the exact error message you got ? qpf & qsf files are small and readable, you can cut and paste to an email. btw : Version 4.2 has been out for a while, no reason not to use it. In doubt, create a trivial design : couple of lines in vhdl with a blinking LED, clock and reset. Do this in an empty drectory and go all the way down to programming. BertArticle: 81787
Tom, Thankyou.Article: 81788
John_H wrote: > The results may be consistent according to the Verilog Language Reference > Manual but I wouldn't expect it. Can you explain how ? Is it clear from the Stratified Event queue (I mean the evaluation order ?)Article: 81789
Mark -
In testbenches, you typically want to be VERY careful to not let Z or X
values
accidently slip through as "don't cares". A lot of times, I'll code
testbenches like:
reg [15:0] expect;
reg [15:0] actual;
expect = 16'1234;
// get the actual value set...
if (actual !== expect)
begin
---complain---
end
Note the ! = = type compare. This means identically not-equal, no
"don't cares"
allowed. There is a corresponding === (3 equal signs).
Note that the OpenCores stuff is quite useful, but I usually have to
triple check
the code (and fix stuff) before I use it. It's usually a great
startying point for
study.
I hope this helps.
John P
Article: 81790Hi Matthias: Thanks for your reply. But I need to read the output (size: 256*256) from the BRAM and to store it in my desktop. When I discussed this problem with some of my friends here, they told me that I need to find the way to connect my user-logic to the PowerPC bus and then I need to read the data from the BRAM using the BRAM controller and store it in the desktop. Can you tell me the way to connect the user-logic with the bus and access the BRAM in virtex2pro? Thanks, Aroul Matthias Alles <alles@rhrk.uni-kl.de> wrote in message news:<d2f05h$4kb$1@news.uni-kl.de>... > Arul schrieb: > > I am using Virtex2pro - xc2vp30 to implement my HDL-based design. The > > output of my design will be stored in BlockRAM. How can I read my > > output from BlockRAM (BRAM)? Do I need to access BRAM using PowerPC? > > If so, how can I connect this BRAM with the PowerPC bus? I am a > > beginner of FPGA implementation. So, your advice will greatly help me. > > Using BRAM is quite easy. Take a look at the XST documentation, chapter > 2: "HDL Coding Techniques". There you find many examples how to describe > your design so that the synthesis will use the features of the FPGA. You > don't need the PowerPC to access the BRAMs. > > Matthias AllesArticle: 81791
Hi Vladimir,
In the Xilinx Software the default settings are
optimized
for Software Run Time - not for effort level. Are you using a PC or
Unix? I am more familiar with PC - on your PC if you right click on
the "synthesize -XST" and select properties you can choose effort
level and various other options.
SRL16's are an extremely efficient way to use 1 slice as a 16-deep
register. If you want to force the use of an actual flipflop in order to
meet timing - you can place a reset on the last flipflop. Flipflops
with resets go into regular flipflops - flipflop chains with no resets
will be able to take advantage of the SRL16 feature which could
save you a lot of area.
- Vic
v_mirgorodsky@yahoo.com wrote:
> Dear Antti Lukats,
>
> I am just curious, how to optimize VHDL code to use with Xilinx versus
> Altera? Yes, I know, some elements may be created more efficiently in
> Xilinx chips, anothers - in Altera chips. You may target your design to
> use one or another element, but generic triggers, multiplexers and
> adders are not optimizable for certain FPGA architecture within VHDL
> language without using black box primitives.
>
> My concern about Xilinx tools is that they are not giving comparable
> performance versus Altera tools with default settings.
>
> With best regards,
> Vladimir S. MIrgorodsky
Article: 81792On Fri, 25 Mar 2005 20:59:11 -0800, John Larkin <jjSNIPlarkin@highTHISlandPLEASEtechnology.XXX> wrote: >Hi, > >Given a Spartan 3 chip, what I'd like to do is arrange two pins as an >LVDS receiver *and* simultaneously have a regular 3.3 volt tristatable >driver drive one of those pins. From what I know of the output cell >architecture, it looks pretty likely that the hardware resources >exist. My guys are using ISE with schematic entry, and I'm not an ISE >driver, but they say it can't be done, or at least ISE won't let them >do it. > >Any ideas? It would be very cool if this would work; it would save us >a bunch of pins and a bunch of picofarads. > >Thanks, > >John Followup: My guys got it to work. They configured an LVDS transceiver i/o block, whose output stage is tristatable. The transmitter side turns out to be not lvds at all, but a pair of rail-to-rail tristate drivers. So they go into the layout editor and kluge one of the tristate drivers to permanently disable it, connecting its \enable to Vcc or something. Even though it works, it would create such a design maintenance hassle I think we won't do it. JohnArticle: 81793
On Thu, 31 Mar 2005 03:04:02 -0800, "Symon" <symon_brewer@hotmail.com> wrote: >"Quiet Desperation" <nospam@nospam.com> wrote in message >news:250320052307074615%nospam@nospam.com... >> In article <1111809749.291888.193280@f14g2000cwb.googlegroups.com>, >> Marc Randolph <mrand@my-deja.com> wrote: >> >>> For what data-rate(s)? >> >> Up to 3 Gbps on the fast side. >> >> Oh, and programmable logic levels, too. :) >> >> My currrent design is getting NCML from the upstream units. >> >> NCML. There's three other people in the world using NCML as far as I >> can tell. High level is 0 V, low level is -0.5V. Who invented that one? >> >> >> Thank goodness for On's Gigacomm parts. With differential signal they >> take almost anything from 0 to -2V. >> >> Those "any level in" buffers would be real nice in an FPGA. Hint, hint, >> Xilinx. >> >> And I want to go into an FPGA at 3 Gbps without any special Rocket I/O >> stuff. >> >> And as long as I'm dreaming, I'd like a pony. > >Dear Pony Dreamer, >So, I guess I use NCML except that I call my ground signal 2.5V! Seriously, >there are lots of designs out (t)here with 'ground' planes at voltages other >than 0V. Maybe that's something you could consider. > >Micrel make some similar parts to the On Semi ones, have you seen them? > >As for 'any-level-in', you'll find that Xilinx parts have a very wide common >mode range for their LVDS inputs. Just measured a Spartan3. In LVDS mode the inputs work nicely over a common-mode range of < 0.2 to *over* +3.3. I suspect the single-ended modes would work with a Vref in that range, too. JohnArticle: 81794
Marius Vollmer wrote:
[...]
> Now, all the SDRAM controllers that I have looked at use two DLLs (or
> DCMs) to produce the main clock for the controller. The Xilinx
> Applicatin note xapp134 even says:
>
> It is not possible to use one DLL to provide both the FPGA and
> SDRAM clocks since the SDRAM clock goes through an OBUF delay
> creating skew between the two clocks. Using two DLLs with the
same
> clock input and separate feedback signals achieves zero-delay
> between the input clock, the FPGA clock, and the SDRAM clock.
>
> I have only used one DCM for my SDRAM controller, and it seems to
work
> just fine (i.e., I can use the SDRAM as the framebuffer for a
1024x768
> VGA display), but I am of course worried that this is only by
> accident.
[... snip good drawing of OSC pin feeding two DLLs using a net called
"ext clock"...]
> OSC is the external oscillator. If I understand this arrangement
> right, it works as follows: DLL0 will make it so that there is zero
> phase difference between "main clock" and "ext clock". Likewise,
DLL1
> will produce zero phase difference between "sdram clock" and "ext
> clock". Thus, there is zero phase difference between "sdram clock"
> and "main clock".
Howdy Marius,
Very close. The difference doesn't impact anything in this case, but I
believe that the main and sdram clocks actually have zero phase offset
when compared to the GCLK input pin. Said another way, the DLL/DCM has
some automatic delay compensation in it to account for the delay
through the IBUFG and associated routing, at least when in
SYSTEM_SYNCHRONOUS mode (which is the default for DLLs and DCMs).
> What I am using right now looks like this:
>
> : :
> OSC --:---------------------------> OBUF --:---+
> : : | SDRAM
> : : |
> +---------------------------------:---+
> | :
> | buf clock
> | v
> +-> IBUFG ----> DLL0 ---> BUFG -+--> main clock
> ^ |
> +--------------+
>
> DLL0 will produce a zero phase difference between "main clock" and
> "buf clock", which is not exactly the "sdram clock" because of the
> IBUFG. Will that be a problem? My reasoning is that the data
signals
> go thru a IBUF as well, and thus it is OK to synchronize relative to
> the buffered clock. Assuming that a IBUFG and an IBUF produce the
> same amount of delay, it might even be 'more correct' than
> synchronizing to the unbuffered clock "sdram clock", since it is "buf
> data" which must have the correct setup/hold times.
>
> I fully expect my reasoning to be wrong. But where?
You've actually produced a variation of the original drawing. Here's a
simpler version of what you have, just ignoring the fact that the FPGA
buffers the clock:
OSC ---+
|
+--> SDRAM
|
|
|
| : buf clock
| : v
+--:---> IBUFG ----> DLL0 ---> BUFG -+--> main clock
: ^ |
: +--------------+
Assuming there isn't much phase difference between when the clock
reaches the SDRAM and when it reaches the GCLK input, the above is how
a "system synchronous" clock setup works. Your main clock will have
the same phase as (or often times, it will slightly lead) your input
clock signal, measured when it hits the FPGA GCLK pin.
So now the only question is if using the FPGA to buffer the clock
causes any problems. The answer is it should not. Keep in mind that
you can't expect your DLL/DCM to lock until well after the device is
configured and asserts its DONE bit. I've not read up on the S3 DCM,
but I assume it is the same as the in V2Pro, where you need to release
the reset to the DCM *after* the clock is present at the DCM input. As
long as you're doing that, I don't see a problem with it.
Good job!
Marc
Article: 81795Ann <ann.lai@analog.com> wrote in message news:<ee8d19d.-1@webx.sUN8CHnE>.. > Hi, I am using JTAG and BSCAN_SPARTAN3 to scan register contents, but I need >a way to disable and enable the BSCAN_SPARTAN3, there isn't an enable or >disable pin that I see. Basically in my design, the data read out is always >invalid until a point, so before that point, I want to turn BSCAN off. Does >anyone know how to do this? Thanks, Ann Hi Ann, there is no enable or disable available, you need other methods to 'sync' your data data is valid when USER1 (or USER2) is high but the best way is to look at some known pattern after SHIFT goes high and USER1 is high too, after that pattern has been then you are in the active phase of actual data transfer this is how its done in ChipScope as example ... http://gforge.openchip.org/projects/jtaghub I will post the JTAG HUB source shortly at the above link there you can see on example how to use BSCANArticle: 81796
depends on how the rom is generated. You can actually get it to create a smaller ROM if lines are duplicated and it will reduce further that the 548 missing lines. You should however define any unused locations even if they get optimised out. Simon "Acceed See" <invalicd@hotmail.com> wrote in message news:424a1c0a@news.starhub.net.sg... > When I choose Distribute Memory -> Depth 2048 -> Width 64 -> ROM -> LUT > based, > and my .coe file contains only 1500 words, what will ISE do during the P&R? > Will it > save the 548 words or implement them with zeros anyhow? > > My FPGA has ample LUT remaining, but little BRAM. I need to plug in some > more data > which is meant to be put in the BRAMs. Where is the place I can store these > data? > > >Article: 81797
Hi at all!
I tried to insert a Copmonent in my user logic of IPIF
COMPONENT asimonhw
PORT(
clk : IN std_logic; -- Clock Input
rst : IN std_logic; -- Reset Input
asip : IN std_logic; -- Input from Bus
asim : IN std_logic; -- Inputvom Bus
dataout : OUT std_logic_vector(31 downto 0); -- Output vector
enout : OUT std_logic -- Output signal
);
END COMPONENT;
When I insert a Component in my user logic and map this i get a
error:
ERROR:NgdBuild:466 - output pad net 'dataout<0>' has illegal
connection.
ok, then i put IBUF to outputs and OBUF to inputs of my component.
Then i implement the design with ISE and there were no problems. Then
I tried it to implement it with EDK and I get the Errors:
ERROR:NgdBuild:455 - logical net
'myasimon/myasimon/USER_LOGIC_I/dataout<0>' has
multiple drivers. The possible drivers causing this are:
pin dataout<0> on block
myasimon/myasimon/USER_LOGIC_I/Inst_test with type
test,
pin PAD on block myasimon/myasimon/USER_LOGIC_I/dataout<0>
with type PAD
ERROR:NgdBuild:455 - logical net
'myasimon/myasimon/USER_LOGIC_I/dataout<1>' has
multiple drivers. The possible drivers causing this are:
pin dataout<1> on block
myasimon/myasimon/USER_LOGIC_I/Inst_test with type
test,
pin PAD on block myasimon/myasimon/USER_LOGIC_I/dataout<1>
with type PAD
aso.
What for a problem can it be?
Is interessting, that thus IOs in the Component, wich are insertet in
UCF File are ok!
Article: 81798
Hello,
I want to use ethernet to transmit data from pc to ML310. I think
I can use Xilnet or LWIP library to establish the sockets to receive
data. But on board ML310, the ethernet is not connected to OPB bus
directly but through PCI bus. So when I choose Xilnet or LWIP
library,I cannot bind any instance to it. In this way, I cannot
generate library successfully and I cannot use these library for my
ethernet. Does anyone have this experience and tell me how to figure
it out?
While on board ML300, it works because ML310 is connected directly
to the OPB bus.
Much appreciates!!!! :D
Article: 81799
Hallo At all
I try to implement a IPCore in my EDK Design but without attachment on
any bus. My IP Core have some IOs and there are two important inputs,
too. That is Clock and Reset. Ok, when i try to connect the system
clock, which comes from DCM output, with my IP Core Clock input, I
get a error by generating bitsream.
The Error is:
ERROR:NgdBuild:455 - logical net 'fpga_0_SDRAM_8Mx32_SDRAM_Clk' has
multiple
drivers. The possible drivers causing this are:
pin PAD on block
plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/fpga_0_SDRAM_8Mx32_SDRAM_Cl
k with type PAD,
pin O on block dcm_0/dcm_0/CLK0_BUFG_INST with type BUFG
ERROR:NgdBuild:462 - input pad net 'fpga_0_SDRAM_8Mx32_SDRAM_Clk'
drives
multiple buffers. Possible pins causing this are: :
pin I on block obuf_56 with type OBUF,
pin I on block myasimonfi/myasimonfi/USER_LOGIC_I/OBUF_inst_clk
with type
OBUF,
pin I on block myasimonhw/myasimonhw/IBUF_inst with type IBUF
ERROR:NgdBuild:466 - input pad net 'fpga_0_SDRAM_8Mx32_SDRAM_Clk' has
illegal
connection. Possible pins causing this are:
pin C on block reset_block/reset_block/EXT_LPF/lpf_int with type
FDS,
pin C on block reset_block/reset_block/Rstc405resetcore with type
FDS,
pin C on block reset_block/reset_block/Peripheral_Reset_0 with
type FD,
pin C on block reset_block/reset_block/core_cnt_en with type FD,
pin C on block reset_block/reset_block/Bus_Struct_Reset_0 with
type FD,
pin C on block reset_block/reset_block/Core_Reset_Req_d3 with
type FD,
pin C on block reset_block/reset_block/EXT_LPF/asr_lpf_0 with
type FD,
pin C on block reset_block/reset_block/Rstc405resetchip with type
FDS,
pin C on block reset_block/reset_block/Rstc405resetsys with type
FD,
pin C on block reset_block/reset_block/Core_Reset_Req_d1 with
type FD,
pin C on block reset_block/reset_block/Core_Reset_Req_d2 with
type FD,
pin C on block reset_block/reset_block/CORE_RESET/q_int_3 with
type FDRE,
pin C on block reset_block/reset_block/CORE_RESET/q_int_0 with
type FDRE,
pin C on block reset_block/reset_block/CORE_RESET/q_int_1 with
type FDRE,
pin C on block reset_block/reset_block/CORE_RESET/q_int_2 with
type FDRE,
pin C on block reset_block/reset_block/EXT_LPF/asr_lpf_3 with
type FD,
pin C on block reset_block/reset_block/core_req_edge with type
FDS,
pin C on block reset_block/reset_block/EXT_LPF/exr_lpf_1 with
type FD,
pin C on block reset_block/reset_block/EXT_LPF/asr_lpf_2 with
type FD,
pin C on block reset_block/reset_block/EXT_LPF/asr_lpf_1 with
type FD
ERROR:NgdBuild:466 - input pad net 'fpga_0_SDRAM_8Mx32_SDRAM_Clk' has
illegal
connection. Possible pins causing this are:
pin C on block reset_block/reset_block/EXT_LPF/lpf_int with type
FDS,
pin C on block reset_block/reset_block/Rstc405resetcore with type
FDS,
pin C on block reset_block/reset_block/Peripheral_Reset_0 with
type FD,
pin C on block reset_block/reset_block/core_cnt_en with type FD,
pin C on block reset_block/reset_block/Bus_Struct_Reset_0 with
type FD,
pin C on block reset_block/reset_block/Core_Reset_Req_d3 with
type FD,
pin C on block reset_block/reset_block/EXT_LPF/asr_lpf_0 with
type FD,
pin C on block reset_block/reset_block/Rstc405resetchip with type
FDS,
pin C on block reset_block/reset_block/Rstc405resetsys with type
FD,
pin C on block reset_block/reset_block/Core_Reset_Req_d1 with
type FD,
pin C on block reset_block/reset_block/Core_Reset_Req_d2 with
type FD,
pin C on block reset_block/reset_block/CORE_RESET/q_int_3 with
type FDRE,
pin C on block reset_block/reset_block/CORE_RESET/q_int_0 with
type FDRE,
pin C on block reset_block/reset_block/CORE_RESET/q_int_1 with
type FDRE,
pin C on block reset_block/reset_block/CORE_RESET/q_int_2 with
type FDRE,
pin C on block reset_block/reset_block/EXT_LPF/asr_lpf_3 with
type FD,
pin C on block reset_block/reset_block/core_req_edge with type
FDS,
pin C on block reset_block/reset_block/EXT_LPF/exr_lpf_1 with
type FD,
pin C on block reset_block/reset_block/EXT_LPF/asr_lpf_2 with
type FD,
pin C on block reset_block/reset_block/EXT_LPF/asr_lpf_1 with
type FD
Hade some the same proble?
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