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"Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message news:4240455E.1020602@xilinx.com... > The V-4 PowerPC 405 in comparison displaces only 672 slices, > consumes 0.29mW/DMIP (0.44mW/MHz), runs up to 450 MHz and places > and routes in less then a second. Just try to get a soft processor to > match that. :) I think the PPC cores are a nice feature and are well executed. That said, 672 displaced slices are sufficient to hold two (or three austere) 32-bit pipelined RISC soft cores (requiring say 1 BRAM each), each running at ~1/3 of the PPC freq. So, for some applications (e.g. small memory footprint code and data 'controllers' that fit in a BRAM), the hard core is not a big (order of magnitude) win on MIPS/area. Can't 'speak to power' -- the hard processor core is surely much lower power. Properly RPM'd, a compact soft processor core will PAR in neglible time. Certainly the PPC core(s) are vastly more attractive targets for COTS software tools and OSs and infrastructure (docs, developer expertise, ...). See also [http://www.fpgacpu.org/log/feb01.html#010210]: "... this counterintuitive rule of thumb: one streamlined 32-bit soft CPU core optimized for programmable logic might need only half the silicon area of an elaborate 32-bit hard CPU core!" Jan GrayArticle: 81376
"Jan Gray" <jsgray@acm.org> schrieb im Newsbeitrag news:%wY%d.1173$z.144@newsread2.news.atl.earthlink.net... > "Ed McGettigan" <ed.mcgettigan@xilinx.com> wrote in message > news:4240455E.1020602@xilinx.com... > > The V-4 PowerPC 405 in comparison displaces only 672 slices, > > consumes 0.29mW/DMIP (0.44mW/MHz), runs up to 450 MHz and places > > and routes in less then a second. Just try to get a soft processor to > > match that. :) > > I think the PPC cores are a nice feature and are well executed. That said, > 672 displaced slices are sufficient to hold two (or three austere) 32-bit > pipelined RISC soft cores (requiring say 1 BRAM each), each running at ~1/3 > of the PPC freq. So, for some applications (e.g. small memory footprint > code and data 'controllers' that fit in a BRAM), the hard core is not a big > (order of magnitude) win on MIPS/area. Can't 'speak to power' -- the hard > processor core is surely much lower power. Properly RPM'd, a compact soft > processor core will PAR in neglible time. > > Certainly the PPC core(s) are vastly more attractive targets for COTS > software tools and OSs and infrastructure (docs, developer expertise, ...). > > See also [http://www.fpgacpu.org/log/feb01.html#010210]: "... this > counterintuitive rule of thumb: one streamlined 32-bit soft CPU core > optimized for programmable logic might need only half the silicon area of an > elaborate 32-bit hard CPU core!" > > Jan Gray > > LOL, mercy mercy, :) MicroBlaze is is defenetly more than 672/2 slices ! but I think I agree that the rule of thumb is OK! btw Jan I guess you are one of the few who could correctly answer the following FPGA-Quiz question: How many slices are needed to implement frequency divider by 2^37 ? ANSWER: Number of Slices: 3 out of 1408 0% Number of Slice Flip Flops: 2 out of 2816 0% Number of 4 input LUTs: 6 out of 2816 0% Number of bonded IOBs: 1 out of 140 0% Number of GCLKs: 1 out of 16 6% the above is synthesis report for divide by 2^n, n=21..37 P&R shows 3 slices for V2Pro or 4 slices for S3 AnttiArticle: 81377
On Tue, 22 Mar 2005 09:40:07 +1000, John Williams <jwilliams@itee.uq.edu.au> wrote: >Hi Henrik, [...] Hi John, >>>>I am not sure but is this got something to do with the DONE pin not >>>>going high. I dont know abt platform studio but then with Project >>>>navigator there is a setting which drives the done pin high that is if >>>>the done pin in the circuit is not connected to a pullup resistor. >>>[...] >> Damn, it did not work. After some hours it went mad at me again. [...] >I've seen similar strangeness on this board, maybe it's relevant. It >occurrs if I have the configuration mode jumpers set for Slave Serial >mode (e.g. for configuring from the PROM) but was actually configuring >via JTAG instead. > >The fix for me was to ensure that the mode jumpers were in the exactly >correct place. So, for JTAG, I think that's Open closed open closed >(from left to right). Or, for PROM-configuration, all closed. [...] All jumpers was actually closed. I tried to set the jumpers as described. By the way, it tells the same jumber positions in the manual for the board on p. 22. Unfortunatly it did not work. I additionally tried disabling the PROM by JP28, but that makes no difference either. I'll just power cycle the board a few times, and un- and replug until it suddenly works. But it would be nice to get it working every time. I will talk to a Memec guy on tuesday - if I have no solution by then I will try and ask him. And, if he has a solution, I will post it in here. Please let me know if you have any further ideas - I appreciate any help I get. :) -- HenrikArticle: 81378
I'm trying to get a gigabit ethernet design to work with Xilinx's Gige MAC (gemac 5.0/pcs combination) through the rocket IOs/optical transcievers on the ML300 board. I have a simple little design which drives two of the ethernets and prints out received info for one of the ethernets to the screen. With a fibre between the two active ethernets, all is fine: The MGTs and the PCSs sync up within a short time (<1 second for most of the ethernets, one is weaker and seems to require 2-4 seconds to sync up, so I'm not using that ethernet), and once it syncs up, packets are sent without an issue. But with a fibre to the PC on my desk (an HP GigE 1000-SX adaptor), the MGT and PCS don't sync up, so naturally it can't send or receive packets. The PC is sending out pings at .01 seconds on the ethernet (verified by TCP dump), so it isn't just an idle link. One worry in particular I have is on the clocking: The ML300 uses a 125 MHz ethernet reference clock, but the RocketIO wants a 62.5 MHz clock. Additionally, the userclk1's rising edges (the 62.5 MHz clock for the receiver/sender logic path) must be aligned with the falling edges of userclk2 (the 125 MHz clock). Thus, the clocking is DLL (/2) -> userclk/refclk DLL (shift 180) -> userclk2 Since the rocketIO manual recommends direct from the crystal (NOT through the DLL), I'm worried about the refclk (eg, jitter) but have no other choice. Does anyone have any suggestions? I've got a mini GBIC module on order so I can hook the ML300 up to a switch as well. Does anyone have a working design using the gemac core (not the older gigabit mac with integrated PCS) on the ML300 I could use for testing? -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 81379
"Kolja Sulimma": > Jan Bruns wrote: =20 >> Is board-impedance matching really an issue with 20mm / max.400 = mbpps? > no, but you will see a lot of inductive coupling in your design. Maybe = > you can add guard traces between you wires? Guard traces don't sem to help real much with this. Seems like I'll try to isolate not completly synchron signals. Gruss Jan BrunsArticle: 81380
lecroy7200@chek.com wrote: > A second failure took place. I reset all of the ICs, disabled the > cards master clock and left all of the FPGAs in the unprogrammed state. > Looking around I was not able to tell if the 1MHz signal was present > or not. It is so far down in the noise floor that it is virtually > undetectable. > > I decided to start looking at wider BWs. It appears that the internal > clock is not 1MHz, but much higher. Doing a sweep from 500KHz to 50MHz > and comparing the peaks, the IC that is in the strange state is missing > a peak at around 16-17MHz. > > This signal is changes part to part which I would expect for a sloppy > oscillator. > Again, the data sheets do not mention this. I will try and call Xilinx > today and see if they can confirm that this is the internal clock. That freq makes more sense than 1MHz for the buried osc, as 1MHz is relatively slow, so needs more specialised die area - in the old process of the 3000, a ring osc will give 16-17MHz region. Dividers are simple. If you need additional confirmation it is inside the FPGA, you could give the chip a squirt of freeze - ring osc's are temp dependant. They are likely to gate the loader osc, to save power, so this may only confirm you have exited the first power-up load state, but are unable to get back into load state. -jgArticle: 81381
Austin Lesea wrote: > lecroy, > Phil is on the right track. > > This part did have a brownout issue (if the the voltage dropped just > right, for just the right amount of time, and came back up) that would > place it in a locked state that could not be recovered until the power > was cycled. Do you recall how low the Vcc had to cycle, in order to correctly recover ? > > I solved this problem 15 years ago by using a Dallas Semi Power on Reset > part to reset the power supply if it detected a glitch. Sounds just like my power removal wdog.... :) How did you 'detect a glitch' - was that simply via Vcc lowering, or did that get an "I'm OK" signal from the FPGA ? I have wondered why more regulator chips do not offer this type of 'wide hysteresis' in their operation. -jgArticle: 81382
Jim, See below, Austin Jim Granville wrote: > Austin Lesea wrote: > >> lecroy, >> Phil is on the right track. >> >> This part did have a brownout issue (if the the voltage dropped just >> right, for just the right amount of time, and came back up) that would >> place it in a locked state that could not be recovered until the power >> was cycled. > > > Do you recall how low the Vcc had to cycle, in order to correctly recover ? As I recall, it had to go below 150 mV to 300 mV to recover. > >> >> I solved this problem 15 years ago by using a Dallas Semi Power on >> Reset part to reset the power supply if it detected a glitch. > > > Sounds just like my power removal wdog.... :) > How did you 'detect a glitch' - was that simply via Vcc lowering, or > did that get an "I'm OK" signal from the FPGA ? The POR IC had a settable threshold with an external resistive divider. It responding very quickly. I set it to the voltage range I knew I never wanted to be in. I think that was anything below 2.5V. For a 5V supply, I figured many bad things would happen if I went below 2.5V. > > I have wondered why more regulator chips do not offer this type of > 'wide hysteresis' in their operation. > > -jg > The problem is how do you tell? A band gap reference takes a lot of area, and is hard to be accurate in the really deep sub micron tecnologies. So if you can't measure more accurately that +/-5%, why bother?Article: 81383
Hello to all of you, currently I'm working on a "game of life" implementation on FPGA. Everything seems to work fine except for some pixel columns that are giving strange results. I'm quite convinced that the vhdl code, which you can find on my site ( http://jefpatat.freefronthost.com/vhdl/game%20of%20life/VHDL%20code.htm ) is correct. So I assume the error is related to timing problems of some kind. I'm relatively new to the whole FPGA stuff and have to learn everything myself, and timing and constraints is so complicated that I often don't know where to start. If you take a closer look at the VHDL code you can see that in the vgacontroller entity a signal xclk is generated, this is just a 25MHz signal, which is then used for a whole lot of synchronization. I have read about the clock nets available on FPGA and found something at http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf about DCM. I suppose there's a better way to doing things than mine, I just don't really know how. As a conclusion: how do I implement a clock on the "time net" with a frequency which is one fourth (25 MHz) of the hardware provided frequency (100 MHz) Kind regards, Jef PatatArticle: 81384
Hi all, I'm trying to test a filter I implemented with Xilinx ISE 6.1, so I created a testbench waveform. I'd like to import the input waveform from an ASCII file because the Pattern Generator can create only simple patterns. -- And on the 8th Day God said, "Murphy, take over!" |\ | |HomePage : http://nem01.altervista.org | \|emesis |XPN (my nr): http://xpn.altervista.orgArticle: 81385
Mentre io pensavo ad una intro simpatica "mediatronix" scriveva: > Hi: > Have a look at www.mediatronix.com/tools for a free simulator for DDC > designs. You will find a FIR designtool too. > Henk van Kampen. Thanks! this tools are great, I'm enjoying very much the filter designer. -- Ti prego Barbara, non qui! Non ci vede nessuno! (Daniele Luttazzi) |\ | |HomePage : http://nem01.altervista.org | \|emesis |XPN (my nr): http://xpn.altervista.orgArticle: 81386
Mentre io pensavo ad una intro simpatica "Ray Andraka" scriveva: > I missed your original post, so I'll reply here. > 1) the polyphase decimator is a mathematical manipulation to reduce the [...] Thanks, now it's clear. > 2) Multichannel operation is achieved by doubling the tap delays and > interleaving the samples from each channel. The physical filter is > operated at C times the sample rate (C is the number of channels). In > order to do that, you need a multiplied clock and your logic has to be > fast enough to operate at the increased clock rate. The reason for > doing this is to reduce the size of the hardware by time-sharing (the > classic time-area trade-off). Ok, I have some problems with clocks. What is the System Clock referenced in the IP core creation GUI? How it is related to the samples clock (the clock I use for the A/D)? It seems that this system clock has to be greater (or equal) than the sample clock. I have to send to different clock signals to the chip? Thanks for the answers, I also visited your web-site and I found in it some interesting papers. -- Reality is a crutch for people who can't handle drugs. |\ | |HomePage : http://nem01.altervista.org | \|emesis |XPN (my nr): http://xpn.altervista.orgArticle: 81387
Hi Antti, > LOL, mercy mercy, :) > MicroBlaze is is defenetly more than 672/2 slices ! You could use ERIC5... but it does not really compare to a PowerPC ;-) > > but I think I agree that the rule of thumb is OK! > > btw Jan I guess you are one of the few who could correctly > answer the following FPGA-Quiz question: > > How many slices are needed to implement frequency divider by 2^37 ? > > ANSWER: > Number of Slices: 3 out of 1408 0% > Number of Slice Flip Flops: 2 out of 2816 0% > Number of 4 input LUTs: 6 out of 2816 0% > Number of bonded IOBs: 1 out of 140 0% > Number of GCLKs: 1 out of 16 6% > > the above is synthesis report for divide by 2^n, n=21..37 > P&R shows 3 slices for V2Pro or 4 slices for S3 > This makes me curious: Is there other stuff like BRAM involved? Otherwise you HAVE to tell us how you do that (I would simply claim that this is not possible...) Thomas www.entner-electronics.comArticle: 81388
Hi everyone, can anybody tell me the real difference between - behavior (guess this is pure VHDL) - post-translate (guess this is after synthethis) - post-map - post place and route (guess this is when the design is "final" and is known where to be put in the FPGA) Thanks in advance Preben HolmArticle: 81389
Dear Jef, From what i understand, you are manually dividing the clock by 4. there is nothing wrong with this. Xilinx tool automatically identifies the clock signals, and tries assigning them a dedicated clock line. you can see it in the report of XST. What you need to do is to tell Xilinx tool that the clock generated by division is 25 MHz. Constraints! Otherwise, it would have no idea how to do the placement. However, the use of DCM is not mandatory is you want to only divide the clock by 4. But if you have too much, really too much combinational logic, then even the slow clock as 25 MHz will not meet timing. hope this helps. If you can give more details... best regards, Vladislav <tkanmijnischelen@hotmail.com> wrote in message news:1111521846.541234.254790@f14g2000cwb.googlegroups.com... > Hello to all of you, > > currently I'm working on a "game of life" implementation on FPGA. > Everything seems to work fine except for some pixel columns that are > giving strange results. > I'm quite convinced that the vhdl code, which you can find on my site ( > http://jefpatat.freefronthost.com/vhdl/game%20of%20life/VHDL%20code.htm > ) is correct. > So I assume the error is related to timing problems of some kind. I'm > relatively new to the whole FPGA stuff and have to learn everything > myself, and timing and constraints is so complicated that I often don't > know where to start. > If you take a closer look at the VHDL code you can see that in the > vgacontroller entity a signal xclk is generated, this is just a 25MHz > signal, which is then used for a whole lot of synchronization. > > I have read about the clock nets available on FPGA and found something > at http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf about DCM. I > suppose there's a better way to doing things than mine, I just don't > really know how. > > As a conclusion: how do I implement a clock on the "time net" with a > frequency which is one fourth (25 MHz) of the hardware provided > frequency (100 MHz) > > Kind regards, Jef Patat >Article: 81390
Hello to all of you, currently I'm working on a "game of life" implementation on FPGA. Everything seems to work fine except for some pixel columns that are giving strange results. I'm quite convinced that the vhdl code, which you can find on my site ( http://jefpatat.freefronthost.com/vhdl/game%20of%20life/VHDL%20code.htm ) is correct. So I assume the error is related to timing problems of some kind. I'm relatively new to the whole FPGA stuff and have to learn everything myself, and timing and constraints is so complicated that I often don't know where to start. If you take a closer look at the VHDL code you can see that in the vgacontroller entity a signal xclk is generated, this is just a 25MHz signal, which is then used for a whole lot of synchronization. I have read about the clock nets available on FPGA and found something at http://www.xilinx.com/bvdocs/appnotes/xapp462.pdf about DCM. I suppose there's a better way to doing things than mine, I just don't really know how. As a conclusion: how do I implement a clock on the "time net" with a frequency which is one fourth (25 MHz) of the hardware provided frequency (100 MHz) Kind regards, Jef PatatArticle: 81391
"Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca> wrote in message news:<Wr-dnbXaVOLeuaLfRVn-ow@rogers.com>... > > Try out Quartus II. You can download the free version (called "Web > Edition") from our website www.altera.com. The Quartus GUI is generally > pretty easy-to-use and has the look-and-feel of a modern Windows > application. > > > Paul Leventis > Altera Corp. Not that I expect any different from the group Altera pusher, but have you ever tried ISE??? I can't believe that even you would even suggest Quartus, it is just as backwards as the ISE interface!Article: 81392
>> >> but I think I agree that the rule of thumb is OK! >> >> btw Jan I guess you are one of the few who could correctly >> answer the following FPGA-Quiz question: >> >> How many slices are needed to implement frequency divider by 2^37 ? >> >> ANSWER: >> Number of Slices: 3 out of 1408 0% >> Number of Slice Flip Flops: 2 out of 2816 0% >> Number of 4 input LUTs: 6 out of 2816 0% >> Number of bonded IOBs: 1 out of 140 0% >> Number of GCLKs: 1 out of 16 6% >> >> the above is synthesis report for divide by 2^n, n=21..37 >> P&R shows 3 slices for V2Pro or 4 slices for S3 >> > > This makes me curious: Is there other stuff like BRAM > involved? Otherwise you HAVE to tell us how you do that (I would simply > claim that this is not possible...) > > Thomas > > www.entner-electronics.com > Hi Antti, as a long time Altera-user I just remembered that the Xilinx-slices support distributed RAM and stuff... I suppose you take advantage of that. Still very impressive! ThomasArticle: 81393
I am currently trying to use the SN54LVT8980A JTAG TAP MASTER controller to program FPGA PROMS. I have put the chip on a logic analyzer and have found that I get nothing out (no TDO, no CLK when in gated mode, not TMS) when executing a instruction register scan or when I execute a data register scan. However, I do get the above mentioned signals when I execute either a recirculate instruction scan or a recirculate data scan. Moreover, I seem to have to write 5 times to the TDO register before the STATUS register indicates that it is full. Has anyone ever used this chip before? Maybe someone could send me a code snippet to get it to perform a simple instruction-scan or data-scan. Once I get that going I can probably implement my software-based PROM programmer going used this chip. Thanks, AndyArticle: 81394
In article <gp0041t31g725skrq3ff4n38pfk9pi3bqh@4ax.com>, lb.edc@pandora.be says... > >I do agree with Ben, there are a lot of super-PALs (or CPLDs) with >JTAG capabilities. On the other hand, GALs are a very good replacement >for PALs and these are still available. If you chech Lattice's >website, you will find some documents about programmer support for >GAL's and therefore also PAL's. > >Regards, > >Luc > >On Tue, 22 Mar 2005 08:23:07 GMT, Ben Twijnstra <btwijnstra@gmail.com> >wrote: > >>Hi Gregg, >> >>> Hello from the Eighth Doctor >>> (Apologies if this question is not group appropriate.) >>> It seems my company's perenial problem with the PAL chips have sprouted >>> again. The same individual that we created a something or other for, using >>> a collection of PAL chips, and some normal glue logic wants us to make >>> more of these things. Essentially a follow on to that thing. What it's >>> supposed to do isn't the problem. Yet. It's the programming of the blank >>> parts that is the problem. >> >>Can't you convince your colleague to use something slightly more modern than >>a PAL? I see more and more manufacturers dropping support for PALs (great >>pity), and PALASM is not the most user-friendly way to develop logic or >>testing harnesses in. >> >>Especially now that (s)he is going to use multiple PALs on a board (s)he >>might take a look at CPLDs (sort of a super-PAL), which have a larger >>capacity for logic and registers, plus the great majority can simply be >>programmed while already soldered on the board through JTAG. >> >>I'm professionally biased towards Altera MAX devices, but there's a whole >>bunch of other CPLD vendors that offer JTAG programmability. >> >>Best regards, >> >> >>Ben > Hello from the Eighth Doctor We did then. We did this year. No such look. The customer had heard about the wonders of PAL devices from someplace and wanted those devices. So we are sticking with them, for now at least. Fortunately our chosen supplier seems to have a good inventory at the moment. I'm probably going to contact Lattice anyway since I need to find out if they have any agents in the NYC area, who can program a few devices for me, since the programmer won't be here in time for use by us. --- Gregg drwho8 atsign att dot netArticle: 81395
Hi! I want to store the program code for the Microblaze processor in my serial configuration Flash and use a bootloader to copy it to the external memory. Is there an OPB component available that connects to the serial Xilinx Flash, when the Flash is connected to the FPGA like on the Spartan3 Starter Kit Board? Thanks, Matthias AllesArticle: 81396
Matthias, Check out Xilinx Application Note 482. It provides a reference design to accomplish exactly what you are requesting and the example provided works for the Xilinx Spartan-3 Starter kit board. http://www.xilinx.com/bvdocs/appnotes/xapp482.pdf Cheers, Shalin- Matthias Alles wrote: > Hi! > > I want to store the program code for the Microblaze processor in my > serial configuration Flash and use a bootloader to copy it to the > external memory. Is there an OPB component available that connects to > the serial Xilinx Flash, when the Flash is connected to the FPGA like on > the Spartan3 Starter Kit Board? > > Thanks, > Matthias AllesArticle: 81397
Using SRL16 ? you can in one lut have the output set to 1 every 16 clock I think 2^4. So using that as Clock Enable to another you can have 2^(4*n) with n the number of LUT so that would make 2^(4*6) = 2^24 ... damn, not enough. Sylvain Thomas Entner wrote: >>>but I think I agree that the rule of thumb is OK! >>> >>>btw Jan I guess you are one of the few who could correctly >>>answer the following FPGA-Quiz question: >>> >>>How many slices are needed to implement frequency divider by 2^37 ? >>> >>>ANSWER: >>>Number of Slices: 3 out of 1408 0% >>>Number of Slice Flip Flops: 2 out of 2816 0% >>>Number of 4 input LUTs: 6 out of 2816 0% >>>Number of bonded IOBs: 1 out of 140 0% >>>Number of GCLKs: 1 out of 16 6% >>> >>>the above is synthesis report for divide by 2^n, n=21..37 >>>P&R shows 3 slices for V2Pro or 4 slices for S3 >>> >> >>This makes me curious: Is there other stuff like BRAM >>involved? Otherwise you HAVE to tell us how you do that (I would simply >>claim that this is not possible...) >> >>Thomas >> >>www.entner-electronics.com >> > > > Hi Antti, > > as a long time Altera-user I just remembered that the Xilinx-slices support > distributed RAM and stuff... I suppose you take advantage of that. Still > very impressive! > > Thomas > >Article: 81398
Austin Lesea wrote: >> I have wondered why more regulator chips do not offer this type of >> 'wide hysteresis' in their operation. >> >> -jg >> > > The problem is how do you tell? A band gap reference takes a lot of > area, and is hard to be accurate in the really deep sub micron > tecnologies. So if you can't measure more accurately that +/-5%, why > bother? I did say regulator chip, not FPGA :). In the analog realm of regulators this is a no-brainer, all the support silicon is already there, it just needs a difference in the enable/disable details. Regulators/reset generators on FPGA is another topic entirely... The best indicator of what is possible, are the MOSFET charge based Vref chips from Xicor (now intersil), and the bigger embedded controllers, esp towards the Automotive area, where on chip regulators are more and more common. Todays FPGAs are such power hogs, that this is less practical, but on the 'zero power' CPLDs it makes sense to engineer it better than the present numbers. -jgArticle: 81399
What is the best backup procedure for Xilinx? I have used snapshot which seems to copy the whole directory into the current director. You can attach a description to it. Archive compresses the data. And Save Project As seems to get rid of some of the clutter in the directory. b r a d @ a i v i s i o n . c o m
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