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xing1234@yahoo.com wrote: > Thanks Gabor and JJ for your reply. > > If I really want to implement the 300Kbyte ROM in FPGA, I guess I have > to use at least Xilinx Virtex II 6000, which has 144 Block RAM(totally > 324KByte). I may need to think about using external memory. A memory-centric part like the SX35 would likely be a lot more cost effective (or to be fair, maybe an Altera EP2S60). Something that hasn't been discussed is how your ROM is organized though. If it is 8 bits wide and hugely deep, it may be challenging to meet timing with the address lines needing to go to all corners of the chip (or muxing the outputs, although perhaps you can use tri-state bus). Or if it is organized as a bunch of strange sized ROM's, you may end up with parts of some ROM's being wasted in the FPGA (meaning that you need more than 300 KBytes total). > The question comes from an eveluation of an hardware IP, which has 500K > logic gate counts in ASIC plus 300KByte ROM. When I consider if I can > implement it in FPGA, the first thing is what FPGA and how many FPGAs I > need for. For this case, I can barely get ROM done on Virtex 6000, but > not sure if the rest resource of 6000 can accomendate the 500K logics. > > Do I have to synthesis the Logic in Synplicity and place&route it to > know how many slices it requires? or there is a way so that I can know > in advance? Not only do you need to know the size of the design when it is targetted to an FPGA (using Synplify or some other synthesis tool), but you need to know how fast it will run. In my experience, ASIC designers almost ignore their levels of logic. If your ASIC is that way, it may not meet the speed targets you need when targetted to an FPGA. Good luck, MarcArticle: 81001
On Mon, 14 Mar 2005 13:51:51 -0800, sk wrote:
> Hello group,
> I have a design that implements Ethernet (10-base) without a PHY chip
> straight into an Altera Cyclone. Things are working fine mostly, but
> I'd like to improve the electrical interface if possible.
>
You have GOT to be kidding.
> So far I've been using a transformer and two resistors into a standard
> 3.3V LVTTL pin. Levels were not optimal, so in some rare situations I
> lost connection.
>
> I've tried something different now which seems to work much better:
> connecting the transformer directly to 2 pins configured as LVDS (+
> 100Ohm termination resistor).
>
> I admit that this is somewhat of a hack, but I'd be happy about your
> opinion wether it's a really bad one, e.g. if the voltage levels (Vpp =
> 2.5V) out of the transformer might kill the inputs.
>
I don't think normal ethernet signals will kill the inputs, but the
datasheet should say explicitly what the safe voltage levels are.
Transients are another matter. Why not just use a phy?
Also, what type of Ethernet uses simple differential signalling? I'm
not really familiar with 10 megabit Ethernet, but fast Ethernet and
Gigabit Ethernet use complex signalling that can't be detected with a
simple differential receiver.
> thanks,
> Sukandar
Finally, are you doing anything to set the common mode voltage? I would
probably do something like this (use courier or similar to view the
following ascii art schematic):
VCC
___
|
/
\
/ 10 kOhms
\
|
-----+ +--------------------+---lvds+
(||) /
(||) \ 100 Ohms
(||)transformer /
(||) \
-----+ +--------------------+---lvds-
|
/
\ 10 kOhms
/
\
| |
---
GND
regards,
Mac
Article: 81002lecroy7200@chek.com wrote: > > There are several layers of ECL before getting to the Xilinx parts > other startup tales (that may not fit your one-of-N AWOL symptoms): If that's real negative ECL, I have had similar bizarre powerup problems with both an ancient Altera CPLD and an Atmel AVR, when residing in a mixed TTL/ECL design: A temporary failure, or delayed startup, of the +5.0V supply would allow the -5.2V supply to slightly reverse bias the +5.0V rail. Under these conditions, when the +5.0V supply did come up, the CPLD or uC would not initialize properly, until both supplies were removed and then restarted at the same time. Also, TTL<->ECL translators can have strange clamp bias paths into a pin when one supply fails ( IIRC, more of a severe problem in PECL across boards with a failed supply on one card ) BrianArticle: 81003
"Isidoros Sideris" <isidoros@microlab.ntua.gr> wrote in message news:d172ti$i9t$1@ulysses.noc.ntua.gr... >I want to implement a register file with 2 read ports and one write port in > a Spartan3. Is this feasible using LUTs? Another solution is to use flip > flops, but I overuse the resources in this way. I recommend you google for "register file fpga", for example see www.fpgacpu.org/usenet/regfile2.html and my Circuit Cellar series on implementing a RISC in an FPGA at www.fpgacpu.org/xsoc/cc.html. If you can design your instruction set so the write port is always or usually one of the read ports, you might use a single bank of dual ported LUT RAM. That was one of the ideas behind the simpler gr0000 processors (www.fpgacpu.org/papers/soc-gr0040-paper.pdf). Note in Spartan-3 only every other column of LUTs may be used as LUT RAM. :-( Also, with Virtex-4's BlockRAM pipelined output registers, BlockRAM is finally becoming competitive with LUT RAM for register files (see also www.fpgacpu.org/usenet/bb.html). There have also been some discussions on this the fpga-cpu mailing list. For example, start reading at http://groups.yahoo.com/group/fpga-cpu/messagesearch?query=%22register%20file%22. Jan GrayArticle: 81004
One other criterion to consider - is there an easily installable platform independant free implementation of a simulator available? Verilog wins on this one with Icarus. And do your generic/generation magic with a scripting language that generates verilog as output. Then you are in control of your toolchain. ... apart from the synthesis tool of course :-) Cheers MarkArticle: 81005
Hi all, I'm trying to implement two algorithms in synthesizable verilog: 1) insertion sort two presort arrays 2) last step of merge sort to merge presorted arrays in parallel Code fragments or hints are very welcome :) Thanks, ChrisArticle: 81006
When testing an analog circuit, I need to transport two channels of data each of 16-bit at 40MHz from PC to FPGA. The FPGA receives the data and performs some preprocessing. I need an V2-6000 FPGA. Does a USB 2.0 satisfy my data rate requirement? Which evaluation board satisfy my requirement?Article: 81007
Simple answer is no. 16*40M = 640MBit. USB2 has 480 MBit as maximum rate and you probably would not get that consistantly due to other system factors. PCI has the best chance in the PC environment. USB controllers etc often are on the PCI bus anyway within the PC so better to go straight to PCI. 32Bit/33MHz PCI has a theoretical 1056 MBit capacity. Again PCI and system level factors will give a maximum data rate much lower than the maximum. Faster and/or wider PCI will give you a much better chance of transferring your data. -- John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Sea Squid" <Sea.Squid@hotmail.com> wrote in message news:4237f2d7@news.starhub.net.sg... > When testing an analog circuit, I need to transport two channels of > data each of 16-bit at 40MHz from PC to FPGA. The FPGA receives > the data and performs some preprocessing. I need an V2-6000 FPGA. > > Does a USB 2.0 satisfy my data rate requirement? > > Which evaluation board satisfy my requirement? > > >Article: 81008
Hi together. I'm relatively new with FPGAs and I have no experience with rams. Now I'm working on a ram controller for a MEMEC FPGA board with a xilinx spartan IIE (@100 MHz). It should be a very simple module, and speed is not very important, because the data to be written come at a low frequency. So I designed a state-machine, which handles the signals. Unfortunately it does not work, although in the simulation the signals have the correct form. At this point I have some questions: 1.) Do I have to instantiate special IO-buffers for the ram signals? The synthesis creates IO-Buffers but I'm not sure if it is OK to do it this way. 2.) The datasheet of the ram modules show that the signals must be valid for a defined time, before and after the posedge of the ram clock. Is it an appropriate way the set up the signals at the posedge of the clock and use the negedge for the ram? 3.) Do I have to set NOP commands for the ram? The timing diagrams show NOPs, which have a special operation command. On the timing diagram for the AC parameters there are no NOP commands show, simple no command is set. How do I have to handle this? I'd really appreciate every piece of advice! Thanks in advance. MichaelArticle: 81009
I was wondering about possible uses of the FPSLIC devices. I feel there must be an application where they would be more suited than other SoC solutions but I really can't come up with anything. If any one has any suggestions they would be greatly received.Article: 81010
John Adair wrote: > Simple answer is no. 16*40M = 640MBit. USB2 has 480 MBit as maximum > rate and you probably would not get that consistantly due to other > system factors. Actually the original poster specified 2 channels of 16 bits at 40MHz so you're looking at 2*2*40 = 160MB/s = 1280Mb/s. > PCI has the best chance in the PC environment. USB controllers etc > often are on the PCI bus anyway within the PC so better to go > straight to PCI. 32Bit/33MHz PCI has a theoretical 1056 MBit > capacity. The *absolute* best you'll get out of PCI 32/33MHz is 100MB/s and that's under ideal conditions with nothing else hogging the PCI bus. Even at double the PCI bandwidth I'd say you're pushing things to get 160 - you'd want nothing much else happening on the bus for that (not much disk i/o - and that includes swapping) and AGP graphics. I'm afraid you may be looking at 64/66MHz PCI or similar. I'm wondering where your data source is? If it's *also* on the PCI bus (and I'm guessing there's a similar amount of data to be moved) then you're really stuffed unless you can setup a DMA straight from the source to the FPGA. Regards, MarkArticle: 81011
Hi Jan jandc schrieb: >> I wonder if there is any simple way to send the data from a block-ram >> to the RS232-interface, without the need to write all the RS232 >> VHDL-code myself! > > > There you go. And can we now stop requesting RS232 stuff? ;) Sorry, but we can't :-) There are still some packages missing to make it work: > library work; > use work.shift_registers.all; > library nicethings; > use nicethings.ASCII.all, nicethings.overloaded_std_logic_arith.all; In another posting on http://www.castalk.com/ftopic211.html you posted a buffer_procedures package. This package had shifting procedures with similar names to those expected in the shift_registers package. Is the shift_registers package a replacement for the buffer_procedures package? There are also two packages that can be compiled to nicethings. (ascii_constants and ascii_functions). Are these former versions of nicethings ascii and nicethings.overloaded_std_logic_arith?? It would be nice if you could post the missing packages as well, so we can test your design. Besides that, your RS232 core looks good and clearly coded, AND is one of the rare examples that supports RTS/CTS handshaking. I made a similar thing years ago with schematic entry. The q&d-VHDL port of that is quite unreadable and not suitable as a vhdl reference design. I would like to compare these two designs, if only I had the missing packages. best regards Eilert Backhus backhus_who hates spam__at__no spam wanted_isms.hs-bremen.de_where spam is deleted anyway_Article: 81012
> If that's real negative ECL, I have had similar bizarre powerup > problems with both an ancient Altera CPLD and an Atmel AVR, when > residing in a mixed TTL/ECL design: Yes, it's real negative ECL. 100H603s are used for the translation. > A temporary failure, or delayed startup, of the +5.0V supply would > allow the -5.2V supply to slightly reverse bias the +5.0V rail. > > Under these conditions, when the +5.0V supply did come up, > the CPLD or uC would not initialize properly, until both supplies > were removed and then restarted at the same time. This is interesting. During the power supply design, a lot of pain went into the sequencing. A few of the parts have problems when the power is not brought up correcly. The problem so far seems to have happened not during power cycles of the instruments, but while the instruments are in their normal run mode. > Also, TTL<->ECL translators can have strange clamp bias paths > into a pin when one supply fails ( IIRC, more of a severe problem > in PECL across boards with a failed supply on one card ) It's a good point.Article: 81013
Seems you might also consider just putting an SDRam (even 1GByte is <<$ than PCI 64) next to signal capture and download at leasure later on using any modest IO scheme.. How long are these samples to last for?, if less than 1B, just buffer it. If you absolutely need continuous capture then you have a more interesting challenge! BTW there are data capture boxes you can get off the shelf ie USB connected logic analyzer for a few $100. If their buffers are big enough maybe those can be used at least in a lab setup. regards johnjakson at usa dot comArticle: 81014
Hi,
what does the sensitivity-list actually do.
Normally I only put the clock-signal to the list, but sometimes f.x. here:
process(clk, reset)
begin
if (reset = '1') then
count <= preset;
elsif rising_edge(clk) then
if (ce = '1') then
count <= count + 1;
if (count(11) = '1') then
count <= preset;
end if;
end if;
end if;
end process;
then this WARNING is given:
WARNING:Xst:819 - C:/XilinxProjects/DigScope/counter11bit.vhd line 21:
The following signals are missing in the process sensitivity list:
preset.
I don't understand why this signal should be in the sensitivity-list!
Thanks
Preben Holm
Article: 81015Preben Holm wrote: > Hi, > > what does the sensitivity-list actually do. > > Normally I only put the clock-signal to the list, but sometimes f.x. here: > > process(clk, reset) > begin > if (reset = '1') then > count <= preset; > elsif rising_edge(clk) then > if (ce = '1') then > count <= count + 1; > if (count(11) = '1') then > count <= preset; > end if; > end if; > end if; > end process; > > then this WARNING is given: > > WARNING:Xst:819 - C:/XilinxProjects/DigScope/counter11bit.vhd line 21: > The following signals are missing in the process sensitivity list: > preset. > > > I don't understand why this signal should be in the sensitivity-list! > The sensitivity list indicates to a simulator which signals to watch for changes. In this case if you wanted to synthesize an asynchronous latch for preset, normally any time reset is active changes on preset would trickle through to count. Thus the simulator would want to watch for changes in preset during this time and would need preset in the sensitivity list to do that. As coded, a simulator would only look at preset on change of reset or clk. This would correspond to a multi-edge-triggered flip-flop that the FPGA cannot create. That's why the synthesizer complains. Since you got a warning and not an error, my guess is that the synthesizer made the latched preset you intended, however your synthesized result will not match you behavioral simulation. Hope this helps, Gabor > > > Thanks > Preben HolmArticle: 81016
Hi wo knows a cheap 100mbit/s ethernet MAC/PHY daughterboard (e.g. equipped with LAN91C111 from smsc) to use with an fpga dev.board? thanks marcoArticle: 81017
You receive this WARNING because you use a signal declaration for the
preset. In this case, you have to add 'preset' in the sensitivity list.
But it is not a good implementation to using dynamic signal for
initializing registers (your count) via a asynchronous reset.
a) I would put your preset in a generic declaration.
b) Or I would use a synchronous reset schem for your preset
> process(clk, reset)
> begin
> if (reset = '1') then
> count <= (OTHERS => '0'); -- or '1' or "00..11" or a generic
value
> elsif rising_edge(clk) then
if (reset_sync = '1') then
count <= preset;
> elsif (ce = '1') then
> count <= count + 1;
> if (count(11) = '1') then
> count <= preset;
> end if;
> end if;
> end if;
> end process;
Best regards,
Laurent
www.amontec.com
Preben Holm wrote:
> Hi,
>
> what does the sensitivity-list actually do.
>
> Normally I only put the clock-signal to the list, but sometimes f.x. here:
>
> process(clk, reset)
> begin
> if (reset = '1') then
> count <= preset;
> elsif rising_edge(clk) then
> if (ce = '1') then
> count <= count + 1;
> if (count(11) = '1') then
> count <= preset;
> end if;
> end if;
> end if;
> end process;
>
> then this WARNING is given:
>
> WARNING:Xst:819 - C:/XilinxProjects/DigScope/counter11bit.vhd line 21:
> The following signals are missing in the process sensitivity list:
> preset.
>
>
> I don't understand why this signal should be in the sensitivity-list!
>
>
>
> Thanks
> Preben Holm
Article: 81018
When will the FPGA vendors support system verilog? System Verilog adds
structures to Verilog 2001, so you can say: bus.data, bus.addr, etc.
When will VCS support Verilog 2001? It lacks the ability to make
parameterized modules if you use the new "ANSI" style declaration syntax:
module foo #(parameter WIDTH=10) // <-- this part not supported in VCS
(
input clk,
input reset_l,
input [WIDTH-1:0] in,
output reg [WIDTH-1:0] out
);
...
endmodule
Also most tools support 'always @*', but not vcs :-(
Most designers still code in pre-v2001 style because of inconsistent vendor
support for the standard.
When will Altera Verilog support the 'wor' data type? I use this to make
or-tree buses:
wor [7:0] foo;
assign foo = enable_1 ? data_1 : 0;
assign foo = enable_2 ? data_2 : 0;
When will Xilinx fix its buggy casex in xst? (it works in 5.2i)
The complaint about verilog's lack of type checking never bothered me
because I used Synplicity- it was just slightly stricter than vcs. Now I
use xst and altera's- both seem to be more lax, but I can't remember the
details right now.
Anyway, I still prefer Verilog over VHDL's horrible syntax.
In article <1110955980.612805.3910@z14g2000cwz.googlegroups.com>,
mark andrew <mark.andrew@gmail.com> wrote:
>One other criterion to consider - is there an easily installable
>platform independant free implementation of a simulator available?
>Verilog wins on this one with Icarus.
>
>And do your generic/generation magic with a scripting language that
>generates verilog as output. Then you are in control of your toolchain.
>
>... apart from the synthesis tool of course :-)
>
>Cheers
>
>Mark
>
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 81019dear I need to implement the following. 2 microblazes and 2 Data BRAMs (assumeing 1 Instruction BRAM for both ). Both of Data BRAMS range 0x0000 - 0x3fff and each belongs to each microblaze. What is important for me is to share the data memory, such that the programmer write ONE program and considers the memory as ONE global memory with 0x0000 - 7fff. I expect that MMU (address translation) unit is necessary. I wonder if this is possible with one (shared) with 1 OPB. Problem is I have no experience on this. Is these possible? If yes, how? :) If someone gives me some hint or suggestion, it will greatly appreciated.Article: 81020
Hi to all of you, this is kind of an SOS. Some time ago I started with a simple idea: implement the game of life on a FPGA. Everything seemed to work out great but now I'm completely stuck, I need help from some smarter individuals. I assume my problem relates to a warning given in the log file: Register X is equivalent to Y, but I'm not sure. You can find all the explaining and problems at my site, I especially made some pages to explain my problem. http://jefpatat.freefronthost.com/vhdl/game%20of%20life/index.htm I hope some-one can help me out on this, I think it would be a really nice demo. Thanks in advance, Jef PatatArticle: 81021
Then what's the best way to know how fast my logic can run on the FPGAs? Do I have to use the synthesis(from synplify for example) result to fgiure out the maximum frequency? any other methods? THanks! Marc Randolph wrote: > xing1234@yahoo.com wrote: > > Thanks Gabor and JJ for your reply. > > > > If I really want to implement the 300Kbyte ROM in FPGA, I guess I > have > > to use at least Xilinx Virtex II 6000, which has 144 Block > RAM(totally > > 324KByte). I may need to think about using external memory. > > A memory-centric part like the SX35 would likely be a lot more cost > effective (or to be fair, maybe an Altera EP2S60). Something that > hasn't been discussed is how your ROM is organized though. If it is 8 > bits wide and hugely deep, it may be challenging to meet timing with > the address lines needing to go to all corners of the chip (or muxing > the outputs, although perhaps you can use tri-state bus). Or if it is > organized as a bunch of strange sized ROM's, you may end up with parts > of some ROM's being wasted in the FPGA (meaning that you need more than > 300 KBytes total). > > > The question comes from an eveluation of an hardware IP, which has > 500K > > logic gate counts in ASIC plus 300KByte ROM. When I consider if I can > > implement it in FPGA, the first thing is what FPGA and how many FPGAs > I > > need for. For this case, I can barely get ROM done on Virtex 6000, > but > > not sure if the rest resource of 6000 can accomendate the 500K > logics. > > > > Do I have to synthesis the Logic in Synplicity and place&route it to > > know how many slices it requires? or there is a way so that I can > know > > in advance? > > Not only do you need to know the size of the design when it is > targetted to an FPGA (using Synplify or some other synthesis tool), but > you need to know how fast it will run. In my experience, ASIC > designers almost ignore their levels of logic. If your ASIC is that > way, it may not meet the speed targets you need when targetted to an > FPGA. > > Good luck, > > MarcArticle: 81022
On a sunny day (16 Mar 2005 06:46:47 -0800) it happened msd@email.it (msd) wrote in <d4891f3f.0503160646.6d11b3c9@posting.google.com>: >Hi >wo knows a cheap 100mbit/s ethernet MAC/PHY daughterboard (e.g. equipped with >LAN91C111 from smsc) to use with an fpga dev.board? > >thanks >marco > http://www.mcselec.com/commerce/product_info.php?cPath=1_26&products_id=39 I have not used this, but it seems fun, as most protocols are also handled by the w3100A. Maybe in using this you need no FPGA!Article: 81023
Preben Holm wrote:
> what does the sensitivity-list actually do.
It represents a list of signal events to
wait for at the end of the process.
> WARNING:Xst:819 - C:/XilinxProjects/DigScope/counter11bit.vhd line 21:
> The following signals are missing in the process sensitivity list:
> preset.
> I don't understand why this signal should be in the sensitivity-list!
It shouldn't.
Ignore or disarm the warning.
-- Mike Treseler
Article: 81024Many thanks. That was the answer I was hoping for. I did wonder if they placed something in the registry which may have prevented reinstallation and renewal. "Luc" <lb.edc@pandora.be> wrote in message news:maee3113jp74ggpr8ksas46od1rs20fqbf@4ax.com... > Hi, > > You can renew be downloading the latest version after 6 months. You > don't have to pay anything. > > Regards, > > Luc > > On Tue, 15 Mar 2005 17:05:33 -0000, "Fred" <Fred@nospam.com> wrote: > >>The freebie version has a 6 month temporary license. >> >>Can this be renewed indefinitely or must I pay money after the 6 months >>has >>expired? >> >
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