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Simple test for double-pulsing: Just feed the signal under investigation as a clock into a toggling fip-flop. You will see double-pulses easily, they look like missing triggers, since they double-trigger. Even a slow scope shows that... Peter AlfkeArticle: 82926
In article <d43ttt$a13@xco-news.xilinx.com>,
Kevin Neilson <kevin_neilson@removethiscomcast.net> wrote:
>Because of the deficiencies in Verilog or the tools, I often have to
>write Perl to generate Verilog. Examples of these deficiencies include:
>
>- Port list is not parameterizable without use of `defines
>- Many synthesizers don't understand preprocessing constant functions
>- Generate function in Verilog has limitations
>
>Rather than write Perl to generate Verilog modules, which is a
>cumbersome flow, it would be nice to have a Perl preprocessor. What I
>am thinking of is something that would look through your HDL, find
>formatted comments, parse parameters and `ifdefs, and then execute Perl
>and insert the results there. It would see something like this:
>.
>.
>.
>parameter NUM_UNITS=2;
>`define PARAM2 2
>// Perl Start
>// for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
>// print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
>// }
>// Perl End
>.
>.
>
>Then it would execute the Perl in the comments and append the output to
>the commented section, like this:
>.
>.
>.
>parameter NUM_UNITS=2;
>`define PARAM2 2
>// Perl Start
>// for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
>// print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
>// }
>// Perl End
>// Generated Perl Code Start
>adder adder0 (.I(i[0],.O(o[0]);
>adder adder1 (.I(i[1],.O(o[1]);
>adder adder2 (.I(i[2],.O(o[2]);
>adder adder3 (.I(i[3],.O(o[3]);.
>// Generated Perl Code End
>.
>.
>
>Of course this is a simple example that can be accomlished with a
>'generate', but you get my point. Note that the Verilog parameters have
>been parsed and can be used as Perl variables. With this preprocessor
>you could also do a lot of floating-point preprocessing that uses
>functions like "sine" that don't exist in Verilog. Does anything like
>this exist? Or do I have to write my own?
>-Kevin
I do this sort of thing with VHDL using Ruby (http://www.ruby-lang.org -
Perl's prettier younger sister, or Perl meets SmallTalk) and Ruby's
built-in ERB module which lets you embed Ruby code into a string, so you
can do things like this (I was just doing this today, in fact):
package mvg_avg_pkg is
constant integer_part : natural := <%= @bits %>;
constant frac_part : natural := <%= @bin_pt %>;
constant multiplier : unsigned := <%= @bits %>-1 downto 0) :=
"<%= @multiplier.to_binary %>";
end package;
The code between '<%=' and '%>' is valid Ruby code and gets evaluated as
such and the resulting values are filled in. You can also have loops,
etc.
Phil
Article: 82927Hi, When you open a 6.1 project in ISE 7.1, it asked if you want to convert, and it will make a back up for you. So now if you have the back up, how do you open the back up file in 6.1? Thanks, ALArticle: 82928
"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:d442ra$ap1$1@lnx107.hrz.tu-darmstadt.de... > > But I fear that nobody from the ISE programming department reads here > :-( > I know somewhere else they don't read... http://en.wikipedia.org/wiki/Regression_testing ;-) Cheers, Syms.Article: 82929
Eric Smith <eric@brouhaha.com> wrote: >"Andy Peters" <Bassman59a@yahoo.com> writes: >> I think you misunderstand my question, which is: what files are >> necessary and what files are cruft? > >Your Verilog and/or VHDL files, and your UCF files are necessary. Anything >else that you create yourself is necessary. All those things should be >checked into your repository. > >Everything that is generated by the tools should not be checked into >the repository. Assuming you can rely on the tools to regenerate exact copies of everything else which you can't after a patch or service pack or new version. You also need whatever holds the tool configuration and options, is that more than an npl file?Article: 82930
On 19 Apr 2005 03:24:51 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: >In article <in8861dlu0347p98ce9f9m5uetqaf0rrr5@4ax.com>, >John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >>On 18 Apr 2005 10:27:29 -0700, shuss3@yahoo.com wrote: >> >>>I just got my first job offer with a semiconductor company. I am yet to >>>sign the paperwork. I am hoping to get more offers in the forthcoming >>>month. I am wondering if the paperwork that I sign for this company can >>>be used against me if I turn down the position for a different one, say >>>in a month? Is the paperwork legal and binding? My start date is not >>>until July 1st. Thanks in advance for your inputs. >> >> >>Are you in the USA? Slavery is no longer legal here; nobody can force >>you to work at a job for one minute longer than you wish. >> >>If you want to be ethical, tell them you haven't made up your mind >>yet, and request a few more weeks to decide. If you don't care about >>that sort of thing, just fill in the forms and don't show up if you >>get a better deal. The only person who really cares about the ethics >>of your behavior is you. >> > >And the hiring manager that you will have stiffed. If s/he's still the >hiring manager in a few years when you approach him resume-in-hand s/he's >not goint go give you the time of day. > >Phil But the probability of that happening - applying to the same company, same group, same person - is essentially nil. JohnArticle: 82931
Hi Rudi, Rudolf Usselmann wrote: > XILINX, how about a BETA program ? I mean one before you burn > the CDs and make a product announcement and we are stuck with > a useless plastic disc. There is sort of such a thing, it's called the early access program. Contact Xilinx directly, then get ready for multi-gigabyte downloads in the months leading up to a tool release! I'm not sure though what channels are provided for early access members to feedback directly to the SW development teams - you certainly don't want to go through the hotline on that! > I'm sure a few of us with subscription would volunteer to test > drive a pre-release version of your s/w. - I know I would. I think there's a catch-22 here - people doing production designs are often (and understandably) reluctant to install a "beta" version of the tools, for fear it will break their current workflows. However, without having the beta tools tested on real designs, Xilinx won't get any feedback on things that are broken. A real beta test program is a lot more rigourous than a few volunteers offering to maybe try out the tools on some of their designs - because you aren't paying these people, you can't force them to actually do anything useful for you. Not sure what the solution is though... JohnArticle: 82932
Pocket Door wrote: > I am an electrical engineering student who has been tasked to create a > short game using WinCUPL. We are expected to set up a sequence of > states to run the game. > > While the program compiles in WinCUPL and has been debugged it somehow > has outputs which barely match the states at all. I do not understand > how there could be an output when the state does not indicate that > there should be one. I suspect that I am missing some detail in the > programming. One really big "detail" is that it ain't a program -- it's a hardware description. Programs are things written in computer languages to be reduced to machine code and executed _in sequence_ by a _processor_. Hardware descriptions are written in hardware description languages to be reduced to configurations of _logic_ on FPGAs or PGAs where they _exist_, and possibly contain registers that are clocked. If you want anything to "execute" in "sequence" you've got to invent that part. How are you (or your hardware synthesizer) representing the states? Are you using 1-hot encoding or some other method that can have illegal states if the registers aren't initialized properly? Are you initializing your registers? > > It seems that the teachers are as clueless as I am as to the nature of > the problem. If they told you it's programming perhaps. If they told you it's hardware descriptions and you missed that "detail" then perhaps you have a listening problem. > While I have working code from another student I cannot > understand the difference between his and mine. I would really like > to know how WinCUPL works. > > Could I get a good WinCUPL tutorial or instruction site, or some help > with debugging the code? I can post the lab and my code. Otherwise > I can be reached by AIM, screenname Pocket Door. > Usenet is a public service, not a place to solicit private tutoring. Post you code, by all means. I know next to squat about WinCUPL, but someone may help you out. -- Tim Wescott Wescott Design Services http://www.wescottdesign.comArticle: 82933
Maybe me thinks you should get another career. Sorry to be less than helpful. If you give your real name I am sure it can be forwarded to your adviser or just use google as usual. Others here will likely give you their hourly rates for assignment help! JJArticle: 82934
I am performing a huge simulation, netlist and SDF file size were each ~110MB. The first segment of my simulation were correct, then all of a sudden some of my signals became question marks. On the simvision, they appear to have been blank after certain time, and cursor value turned question mark. Is this caused by memory depletion or what? Thank you for your input.Article: 82935
On Tue, 19 Apr 2005 17:20:21 -0600, Kevin Neilson
<kevin_neilson@removethiscomcast.net> wrote:
>That part isn't too bad, but I think the difficult part is to be able to
>use the Verilog parameters in the Perl code. For that to work, I have
>to be able to parse through all the files to find the values of all the
>parameters in that scope.
>-Kevin
I run hot and cold on the idea of using pre-processors, so I won't
offer an opinion for fear of contradicting myself. But if you're
looking for a perl Verilog parser, take a look at:
http://www.burbleland.com/v2html/rvp.html
I don't know if it'll do what you need, but perhaps it will give you
some ideas.
Good luck,
Bob Perlman
Cambrian Design Works
>Symon wrote:
>> Kevin,
>> It'd be less than an hour to write a Perl pre-processor to run the inline
>> stuff. You know about Perl's 'eval' function I assume? Read the file in,
>> write it back out, execute the stuff between the //Perl Start End thingies.
>> Cheers, Syms.
>>
>> "Kevin Neilson" <kevin_neilson@removethiscomcast.net> wrote in message
>> news:d43ttt$a13@xco-news.xilinx.com...
>>
>>>Because of the deficiencies in Verilog or the tools, I often have to
>>>write Perl to generate Verilog. Examples of these deficiencies include:
>>>
>>>- Port list is not parameterizable without use of `defines
>>>- Many synthesizers don't understand preprocessing constant functions
>>>- Generate function in Verilog has limitations
>>>
>>>Rather than write Perl to generate Verilog modules, which is a
>>>cumbersome flow, it would be nice to have a Perl preprocessor. What I
>>>am thinking of is something that would look through your HDL, find
>>>formatted comments, parse parameters and `ifdefs, and then execute Perl
>>>and insert the results there. It would see something like this:
>>>.
>>>.
>>>.
>>>parameter NUM_UNITS=2;
>>>`define PARAM2 2
>>>// Perl Start
>>>// for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
>>>// print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
>>>// }
>>>// Perl End
>>>.
>>>.
>>>
>>>Then it would execute the Perl in the comments and append the output to
>>>the commented section, like this:
>>>.
>>>.
>>>.
>>>parameter NUM_UNITS=2;
>>>`define PARAM2 2
>>>// Perl Start
>>>// for ($j=0;$j<$NUM_UNITS*PARAM2;j++) {
>>>// print("adder adder$j (.I(i[$j],.O(o[$j]);\n");
>>>// }
>>>// Perl End
>>>// Generated Perl Code Start
>>>adder adder0 (.I(i[0],.O(o[0]);
>>>adder adder1 (.I(i[1],.O(o[1]);
>>>adder adder2 (.I(i[2],.O(o[2]);
>>>adder adder3 (.I(i[3],.O(o[3]);.
>>>// Generated Perl Code End
>>>.
>>>.
>>>
>>>Of course this is a simple example that can be accomlished with a
>>>'generate', but you get my point. Note that the Verilog parameters have
>>>been parsed and can be used as Perl variables. With this preprocessor
>>>you could also do a lot of floating-point preprocessing that uses
>>>functions like "sine" that don't exist in Verilog. Does anything like
>>>this exist? Or do I have to write my own?
>>>-Kevin
>>
>>
>>
Article: 82936"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:6v7b611c6jhrp534qicpjlm8f0sqfbllkl@4ax.com... > On 19 Apr 2005 03:24:51 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: > > >In article <in8861dlu0347p98ce9f9m5uetqaf0rrr5@4ax.com>, > >John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >>On 18 Apr 2005 10:27:29 -0700, shuss3@yahoo.com wrote: > >> > >>>I just got my first job offer with a semiconductor company. I am yet to > >>>sign the paperwork. I am hoping to get more offers in the forthcoming > >>>month. I am wondering if the paperwork that I sign for this company can > >>>be used against me if I turn down the position for a different one, say > >>>in a month? Is the paperwork legal and binding? My start date is not > >>>until July 1st. Thanks in advance for your inputs. > >> > >> > >>Are you in the USA? Slavery is no longer legal here; nobody can force > >>you to work at a job for one minute longer than you wish. > >> > >>If you want to be ethical, tell them you haven't made up your mind > >>yet, and request a few more weeks to decide. If you don't care about > >>that sort of thing, just fill in the forms and don't show up if you > >>get a better deal. The only person who really cares about the ethics > >>of your behavior is you. > >> > > > >And the hiring manager that you will have stiffed. If s/he's still the > >hiring manager in a few years when you approach him resume-in-hand s/he's > >not goint go give you the time of day. > > > >Phil > > But the probability of that happening - applying to the same company, > same group, same person - is essentially nil. > > John > So, your point is what? BobArticle: 82937
Pocket Door wrote: > I am an electrical engineering student who has been tasked to create a > short game using WinCUPL. We are expected to set up a sequence of > states to run the game. > > While the program compiles in WinCUPL and has been debugged it somehow > has outputs which barely match the states at all. That statement is contradictory. If it has been debugged, then it works. If it fails, then you have not yet finished debugging... Did you just mean it compiles without errors ? - that only means it is syntax checked - not debugged. > I do not understand > how there could be an output when the state does not indicate that > there should be one. I suspect that I am missing some detail in the > programming. Does your testing procedure include Hardware Vector testing on a device programmer ? Or is this the simulation vector output, from CUPL ? The most solid design path, if you can apply it, is to both SW simulate, and ALSO run test vectors on a device programmer. When ALL pass, you can be confident all test-covered functions are OK. And also well set up for both future revisions, and production programing. > > It seems that the teachers are as clueless as I am as to the nature of > the problem. > While I have working code from another student I cannot > understand the difference between his and mine. I would really like > to know how WinCUPL works. There is good potential here for learning. If you have one example that works, and your own, then compare the source files, and the CUPL .DOC files, and also the .SI and .SO files, It's a matter of 'spot the difference', and then trying changes, until either his breaks, or yours works, depending on which direction you decide to approach from. The CUPL output .DOC file shows what CUPL has built, and so shows 'how cupl works' - if you also go tru a fitter, look at that .FIT report file as well. > > Could I get a good WinCUPL tutorial or instruction site, or some help > with debugging the code? I can post the lab and my code. Otherwise > I can be reached by AIM, screenname Pocket Door. Example files are some of the best tutorials, and your teachers should have many working examples. -jgArticle: 82938
Hello, I have been working on a Virtex II Pro Development kit from Avnet. I tried running a custom compiled linux on the board and it didn't work. However, after this episode, the board is unable to start "avmon" either. The serial terminal displays the following two lines and stops. Loading program from flash address 0x94f80000 to RAM address 0x88080000 ... done. Jumping to 0x88080000... I was wondering if the flash got overwritten by any chance. Is there a way to reload the flash memory to its original contents? Thanks, SirishArticle: 82939
On Wed, 20 Apr 2005 02:31:28 GMT, "Bob" <nimby1_notspamm_@earthlink.net> wrote: > >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message >news:6v7b611c6jhrp534qicpjlm8f0sqfbllkl@4ax.com... >> On 19 Apr 2005 03:24:51 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: >> >> >In article <in8861dlu0347p98ce9f9m5uetqaf0rrr5@4ax.com>, >> >John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: >> >>On 18 Apr 2005 10:27:29 -0700, shuss3@yahoo.com wrote: >> >> >> >>>I just got my first job offer with a semiconductor company. I am yet to >> >>>sign the paperwork. I am hoping to get more offers in the forthcoming >> >>>month. I am wondering if the paperwork that I sign for this company can >> >>>be used against me if I turn down the position for a different one, say >> >>>in a month? Is the paperwork legal and binding? My start date is not >> >>>until July 1st. Thanks in advance for your inputs. >> >> >> >> >> >>Are you in the USA? Slavery is no longer legal here; nobody can force >> >>you to work at a job for one minute longer than you wish. >> >> >> >>If you want to be ethical, tell them you haven't made up your mind >> >>yet, and request a few more weeks to decide. If you don't care about >> >>that sort of thing, just fill in the forms and don't show up if you >> >>get a better deal. The only person who really cares about the ethics >> >>of your behavior is you. >> >> >> > >> >And the hiring manager that you will have stiffed. If s/he's still the >> >hiring manager in a few years when you approach him resume-in-hand s/he's >> >not goint go give you the time of day. >> > >> >Phil > > >> >> But the probability of that happening - applying to the same company, >> same group, same person - is essentially nil. >> >> John >> > > >So, your point is what? > I said it already: the person who most cares about your ethics is yourself. JohnArticle: 82940
Hi Williams, have you made a timing simulation of the placed and routed design? Maybe the write enable has a high delay for that one register, and doesn't meet timing requirements anymore. (Just a guess) Is your IP-core a softcore (only source) or a preplaced and wired hardmacro? have a nice synthesis Eilert williams schrieb: > Hello, > > I am integrating an IP core and i am facing a strange problem. > One of the register of the IP core which is R/W register is not > writable ..in simulation I am able to write but when ported to FPGA I > am not able to write…its default value is also wrong and when I write > to one fixed register in that core... its value gets reflects on that > register. Reset value of all the register is ok and I am able to read > and write all R/W registers except one. What may be the > problem…..since simulation results shows that the IP is ok…so I cannot > pin point that tell the IP vendor that there is a bug in ur IP….. > > Any feedback??? > Thanks and Regards > WilliamsArticle: 82941
Hello Antti,
Thank you for your reply. I had disclosed my identity in
the mail(regards, Kishore) . Please read the mail again.
Also I competely disagree with your assumption that I haven't done any
homework. After I had gone through a couple of pages collected through
I had some ambiguity in the differences between the two CPU's , So I
had asked the above question only to refine my web searching.
Pease be straight forward while giving any suggestions.
Regards,
Kishore
Article: 82942"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message news:bcnb61h5kmbrsf891p9uott7n53cua1ihd@4ax.com... > On Wed, 20 Apr 2005 02:31:28 GMT, "Bob" > <nimby1_notspamm_@earthlink.net> wrote: > > > > >"John Larkin" <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote in message > >news:6v7b611c6jhrp534qicpjlm8f0sqfbllkl@4ax.com... > >> On 19 Apr 2005 03:24:51 GMT, ptkwt@aracnet.com (Phil Tomson) wrote: > >> > >> >In article <in8861dlu0347p98ce9f9m5uetqaf0rrr5@4ax.com>, > >> >John Larkin <jjlarkin@highNOTlandTHIStechnologyPART.com> wrote: > >> >>On 18 Apr 2005 10:27:29 -0700, shuss3@yahoo.com wrote: > >> >> > >> >>>I just got my first job offer with a semiconductor company. I am yet to > >> >>>sign the paperwork. I am hoping to get more offers in the forthcoming > >> >>>month. I am wondering if the paperwork that I sign for this company can > >> >>>be used against me if I turn down the position for a different one, say > >> >>>in a month? Is the paperwork legal and binding? My start date is not > >> >>>until July 1st. Thanks in advance for your inputs. > >> >> > >> >> > >> >>Are you in the USA? Slavery is no longer legal here; nobody can force > >> >>you to work at a job for one minute longer than you wish. > >> >> > >> >>If you want to be ethical, tell them you haven't made up your mind > >> >>yet, and request a few more weeks to decide. If you don't care about > >> >>that sort of thing, just fill in the forms and don't show up if you > >> >>get a better deal. The only person who really cares about the ethics > >> >>of your behavior is you. > >> >> > >> > > >> >And the hiring manager that you will have stiffed. If s/he's still the > >> >hiring manager in a few years when you approach him resume-in-hand s/he's > >> >not goint go give you the time of day. > >> > > >> >Phil > > > > > >> > >> But the probability of that happening - applying to the same company, > >> same group, same person - is essentially nil. > >> > >> John > >> > > > > > >So, your point is what? > > > > I said it already: the person who most cares about your ethics is > yourself. > > John > Okay, but I'm not sure that's always true. It should be, though. I sense that the OP hasn't developed your or my level of ethics, yet. My ethics plus my memory would cause me to not hire him (if I were in that position) -- assuming he had chosen a deceitful route and I knew about it. I hope that he is reading these replies, and at least considers the potential ramifications of his actions. Regards, BobArticle: 82943
The 16MHz stands for an external data stream. I have no direct clock recovery of that data stream. The 125MHz comes from a PLL. The input clock of the PLL is not the source clock of the data stream. I will think about your suggestions. Thank you to all. Rgds AndréArticle: 82944
Well in the release notes for Synplify 8.0A (downloadable from the Actel website) it has the following: For the Actel ProAsic Plus family, the synthesis software now extracts single-port and dualport versions of the following RAM configurations: SA Synchronous write, asynchronous read SST Synchronous write, synchronous read, transparent output SSR Synchronous write, synchronous read, registered output For RAMS that are bigger than the basic block size of 256x9, the software infers them by cascading similar kinds of basic blocks. For wider RAMs, the software cascades basic blocks so that the same kinds of inputs are tied together. For deeper RAMs, the software cascades basic blocks and uses decoding logic. So it looks like it is now possible to infer the RAMs, but I haven't tried it yet, so am not sure how good it is, or what the HDL template required is.Article: 82945
nospam <nospam@nospam.invalid> writes: > Eric Smith <eric@brouhaha.com> wrote: >>Everything that is generated by the tools should not be checked into >>the repository. > > Assuming you can rely on the tools to regenerate exact copies of everything > else which you can't after a patch or service pack or new version. You I always install the tools and SP's in a fresh location. I always keep the previous releases. I work in a UNIX environment where this is easier, i.e. no shared registry where things gets messed up. > also need whatever holds the tool configuration and options, is that more > than an npl file? I do everything from the command line so the options are stored in the makefile. For my Altera flow all the options are given in the Tcl script. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 82946
Hi All, Been trying to find out the cost of Altera DSP Builder 3.0.0. Can't find any pricing info anywhere on web (also tried calling but after being shunted around gave up). V2.2 seems to have been $1995: http://www.altera.com/corporate/news_room/releases/releases_archive/2004/products/nr-dspbuilder.html Is this still the case for 3.0.0?Article: 82947
HI all,
While compiling my design in Quartus II 4.2 , I got following errors.
The piece of code is given below....
Error: VHDL error at Ctrl_Ram.Vhd(66): can't determine definition of
operator ""&"" -- found 2 possible definitions
Error: Verilog HDL or VHDL error at Ctrl_Ram.Vhd(66): Unconverted
VHDL-1402: ambiguous type: 'Regfile' or 'SIGNED'
Error: VHDL Type Conversion error at Ctrl_Ram.Vhd(66): can't determine
type of object or expression near text or symbol "UNSIGNED"
Error: Ignored construct Ctrl_Ram_Arch at Ctrl_Ram.Vhd(42) because of
previous errors
-- These subtypes are in a package....
subtype WORD is signed(15 downto 0);
subtype DWORD is unsigned(31 downto 0);
-- In the Architecture declaration part I am defining follwing
signals..
type Regfile is array (natural range<>) of WORD;
signal Regfile_Ctrl_High : Regfile(0 to 15); -- High Bank Registe File
signal Regfile_Ctrl_Low : Regfile(0 to 15); -- Low Bank Register File
signal data_out_high : WORD;
signal data_out_low : WORD;
-- And these are the concurrent statements in Architecture body...
-- Regfile Read Assignments
data_out_low <= Regfile_Ctrl_Low(TO_INTEGER(Addrs_In));
data_out_high <= Regfile_Ctrl_High(TO_INTEGER(Addrs_In));
-- Concatenation of Low and High to form 32 Control Word
Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN
THIS LINE...
Whats wrong with the last statment. I expect '&' operator to
concatenate the two signals. What could be the other meaning of '&'
operator. I think I am doing a silly mistake some where . Please help
me in resolving this..
Thanks.
-- Mohammed A Khader.
Article: 82948Hi People, I am interested to build AND gate (as neural network) using FPGA. I am using Xilinx webpack 7. If anyone can advice on how can I build one using basic components such as adder, multiplier.. lookup table etc... thanks in advance. JohnArticle: 82949
> > -- Concatenation of Low and High to form 32 Control Word > Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN > THIS LINE... > > -- just try Data32_Out <= unsigned(data_out_high) & unsigned(data_out_low); regards, laurent gauch www.amontec.com
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