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Messages from 84050

Article: 84050
Subject: Re: signals in modelsim
From: Brijesh <brijesh_xyz@cfrsi_xyz.com>
Date: Wed, 11 May 2005 14:54:21 -0400
Links: << >>  << T >>  << A >>
Benjamin Menküc wrote:
> Hi Brijesh,
> 
> Post-Translate Simulation works. However Behavioral Model simulation 
> still doesn't.
> 
>> 1) One does not instantiate a test bench. Test bench is a place holder 
>> for your enitity under test and logic required to test the entity.
>> "My testbench is instantiated as uut." did you mean that you have 
>> named your testbench as "uut"?
> 
> 
> my testbench is instantiated like this:
> ...
>     -- Instantiate the Unit Under Test (UUT)
>     uut: led_test PORT MAP(
> ...
> Under properties in the Project Navigator I have entered UUT as instance 
>  name. (it works for the other types of simulation).
> 
>>
>> 2) Did your test bench compile without any errors?
> 
> 
> since I have inserted a SRL16, it hangs now
> SRL16_inst : SRL16
>    generic map (
>       INIT => X"0000")
>    port map (
>       Q => dcm3_rst,       -- SRL data output
>       A0 => '1',     -- Select[0] input
>       A1 => '1',     -- Select[1] input
>       A2 => '0',     -- Select[2] input
>       A3 => '0',     -- Select[3] input
>       CLK => clk_ibufg,   -- Clock input
>       D => not lvds_locked        -- SRL data input
>    );    <-- in this line
> 
> the error message is
> # -- Compiling architecture behavioral of led_test
> # ** Error: led_test.vhd(475): The actual for formal 'd' is not a 
> globally static expression.

Modelsim is very picky, it does not what you did to the D input
 >       D => not lvds_locked        -- SRL data input

You inverted the signal during port mapping. It does not like that.

Try something like

lvds_locked_N <= not lvds_locked;

then use the lvds_locked_N in the port mapping.





> 
> regards,
> Benjamin

Article: 84051
Subject: Re: Virtex4 running at 360Mhz DDR
From: "Symon" <symon_brewer@hotmail.com>
Date: Wed, 11 May 2005 13:36:18 -0700
Links: << >>  << T >>  << A >>
"Austin Lesea" <austin@xilinx.com> wrote in message
news:d5teda$2vn1@cliff.xsj.xilinx.com...
> Symon,
>
> What is 12.5pF in series with 12.5pF?
>
> Yes, that is right, 6.25pF differential load, not 12.5pF.
>
> Falling for the A FUD is especially embarrassing when you just repeat
> things which are factually incorrect.
>
> All these things are taken into account from the simulation.
>
> Austin
>
OK, I'm not sure where that came from, but let me explain. Each pin of the
pair is driven by a 50 ohm line. Taken together, these two 50 ohm lines make
a 100 ohm differential pair. At one single pin you've got a 12.5pF capacitor
being driven from 50 ohms. If you view the pair together, you've got 6.25pF
driven by 100 ohms. The return loss is the same in both cases. As is the
rise time (RC = 625ps). So, Altera's 6.1pF per pin turns into 3.05pF when
viewed as the termination to a pair. In the 1Gbit region, their return loss
is much better. Their rise time is twice as fast. (RC=305ps).
Now, pay attention. I can make your c(r)appy LVDS work better. Given the
problem is that you've got a large Cpin because (I guess) of all the other
attached goodies, a way to improve things is to drive this capacitance with
a lower impedance. For an FPGA to FPGA connection, use a 50 Ohm differential
transmission line instead of 100 Ohms. If you place an extra external 100
Ohms differential termination resistor at _BOTH_ end of this t-line, you
have a pretty well matched 50 Ohm connection. The pole caused by the
parasitic capacitance has moved out to double the frequency it was at. Of
course, the signal amplitude has halved, which tends to make the eye close
vertically, but it will open horizontally, which is the limiting factor in
this case. Maybe LVDS_EXT would be a good idea too.
There are also other methods to open the eye for specific bitrates if the
t-line characteristics and parasitics of the parts are known. You need to
use an application specific filter at the end of the t-line.
HTH, Syms.



Article: 84052
Subject: Re: Slice Virtex II = Equivalent gates ??
From: "Peter Alfke" <peter@xilinx.com>
Date: 11 May 2005 13:42:42 -0700
Links: << >>  << T >>  << A >>
Give up, this is hopeless.
The structures are so different, there is no conversion factor.
Let me give you the extremes:

The 4-input LUT can be used as either an inverter or a 10-gate XOR
structure, or as a 64+-gate 16-bit RAM, or as a 100-gate sixteen bit
shift register.
The associated fancy flip-flop is worth 7+ gates.
And a slice is twice what I listed above, so it's anything from 2 gates
to 214 gates.
Is that enough leeway?
Some people use the geometric mean value of 14...
Peter Alfke, Xilinx Applications


Article: 84053
Subject: Re: Virtex4 running at 360Mhz DDR
From: Austin Lesea <austin@xilinx.com>
Date: Wed, 11 May 2005 14:12:36 -0700
Links: << >>  << T >>  << A >>
Symon,

All true.

I would suggest that you should have more of a differential line, than 
two single ended 50 ohm lines, but it doesn't change anything at all 
(you still end up being differentially terminated at the receiver, with 
6.25pF across 100 ohms).

The eye is plenty good for up to 1 Gbs (see the ML450).

It does not work up to 1.3 Gbs, because we didn't design it to work up 
to there:  that is what the MGTs are for.

If there is a 'beauty contest' for the 'best LVDS eye pattern', I will 
admit we come in second (due to increased Cpin), but I will not admit 
that it matters so far as use, function, or anything important is 
concerned.  The Idly feature that allows for independent skew adjustment 
for each IO pin (pair) to center the eye sampling point to within 
+/-78ps is a far more useful feature than having 'pretty eyes'.

Austin

Article: 84054
Subject: Re: Using capacitor to slow the rise time.
From: Jeremy Stringer <jeremy@_NO_MORE_SPAM_endace.com>
Date: Thu, 12 May 2005 10:07:56 +1200
Links: << >>  << T >>  << A >>
Philip Freidin wrote:
>Bob Perlman wrote:
>1) Do you use capacitors on digital lines?
>2) Do you use analog one-shots in your designs?
> 
>Ray Andraka wrote:
>3) Do you connect logic outputs to clock inputs (or do you use gated
>  clocks)?
> 
>Symon Brewer wrote:
>4) Have you had any bugs that 'fixed themselves' without you knowing 
>  why? (They always come back!)
>5) Any unterminated digital lines going off board and/or longer than 
>  c.15cm?
> 
>Philip Freidin wrote:
>6) Do you have any pet theories on how to fix metastables?
>
>7) Do you use the async set and reset pins on FFs for other than
>  system initialization?
>
>Thomas Rudloff wrote:
>8) Do you use pull up resistors on fast CMOS busses that require less 
>  than 10ns/V rise / fall time?
>
>Jeff Cunningham wrote:
>9) Do you ever knowingly violate worst case timing specs?
>
>
>Philip Freidin wrote (again):
>10) Do you only use time specs for the "important" parts of your design?
>
 >Jeremy Stringer wrote (again):
 >11) Do you ever use LUTs as delay elements to change interface timings?

Article: 84055
Subject: Re: RS 232 receiver using spartan 3 board
From: "info_" <"info_"@\\nospam_no_underscore_alse-fr.com>
Date: Thu, 12 May 2005 00:17:57 +0200
Links: << >>  << T >>  << A >>
teodor wrote:
> Hi, I have a virtex4 development kit (ML403) and I plan to communicate with a PC via rs232. I see that you have done some work in the field and I just wanted to know if you have made any progress and if you could give me any hints where to start.
> 
> Thanks
> 
> ///Teodor

You should have SOC apps coming with the board running
already with a UART.

But if you don't want the processor and embedded stuffs,
it's very easy : with our UART IP, you would have a test
setup working within minutes.
It's free only for educational & hobby use (and cheap otherwise).
One user did run it at 921k bauds ! (bypassing the level translators)

For the keyboard, it's even easier: the IP is on our Web and free.
(the bi-directional PS/2 is normally not free).

http://www.alse-fr.com/English/tech_corner.html

Bert Cuzeau

Article: 84056
Subject: Re: Slice Virtex II = Equivalent gates ??
From: "info_" <"info_"@\\nospam_no_underscore_alse-fr.com>
Date: Thu, 12 May 2005 00:24:10 +0200
Links: << >>  << T >>  << A >>
Peter Alfke wrote:

> Give up, this is hopeless.
> The structures are so different, there is no conversion factor.

Too bad some marketing guys didn't give up this way of counting
earlier ;-)

Article: 84057
Subject: Re: 8051 IP core
From: "info_" <"info_"@\\nospam_no_underscore_alse-fr.com>
Date: Thu, 12 May 2005 00:29:15 +0200
Links: << >>  << T >>  << A >>
CODE_IS_BAD wrote:

> hi all...
>   i would like to know wether anyone of you has used Oregano's free
> 8051 IP core. Also i read somewhere that this core cannot be
> synthesized on the xilinx or Quartus software. Is it true? Please let
> me know. 
> Thanx in advance
> 

Funny nobody mentioned Nexar : the 8051 core comes with the
package, + development & debugging tools.
Other cores provided are 16c5x, Z80, a small RISC ... otomh
It's quite easy to set up and use in an FPGA context indeed.

Bert Cuzeau

Article: 84058
Subject: Re: FPGA/Embedded Design Training
From: "Eric" <ericjohnholland@hotmail.com>
Date: 11 May 2005 15:32:24 -0700
Links: << >>  << T >>  << A >>
I'm kind of in the same boat... I do way more paper work and less
design work than I would like at my job.

So I bought a Zilog Z8 board and I do projects at home.

I also bought a Xilinx Spartan III board for $150 and play with that at
home too.

It is better than watching TV.

Nothing beats "hands on" experience.

A lot of time Distributors like Avnet, Arrow, and Future give away free
dev kits if you ask.... This is how I got one of my FPGA boards.

Plus by working on stuff your training yourself... your employer might
value  that and even purchase boards for you... My employer does!

Good Luck
Eric


Article: 84059
Subject: Re: crazy behaviour of fpga, timing ?
From: "info_" <"info_"@\\nospam_no_underscore_alse-fr.com>
Date: Thu, 12 May 2005 01:12:07 +0200
Links: << >>  << T >>  << A >>
ALuPin@web.de wrote:

> Which constraint type does fulfill these delay requirements
> in the input pins? I mean : Under which name do I have to search
> in the Constraint Manager ?

I/O Tsu & Th

By definition :
  tsu = data delay - clock delay + intrinsic tsu
  th = clock delay - data delay + intrinsic th

PS : in the ps range, you probably should also take into account
the PCB delays.
60 MHz isn't a too high freq, so it should be quite doable if there
is a minimal skew between all the (synchronous) signals.

There is a way I don't dare to mention since everyone will (at best)
frown at it : you can synchronize at one clock edge or the other
and just try : one solution at least should give a 0 error rate,
and hopefully the other should exhibit "some" errors, in which case
you have found a decent solution. If both work... you'll need
to do things more seriously.
Very dirty but it worked once well for me (with the context of not
very high clock freqs and in the absence of better characterization).
I didn't tell you and I won't sign this post :-)

The clean & official way is better, but again you need reliable
timing information on the data producer and all the delay elements.
Keep also in mind that "worst case timing" is not necessarily your
worst case... And I always found that a good scope was of great help.


Regards,
Treb

Article: 84060
Subject: Minimum circuit to get Spartan-3 running
From: "jgknowla1" <nospam@phyro.com>
Date: 11 May 2005 16:22:01 -0700
Links: << >>  << T >>  << A >>
Greetings,

I have one of the Digilent spartan-3 starter boards, and have been
browsing this newsgroup for a while.  I think I may be ready to design
a small board of my own.  I can't seem to find a minimum circuit to get
the chip running.  I'm thinking really simple here...no external RAM,
etc.  Just a JTAG interface, clock, and reasonable power/ground methods
(decoupling, etc).

Has anyone seen something like this before?

thanks,
the newcomer


Article: 84061
Subject: Re: FPGA/Embedded Design Training
From: "Kryten" <kryten_droid_obfusticator@ntlworld.com>
Date: Wed, 11 May 2005 23:39:17 GMT
Links: << >>  << T >>  << A >>
<kevin@firebolt.com> wrote in message 
news:1115812871.098504.265820@z14g2000cwz.googlegroups.com...
> Heyas,
>
> I've recently graduated college (< 2 years) and in that time have taken
> up a job which does not do nearly as much embedded design as I would
> like.  Does anyone have any ideas how I can keep up my skills and
> continue to learn while I'm in the position that I'm in?  There are
> always college courses, but not that many that are specific enough.
> Also, being such an "in-experienced" engineer (according to all the
> hiring managers out there), the current employer isn't about to spend
> thousands sending me around the country to training conferences.

Hi Kevin.

I know the feeling, even many years into my career.

Don't take hiring manager's comments too personally.
It's their job to get the best deal so they're always going to come up with 
some reason for making your position weak. If you're young, they'll argue 
you are too young and inexperienced and if you are older they'll argue you 
are too old, expensive and set in your ways. If I hear those arguments I ask 
them what is their perfect narrow age range and why did they not put that in 
the job spec. I ask how much they want to pay, and that if they're paying 
they dictate how things get done. It gets over the message that I've heard 
these arguments and let's get on to the real business of whether I can do 
the job.

I try to ask "what would I want to see if I were an employer?".

Well, I'd like to see a candidate who took matters into their own hands and 
showed initiative.
For example, venting the desire to do embedded work by doing some impressive 
projects from their own minds and pockets.

I know one guy who has a degree in electronics and laughs (nervously) has 
never touched a soldering iron. not so much as making a crystal set.
I said is it any mystery why nobody ever gave him an electronics job?
I would not. Would he? Would you?

So you can see why employers value experience over paper.

I'd want to see someone who dug into his own pocket, bought some dev kits 
and taught himself how to use the things and made something cool with them. 
It shows initiative, and that you don't wait forever for someone else to do 
things for you.

In employment, people will present you with problems and ask you to find 
solutions.

You've got the problem of finding a better job, and made a good first move 
asking around.
A next step might be to ponder what would be a really good project to show 
just what a cool kick-ass creative guy you are.

No self-driven project will guarantee you a job but they will put you steps 
ahead of doing nothing.

How about inventing some gadget to help the disabled?
That would shows some nobility of spirit which I would find admirable.
And it would help disabled people who might not be able to afford engineers 
at commercial rates.

How about a pulsejet powered wheelchair?

http://www.aardvark.co.nz/pjet/

"Timmmmmyyyyyy!!!!!"




Article: 84062
Subject: Re: Slice Virtex II = Equivalent gates ??
From: "Marc Randolph" <mrand@my-deja.com>
Date: 11 May 2005 17:02:08 -0700
Links: << >>  << T >>  << A >>
info_ wrote:
> Peter Alfke wrote:
>
> > Give up, this is hopeless.
> > The structures are so different, there is no conversion factor.
>
> Too bad some marketing guys didn't give up this way of counting
> earlier ;-)

Howdy,

If I had to make a WAG, the marketing department would claim that it
isn't their fault: "the customer asked for it!"  But the marketing guy
that says this doesn't realize that the proper answer isn't a number -
it's an explaination as to why any number they provide won't be
accurate.  Then the customer says "but the other FPGA vendor gave me a
number - why can't you?"

Customers are such a pain.  :-)

Have fun,  

   Marc


Article: 84063
Subject: re:Uart16550 can't receive data over 16byte a time
From: bigboytemp@hotmail-dot-com.no-spam.invalid (Big Boy)
Date: Wed, 11 May 2005 19:16:25 -0500
Links: << >>  << T >>  << A >>
Normally, you have to configure the 16550 to generate an interrupt
when the buffer get to a certain level.  I think you have 4 levels
you can set.  For example, if you set an interrupt to occur after the
fifo is half-full, this meen that after receiving 8 bytes, you'll get
an interrupt.  Then you have a margin of 8 bytes to clear the fifo. 
Note that if you receive for example only 4 bytes, then, after a
timeout, an interrupt will be generated so you don't have to worry
about data staying lattent in the buffer.

The lower you set the threshold, the more interrupts you'll have.  The
higher you set it, less interrupt will occur, so your code will be
interrupted less often, however, if your interrupt service routine is
too slow, the FIFO may get full.  So, the level at which you trigger
an interrupt must be set depending on your application.  I think that
be default the 16550 won't generate interrupt.  You have to configure
it, and also configure at which fifo level it will generate
interrupt.  This is because it will start in compatibility mode with
it's ancestor, the 8250, which could generate an interrupt, but only
after receiving a single byte (had no FIFO).  Though not 100% sure.

You can always implement a software fifo which is larger than 16
bytes.  Then, the interrupt service routine simply fill the fifo,
while your main code can poll the fifo less often.  Just make sure
that your code and interrupt routine do handle the fifo correctly so
they don't mutually interfere.


Article: 84064
Subject: Re: Virtex4 running at 360Mhz DDR
From: "Brian Davis" <brimdavis@aol.com>
Date: 11 May 2005 18:41:29 -0700
Links: << >>  << T >>  << A >>
Symon wrote:
>
>Taken together, these two 50 ohm lines make a 100 ohm
>differential pair. At one single pin you've got a
>12.5pF capacitor being driven from 50 ohms. If you view
>the pair together, you've got 6.25pF driven by 100 ohms.
>The return loss is the same in both cases. As is the rise
>time (RC = 625ps). So, Altera's 6.1pF per pin turns into
>3.05pF when viewed as the termination to a pair.
>
nice explanation...

Best wishes on getting Austin to stop with his
"but it's really half, differentially" handwaving.

I've tried before, with results similar to that
"but it goes to Eleven" bit from "Spinal Tap".

>
>a way to improve things is to drive this capacitance
>with a lower impedance
>

 Also, when you've got plenty of drive margin, a differential
attenuator ahead of the FPGA (with internal termination) works
nicely to attenuate the reflection, and also makes for a convenient
differential probe point.  If you have 6dB to spare, even the most
horrible of loads presents at least 12dB return loss, with the probe
seeing 1/4 the reflection voltage of the original circuit.(however, the
attenuator doesn't lower the drive impedance as does your suggestion )

Brian


Article: 84065
Subject: Looking for Rapid prototyping system, ?Quickturn ASIC-Emulator?
From: "Ken" <cckenneth@gmail.com>
Date: 11 May 2005 18:43:50 -0700
Links: << >>  << T >>  << A >>
Hello all,
  I am responsable to purchase and set up a electonics prototyping
system for my university. The price is not a issue but the major
concern is that the system should be easy to set up. (preferably a
one-whole unit or a few modules)
  I have done some search in the web, it seems the 'Quickturn
ASIC-Emulator' meets my requirement. However, it seems that it is not
selling any more.
  I have a few questions.
1. Do you think the 'Quickturn ASIC-Emulator' is a good machine for
rapid prototyping?
2. Is there other system which is simular to 'Quickturn ASIC-Emulator'?

  Thank you very much in advance.

Regards,
Kenneth


Article: 84066
Subject: Counting Clocks
From: "Weddick" <weddick@comcast.net>
Date: Wed, 11 May 2005 19:15:40 -0700
Links: << >>  << T >>  << A >>
I have what I thought was a simple problem.  I need to count the number of 
clocks to determine when to take data out of the shift register.  The data 
is a continuous stream and I want to be able to count every 8 bits.  I 
thought I could use a 3 bit counter but can't seem to get the code correct. 
I then went to a 4 bit counter, and while it works I am not sure if the code 
is the best way. Any ideas?

Thanks,
Joel






Article: 84067
Subject: How to use XMD debugger
From: Lina <lnzhao@emails.bjut.edu.cn>
Date: Wed, 11 May 2005 19:38:39 -0700
Links: << >>  << T >>  << A >>
Hi all,

I am using Virtex-II Pro50 to do some experiments. I would like to use XMD to debug, but I couldn't set the break point where I would like to set. There only are some fixed places given by the system to stop for the programme. who knows how to set the break points at any places I would like to? Thank you very much for all your help!

Article: 84068
Subject: Re: Virtex4 running at 360Mhz DDR
From: "Brian Davis" <brimdavis@aol.com>
Date: 11 May 2005 20:28:25 -0700
Links: << >>  << T >>  << A >>
Austin,
>
>Lots of scope shots are available (ask your FAE).
>
Then why not publish them, along with a comparison of IBIS/HSPICE
simulations versus the real world measurements?

>
>But, I am sure our Marketing Folks will be rolling our scope shots
>as part of pitch-packs, etc. for those who are unable or unwilling
>to do the SI engineering that their job requires of them.
>

Let's see if I've got this straight [1]:

A) Xilinx publicly posts in FPGA and SI forums touting their
   real world X vs. A package testing, and asks for feedback [2]

B) Forum users post some suggested measurements, which a
   certain Xilinx employee says they can make

C) Two months later, when asked when said measurements might
   be published, the very same Xilinx employee cops an attitude

>
>Get the ML450 board, or ask for the documentation.
>

 That would be the same manual (UG077 v1.2) that mentions a
HyperTransport compliant DUT interface connector, without
pointing out that the the specified V4 FPGA Cin is 5x the
allowed HyperTransport max Cin for a 1 Gbps part ???

 As to why that matters: a HyperTransport test probe attempting
to monitor the input link to the FPGA can't function properly
because Cin reflections off the FPGA would prevent the probe from
properly clocking the data at the mid T-line probe sampling point.

 There are ways around this, but life would be easier if Xilinx
actually bothered to meet the spec in the first place.

  Lacking that, proper documentation of your part's shortcomings,
and how and when to work around them, would be appropriate.


Brian


[1] Speaking of those unable to perform the SI engineering that is
required of them : when might we expect publication of characterized
static DCI power and DCI impedance modulation limits for the five year
old Virtex2 FPGA family ?

[2]
http://groups-beta.google.com/group/comp.arch.fpga/msg/d1004ae1fdca9825?hl=en


Article: 84069
Subject: Tutorial on debug of packet processing in FPGA hardware using Identify
From: "John W. Lockwood" <lockwood@arl.wustl.edu>
Date: Wed, 11 May 2005 23:29:09 -0500
Links: << >>  << T >>  << A >>

For those of us that build packet processing circuits in
FPGA hardware, finding bugs in circuits is difficult.

In the research and graduate courses at WashU, we have been
using Synplicity's Identify tool to locate bugs in packet processing
hardware.   Based on our good experiences on this topic, I posted
a tutorial from my class.  The slides describe our network platform
and show the methodology of how we debug of network hardware.

If you are teaching a debugging networking circuits or teaching a course
on the topic, you might find the material below useful.   I included both
the PowerPoint and Adobe Acrobat versions of a presentation that I
present in my courses.

Development of a System-On-Chip Extensible Network Processor and debugging 
using Identify,
    Acrobat format: 
http://www.arl.wustl.edu/projects/fpx/references/WashU_Identify.pdf
    or PowerPoint format: 
http://www.arl.wustl.edu/projects/fpx/references/WashU_Identify.ppt


 John Lockwood
   Reconfigurable Network Group
     http://www.arl.wustl.edu/projects/fpx/reconfig.htm




Article: 84070
Subject: Re: How to use XMD debugger
From: Paul Hartke <phartke@Stanford.EDU>
Date: Wed, 11 May 2005 22:14:17 -0700
Links: << >>  << T >>  << A >>
Chapter 15, Xilinx Microprocessor Debugger (XMD) of the Embedded System
Tools Reference Manual has a bunch of useful info:
http://www.xilinx.com/ise/embedded/est_rm.pdf

Lina wrote:
> 
> Hi all,
> 
> I am using Virtex-II Pro50 to do some experiments. I would like to use XMD to debug, but I couldn't set the break point where I would like to set. There only are some fixed places given by the system to stop for the programme. who knows how to set the break points at any places I would like to? Thank you very much for all your help!

Article: 84071
Subject: Re: DDR speed of the XUPV2P Board from Digilent
From: John Williams <jwilliams@itee.uq.edu.au>
Date: Thu, 12 May 2005 15:18:37 +1000
Links: << >>  << T >>  << A >>
Simon Peacock wrote:
> For that you need to check the DRAM manufacturer...  sometimes its not the
> clock thats so important.. but the time delays.. so at 200MHz you might find
> it 5-5-5 but 3-3-3 at 133MHz

While we're on the subject - does anybody know of an EDK reference 
design for the XUP2VP, particularly one exercising the DDR slot?  I 
looked on the Digilent website but didn't see anything, nor on the 
xilinx.com page dedicated to the board.

Thanks,

John

Article: 84072
Subject: Re: 8051 IP core
From: "CODE_IS_BAD" <Puneetsingh81@gmail.com>
Date: 11 May 2005 22:24:31 -0700
Links: << >>  << T >>  << A >>
Hi all...
  thanx for the answers.... what i am looking for is a free IP core....
And if i see the oregano's core it does not provide for SFR address and
data bus.... Is there any free IP core that provides that and if not
then some tips on how to modify the core to add SFR  busses ??? thanx
in advance........


Article: 84073
Subject: EDK 7.1 XMD and platform USB cable
From: "Antti Lukats" <antti@openchip.org>
Date: Thu, 12 May 2005 08:19:52 +0200
Links: << >>  << T >>  << A >>
Hi

does anyone have had full success using the xilinx platform USB Cable and
XMD in EKD 7.1?
I was trying to check out the 'star wars' movie demo supplied by avnet with
their uClinux Virtex4 reference design, but unfortunatly my new PC has no
printer port so I am bound to use the latest and best ?? USB JTAG cable from
Xilinx.

and unfortunatly XMD 7.1 doesnt seem to like the cable :( at first I assumed
this being a problem related to Virtex 4, but now checking with Virtex2Pro,
same problem... XMD just doesnt seem to handle usb cable.

is there some trick or fix? and yes I have all the latest service packs
installed!

Antti

http://www.sipsik.net



Article: 84074
Subject: Re: Xilinx versus Elixent; other radically different concepts?
From: jsavard@excxn.aNOSPAMb.cdn.invalid (John Savard)
Date: Thu, 12 May 2005 06:36:07 GMT
Links: << >>  << T >>  << A >>
On 11 May 2005 06:01:41 -0700, "Gabor" <gabor@alacron.com> wrote, in
part:

>Check out Mathstar.  They have a fabric of ALU's MAC's and register
>files that runs at 1 GHz.  The current chips don't include a micro
>but I understand they plan to add that in future revisions.

Thank you; I did check out the site, and it looks interesting.

John Savard
http://www.quadibloc.com/index.html
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