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A partial help is that some of the newer Xilinx families will support input LVDS/ LVPECL on Vccio = 3.3V. Spartan-3 does, V2-Pro does but I am not sure on V4 but probably yes. The general line on outputs is that these need 2.5V but it might be worth investigating what the limitation is. Here is a useful supporting link http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=18095 . Another way to tackle this is to run the FPGA with a Vccio = 2.5V and keep the signal swing from your 3.3V devices under the protection diode conduction point of the FPGA I/O i.e. about 3.1V (Vccio = 2.5V exactly). You may be able to run your 3.3V logic at 3.0V to keep the swings in this range or use bus switches to limit swing. Timing penalty is about 250 pS maximum for the bus switches. We do this for 5V/3.3V PCI interfacing in our Broaddown2 and MINI-CAN products and the solution is not necessarily large or costly. There are three 20 bit bus switches on both these products and you can see them on the board pictures on our website next to the PCI edge connector. John Adair Enterpoint Ltd. - Home of Broaddown2 and MINI-CAN FPGA Development Boards. http://www.enterpoint.co.uk "Quiet Desperation" <nospam@nospam.com> wrote in message news:100520051719304493%nospam@nospam.com... > Not another how-to question. I got app notes and opinions coming out my > ears already. > > I was just wondering if it was impossible to have maintained the 3.3V > LVDS and LVPECL stuff for another couple of generations. The 3.3V > LVPECL is still pretty much widely used. On Semi, for example, is only > now getting some of 2.5V stuff out there. Some only say 2.5V online and > there's no mention of it in the data sheet when you download it. > > My problem is trying to design new plug-in cards to existing units with > 3.3V LVPECL. I'd like to use Virtex4 chixps because they are far > cheaper right now than the Virtex-2 chips. For eample, Avnet quotes $3K > on the LX100 and $9K on the 2V8000! > > I've also got situations where the data rates are such that I'm Real > Unhappy putting a resistor network into the path, especially since I > have a connector already involved in the impedance discontinuity > landscape. > > So I was just wondering: is my current grief for a greater good? ;-)Article: 84001
Hi gang, Future electronics is offering Altera Cyclone/Nios-II Evaluation Kit for $49. What do other have to say about this deal. http://www.futureelectronics.comArticle: 84002
Hi, I am looking for a Virtex 4 based FPGA development board with ideally a PCI Express interface and at least a FX-100 Virtex 4. If anybody knows of any vendors who have this or are working on this, please let me know. Thanks, Sam.Article: 84003
There are no V4 FX with MGTs shipping yet, hence there are no boards available yet. Antti PS There will be an s3+PX1011A (PCIe PHY) evalkit available from Avnet soon, but that uses external PHY <asoc35@dsl.pipex.com> schrieb im Newsbeitrag news:1115804594.476359.55650@g14g2000cwa.googlegroups.com... > Hi, > > I am looking for a Virtex 4 based FPGA development board with ideally a > PCI Express interface and at least a FX-100 Virtex 4. If anybody knows > of any vendors who have this or are working on this, please let me > know. > > Thanks, > > Sam. >Article: 84004
I would prefer Avnet's Spartan 3E board for $69 :) Antti "Neo" <zingafriend@yahoo.com> schrieb im Newsbeitrag news:1115803812.614568.125000@g47g2000cwa.googlegroups.com... > Hi gang, > Future electronics is offering Altera Cyclone/Nios-II Evaluation Kit > for $49. What do other have to say about this deal. > http://www.futureelectronics.com >Article: 84005
Broaddown4 on the way but it is very early in the development I would not like to give a timescale as yet for production boards. Contact me offline on our support or sales emails, available on our website, if your application can wait a while or if one of our other solutions might fill your gap. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk <asoc35@dsl.pipex.com> wrote in message news:1115804594.476359.55650@g14g2000cwa.googlegroups.com... > Hi, > > I am looking for a Virtex 4 based FPGA development board with ideally a > PCI Express interface and at least a FX-100 Virtex 4. If anybody knows > of any vendors who have this or are working on this, please let me > know. > > Thanks, > > Sam. >Article: 84006
Hi, I get the following error, I am not sure how to fix that. I have tried increasing the memory size, but that doesnt help. mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .sdata2) mb-ld: region ilmb_cntlr is full (TestApp/executable.elf section .sdata2) mb-ld: section .data [00000000 -> 0000005f] overlaps section .text [00000000 -> 0000109f] make: *** [TestApp/executable.elf] Error 1 Any suggestions? CheersArticle: 84007
Hi , I have a Virtex II Pro FPGA Board and I have a verilog HDL code, I synthesized and generated bit stream to configure the FPGA. Now unable to solve the following questions. how can I test that code on the board ? I mean how to find verify its functionality . how can I drive the input data to the code? how can I observe the outputs for the given inputs? Please help me in this regard. Regards, KishoreArticle: 84008
I 'm not able to find this board on futureelectronics website, do you have a product reference or so? "Neo" <zingafriend@yahoo.com> schrieb im Newsbeitrag news:1115803812.614568.125000@g47g2000cwa.googlegroups.com... > Hi gang, > Future electronics is offering Altera Cyclone/Nios-II Evaluation Kit > for $49. What do other have to say about this deal. > http://www.futureelectronics.com >Article: 84009
Its listed alright, its on the right side of the page.Article: 84010
thanks, I've forgotten my eyes in my bed this morning! "Neo" <zingafriend@yahoo.com> schrieb im Newsbeitrag news:1115811770.024199.285150@o13g2000cwo.googlegroups.com... > Its listed alright, its on the right side of the page. >Article: 84011
Heyas, I've recently graduated college (< 2 years) and in that time have taken up a job which does not do nearly as much embedded design as I would like. Does anyone have any ideas how I can keep up my skills and continue to learn while I'm in the possition that I'm in? There are always college courses, but not that many that are specific enough. Also, being such an "in-experienced" engineer (according to all the hiring managers out there), the current employer isn't about to spend thousands sending me around the country to training conferences. Thanks, KevinArticle: 84012
Hi, I would prefer a board with external RAM (DDR or SRAM). For the very first step this board might be enough, but not for the second step :) regards, BenjaminArticle: 84013
John, Check out Mathstar. They have a fabric of ALU's MAC's and register files that runs at 1 GHz. The current chips don't include a micro but I understand they plan to add that in future revisions. John Savard wrote: > A while back, searching for technologies more adapted to creating a > microprocessor with a customized instruction set, I came across the web > site for Elixent. They have a chip which contains a microprocessor, plus > a fabric, something like an FPGA, but in which the cells are not simple > gates or look-up tables, but instead ALUs. Also, NEC and other companies > have 'reconfigurable computing' chips with many small computers of a > sort. > > Are there other kinds of software-customizable chips out there that are > very different from an FPGA? > > John Savard > http://www.quadibloc.com/index.html > _________________________________________ > Usenet Zone Free Binaries Usenet Server > More than 120,000 groups > Unlimited download > http://www.usenetzone.com to open accountArticle: 84014
jeycrisis wrote:
>Thank you again, I thing I will try this option...
>Do I have to change something on MO, M1, M2, because on the board I am
>using there is no way to access these pins.
>
>
>
yes you have to pull them low/high according with the datasheet (most of
the boards they have jumpers)
Aurash
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 84015Aurelian Lazarut wrote: > jeycrisis wrote: > >> Thank you again, I thing I will try this option... >> Do I have to change something on MO, M1, M2, because on the board I am >> using there is no way to access these pins. >> >> >> > yes you have to pull them low/high according with the datasheet (most of > the boards they have jumpers) > Aurash > Must be verified, but almost all parts have internal pull-up on M0 M1 M2 ! Just a jumper (or pull-down popullated or not) is required . Larry, www.amontec.comArticle: 84016
Hi Everyone, I tried to run the processor as well as the OCM with 100/100, 300/100, 300/300 as well as 300/150 MHz combinations. But the last ones are not working at all. For the 300/300 as well as the 300/150 designs, I have also given C_DSCNTLVALUE as well as C_ISCNTLVALUE the values 0x81 and 0x83 respectively. But I am not getting any outputs. The algorithm is infact floating point intensive and the only thing I am trying to do other than these calculations is that I am trying to display some intermediate results through the OPB UartLite. Do you have any suggestions. I am attaching the mhs file of the 300/150 design below. Joe # ############################################################################ ## # Created by Base System Builder Wizard for Xilinx EDK 6.3 Build EDK_Gmm.10 # Wed May 11 10:28:47 2005 # Target Board: Memec Design Virtex-II Pro P7-ff672 Development Board Rev 3 # Family: virtex2p # Device: XC2VP7 # Package: FF672 # Speed Grade: -6 # Processor: PPC 405 # Processor clock frequency: 300.000000 MHz # Bus clock frequency: 100.000000 MHz # Debug interface: FPGA JTAG # On Chip Memory : 40 KB # ############################################################################ ## PARAMETER VERSION = 2.1.0 PORT fpga_0_RS232_RX_pin = fpga_0_RS232_RX, DIR = INPUT PORT fpga_0_RS232_TX_pin = fpga_0_RS232_TX, DIR = OUTPUT PORT fpga_0_RS232_req_to_send_pin = net_gnd, DIR = OUTPUT PORT sys_clk_pin = dcm_clk_s, DIR = INPUT, SIGIS = CLK PORT sys_rst_pin = sys_rst_s, DIR = INPUT BEGIN ppc405 PARAMETER INSTANCE = ppc405_0 PARAMETER HW_VER = 2.00.c BUS_INTERFACE JTAGPPC = jtagppc_0_0 BUS_INTERFACE ISOCM = iocm BUS_INTERFACE DSOCM = docm BUS_INTERFACE IPLB = plb BUS_INTERFACE DPLB = plb PORT PLBCLK = sys_clk_s PORT C405RSTCHIPRESETREQ = C405RSTCHIPRESETREQ PORT C405RSTCORERESETREQ = C405RSTCORERESETREQ PORT C405RSTSYSRESETREQ = C405RSTSYSRESETREQ PORT RSTC405RESETCHIP = RSTC405RESETCHIP PORT RSTC405RESETCORE = RSTC405RESETCORE PORT RSTC405RESETSYS = RSTC405RESETSYS PORT BRAMISOCMCLK = ocm_clk_s PORT BRAMDSOCMCLK = ocm_clk_s PORT CPMC405CLOCK = proc_clk_s END BEGIN jtagppc_cntlr PARAMETER INSTANCE = jtagppc_0 PARAMETER HW_VER = 2.00.a BUS_INTERFACE JTAGPPC0 = jtagppc_0_0 END BEGIN proc_sys_reset PARAMETER INSTANCE = reset_block PARAMETER HW_VER = 1.00.a PARAMETER C_EXT_RESET_HIGH = 0 PORT Ext_Reset_In = sys_rst_s PORT Slowest_sync_clk = sys_clk_s PORT Chip_Reset_Req = C405RSTCHIPRESETREQ PORT Core_Reset_Req = C405RSTCORERESETREQ PORT System_Reset_Req = C405RSTSYSRESETREQ PORT Rstc405resetchip = RSTC405RESETCHIP PORT Rstc405resetcore = RSTC405RESETCORE PORT Rstc405resetsys = RSTC405RESETSYS PORT Bus_Struct_Reset = sys_bus_reset PORT Dcm_locked = dcm_0_lock END BEGIN isocm_v10 PARAMETER INSTANCE = iocm PARAMETER HW_VER = 2.00.a PARAMETER C_ISCNTLVALUE = 0x83 PORT ISOCM_Clk = ocm_clk_s PORT sys_rst = sys_bus_reset END BEGIN isbram_if_cntlr PARAMETER INSTANCE = iocm_cntlr PARAMETER HW_VER = 3.00.a PARAMETER C_BASEADDR = 0xffff8000 PARAMETER C_HIGHADDR = 0xffffffff BUS_INTERFACE ISOCM = iocm BUS_INTERFACE DCR_WRITE_PORT = isocm_porta BUS_INTERFACE INSTRN_READ_PORT = isocm_portb END BEGIN bram_block PARAMETER INSTANCE = isocm_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = isocm_porta BUS_INTERFACE PORTB = isocm_portb END BEGIN dsocm_v10 PARAMETER INSTANCE = docm PARAMETER HW_VER = 2.00.a PARAMETER C_DSCNTLVALUE = 0x83 PORT DSOCM_Clk = ocm_clk_s PORT sys_rst = sys_bus_reset END BEGIN dsbram_if_cntlr PARAMETER INSTANCE = docm_cntlr PARAMETER HW_VER = 3.00.a PARAMETER C_BASEADDR = 0x80800000 PARAMETER C_HIGHADDR = 0x80801fff BUS_INTERFACE DSOCM = docm BUS_INTERFACE PORTA = dsocm_porta END BEGIN bram_block PARAMETER INSTANCE = dsocm_bram PARAMETER HW_VER = 1.00.a BUS_INTERFACE PORTA = dsocm_porta END BEGIN plb_v34 PARAMETER INSTANCE = plb PARAMETER HW_VER = 1.02.a PARAMETER C_DCR_INTFCE = 0 PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_bus_reset PORT PLB_Clk = sys_clk_s END BEGIN opb_v20 PARAMETER INSTANCE = opb PARAMETER HW_VER = 1.10.b PARAMETER C_EXT_RESET_HIGH = 1 PORT SYS_Rst = sys_bus_reset PORT OPB_Clk = sys_clk_s END BEGIN plb2opb_bridge PARAMETER INSTANCE = plb2opb PARAMETER HW_VER = 1.01.a PARAMETER C_DCR_INTFCE = 0 PARAMETER C_NUM_ADDR_RNG = 1 PARAMETER C_RNG0_BASEADDR = 0x40000000 PARAMETER C_RNG0_HIGHADDR = 0x400000ff BUS_INTERFACE SPLB = plb BUS_INTERFACE MOPB = opb PORT PLB_Clk = sys_clk_s PORT OPB_Clk = sys_clk_s END BEGIN opb_uartlite PARAMETER INSTANCE = RS232 PARAMETER HW_VER = 1.00.b PARAMETER C_BAUDRATE = 9600 PARAMETER C_DATA_BITS = 8 PARAMETER C_ODD_PARITY = 0 PARAMETER C_USE_PARITY = 0 PARAMETER C_CLK_FREQ = 100000000 PARAMETER C_BASEADDR = 0x40000000 PARAMETER C_HIGHADDR = 0x400000ff BUS_INTERFACE SOPB = opb PORT OPB_Clk = sys_clk_s PORT RX = fpga_0_RS232_RX PORT TX = fpga_0_RS232_TX END BEGIN dcm_module PARAMETER INSTANCE = dcm_0 PARAMETER HW_VER = 1.00.a PARAMETER C_CLK0_BUF = TRUE PARAMETER C_CLKFX_BUF = TRUE PARAMETER C_CLKFX_MULTIPLY = 3 PARAMETER C_CLKIN_PERIOD = 10.000000 PARAMETER C_CLK_FEEDBACK = 1X PARAMETER C_EXT_RESET_HIGH = 1 PARAMETER C_CLKDV_DIVIDE = 2.0 PORT CLKIN = dcm_clk_s PORT CLK0 = sys_clk_s PORT CLKFX = proc_clk_s PORT CLKFB = sys_clk_s PORT RST = net_gnd PORT LOCKED = dcm_0_lock PORT CLKDV = ocm_clk_s ENDArticle: 84017
One possible way for you to do this is with our ChipScope Pro product. In addition to the logic analysis functions, it also has a Virtual Input/Output (VIO) core that you can add to your system for testing, control and debug. You can get a free eval license here: http://www.xilinx.com/chipscope Ed nkishorebabu123@rediffmail.com wrote: > Hi , > > I have a Virtex II Pro FPGA Board and I have a verilog HDL code, I > synthesized and generated bit stream to configure the FPGA. Now unable > to solve the following questions. > > how can I test that code on the board ? I mean how to find verify its > functionality . > how can I drive the input data to the code? > how can I observe the outputs for the given inputs? > > Please help me in this regard. > > Regards, > Kishore >Article: 84018
I want to add libc.a and libm.a into my project and use the the standand C functions such as doing float computing, malloc spaces, to deal with string, and so on. But there are some problems: 1. how to add the libs into my projects. 2. how to use the libm.a and libc.a. what fuctions do the two libs provide? what's the grammar to use the libs? Please help me. Thank you very much!Article: 84019
<nkishorebabu123@rediffmail.com> wrote in message news:1115807606.252661.40300@g47g2000cwa.googlegroups.com... > Hi , > > I have a Virtex II Pro FPGA Board and I have a verilog HDL code, I > synthesized and generated bit stream to configure the FPGA. Now unable > to solve the following questions. > > how can I test that code on the board ? I mean how to find verify its > functionality . > how can I drive the input data to the code? > how can I observe the outputs for the given inputs? > > Please help me in this regard. > > Regards, > Kishore > ummm ... you serious ... what does the code do? If its completely stand alone and has no inputs or outputs ... your done! :0 usually stuff has some IO to communicate to the outside world ... these IO are what you should stimulate and monitor. MikeArticle: 84020
yes,it is stolen .Article: 84021
Bert,
I have an external USB transceiver which sends data to my FPGA.
The spec. of the transceiver says the following:
output delay with respect to the positive edge of clock
tOUT (60MHz clock) 2pF -
12pF -
30pF 9 ns
So if I take into account a transceiver output pin capacitance
of about of let's say 8pF and about 5pF of my FPGA input
pins capacitance (also 5pF for clock input pin of FPGA)
then I would have about the half of 30pF.
That clock-to-output time specification of the transceiver
(I hope that it refers to the clock at user output pin) leads
to the fact that maybe I need to delay my data in the
FPGA input pins so that SETUP/HOLD is not violated.
Which constraint type does fulfill these delay requirements
in the input pins? I mean : Under which name do I have to search
in the Constraint Manager ?
Best regards
Andr=E9
Article: 84022Can UART16550 receive only 16bytes a time, if so, how long should the next receive wait after the first receive? how can i receive the data without losting? I think the FIFO will never be full,when you receive the data from FIFO, it is right?Article: 84023
Neo wrote: > Hi gang, > Future electronics is offering Altera Cyclone/Nios-II Evaluation Kit > for $49. What do other have to say about this deal. > http://www.futureelectronics.com > I might have missed it, but no details on features?Article: 84024
Did you verify all the designs actually meet the desired timing constraints? Check out the *.twr and *.par files in the implementation directory. Paul Joey wrote: > > Hi Everyone, > > I tried to run the processor as well as the OCM with 100/100, 300/100, > 300/300 as well as 300/150 MHz combinations. But the last ones are not > working at all. > > For the 300/300 as well as the 300/150 designs, I have also given > C_DSCNTLVALUE as well as C_ISCNTLVALUE the values 0x81 and 0x83 > respectively. But I am not getting any outputs. The algorithm is infact > floating point intensive and the only thing I am trying to do other than > these calculations is that I am trying to display some intermediate results > through the OPB UartLite. Do you have any suggestions. I am attaching the > mhs file of the 300/150 design below. > > Joe >
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