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I want to extend my program to extern RAM in EDK, But i can't find any document about assemble program of MICROBLAZE or POWERPC, and the usage of GENERATE LINKER SCRIPT dialog in menu TOOL->GENERATE LINKER SCRIPT,please give me some advice,thanks a lot!Article: 85026
Hi BCD, The board I am using isn't an evaluation board. It is Virtex-II Pro50. There are always mistakes with EDK7.1i, but when I do programmes with EDK6.3i, they will be all right. LinaArticle: 85027
Hi all, I am implementing a 6x6 matrix keypad scanner in CPLD. My requirment is i should detect multiple key presses also. What i am planning to do is , i will scan the rows (6 of them sequentially) , when all the 6 rows are scanned i will send the 36 bit output(each bit corresponds to each individual key .'0' indicates pressed)to the controller.The scan rate for each row is approximately 32 msec , so every 32x6=192 msec i will be sending the 36 bit code to controller(HCS12). I want your comments on this implementation in CPLD. Regards, PraveenArticle: 85028
Praveen, It depends on what you want to do in case of multiple key press event. In case of single bit key press, send some encoded information (max. 6 bits) instead of transmitting all the 36 bits. The encoded bit transmission is quite good if you don't want to take any action in case of multiple key press event, or if you want to display some extended character in case of multibit key press. hope that helps. Sunil <praveen.kantharajapura@gmail.com> wrote in message news:1117770846.122441.301610@g47g2000cwa.googlegroups.com... > Hi all, > > I am implementing a 6x6 matrix keypad scanner in CPLD. > My requirment is i should detect multiple key presses also. > What i am planning to do is , i will scan the rows (6 of them > sequentially) , when all the 6 rows are scanned i will send the 36 bit > output(each bit corresponds to each individual key .'0' indicates > pressed)to the controller.The scan rate for each row is approximately > 32 msec , so every 32x6=192 msec i will be sending the 36 bit code to > controller(HCS12). > > I want your comments on this implementation in CPLD. > > Regards, > Praveen >Article: 85029
I do not know why you are so slow, you could easily be a thousand times faster. Since you can only detect a single closure, you could encode the scan into a 6-bit word. I am glad you realized that you cannot detect multiple simultaneous key closures, without inserting iolation non-linearities (diodes) into the array. Peter AlfkeArticle: 85030
At 35 MHz, the period is around 30 ns. If you change the frequency by 1 Hz, you change the period by 30 ns / 35 million. That is less than one femtosecond. (Less than a thousandth of a picosecond) Light travels 0.3 micron (about half its own wave length) in 1 femtosecond. Just to put things in perspective... Peter AlfkeArticle: 85031
xenos wrote: > Hi Everyone, > I am an electrical engineer but I have never had a chance to learn > about FPGAs. I think now is a time to make a foray in this world. My > problem is I dont know where to start. So I will appreciate if someone > can tell me what are the things I will need to start from scratch, like > software, hardware etc. Thanks a lot Since the other posts concentrate on Verilog, I'll give you some pointers on VHDL. Don't want to start up the old Verilog vs. VHDL discussion, just want to give you both options. Since I don't know Verilog, I can't comment on what is easier to learn if you're just getting started. There's a VHDL-tutorial on http://www.vhdl-online.de (available in English), which is OK for starters, I think. On http://www.amontec.com/fix/vhdl_memo/index.html you can find an on-line syntax reference, which is pretty handy. As editor for your source files I recommend Xemacs ( http://www.xemacs.org ), which has excellent support for syntax highlighting, TAB-completion, easy generation of the most commont VHDL constructs and so on, and of course it's free (BTW, it supports Verilog as well). For simulation, just download Xilinx' free ISE WebPack from http://tinyurl.com/bk7km , which includes a limited release of ModelSim (I think it's restricted in simulation speed and the number of lines your source files can have, but it should be enough to get you started). Should you decide to go into this area of work, ModelSim is very likely to be the simulation tool you'll be using, so you might as well just learn the ropes with that instead of starting with another tool and then having to switch to ModelSim later (BTW, WebPack as well as ModelSim support both Verilog and VHDL). ISE WebPack also includes a tool for synthesis, which I think is a good thing for people starting out with the whole FPGA thing. I find that especially for people coming from a software background, it's good if they see from the beginning how their coding style affects the hardware that is generated. Simulating everything until it does what it's supposed to do is one thing, but sooner or later you also have to develop a feeling for how the tools map your code to the hardware. So I think it's not a bad idea to just run synthesis on your code and have a look at the schematic it generates from time to time. As long as it's a smaller project and not too complicated, that can teach you a thing or two as well. Another thing the others haven't mentioned is the fact that you can work with FPGAs without using a HDL at all. Smaller, simpler projects can be entered through schematic entry. This gives you the most control of what will end up in hardware, but can of course get very tedious... HTH, SeanArticle: 85032
Hi Falk I did not get your idea .. Could you please put ur idea in a figure please .. to interface VCO to DDS shall we need a DAC also ? regards bijoyArticle: 85033
The problem is not really feeding the drive with 3.3V, it is more the 5V that's comming back from the drive that can cause problem. You should use level converters. I did desing an ATA interface in the past, but not with an FPGA, I used a micro-controller (ATMEL). Make sure you set correct CS, Address, and pulse DIOR. Also, take note that some of those signals are inverted, make sure you use correct polarity, using inverter if needed.Article: 85034
Hi to all, Sorry to bother you with this reply, but disregard my previous post. The mc8051_Design.zip R1.4 folder can be downloaded using this @: http://www.oregano.at/ip/mc8051/ Have fun with FPGAs :D MikeArticle: 85035
Sorry to bring up this old topic again. Does anybody know how easy/hard it is to enforce IP Laws in Taiwan ? Technically they are still part of China. But how does reality look like ? Anybody has any experience with IP Protection/enforcement in Taiwan ? Horror/success stories ? Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 85036
bijoy wrote: > Hi Falk > > I did not get your idea .. > > Could you please put ur idea in a figure please .. > > to interface VCO to DDS shall we need a DAC also ? I gleam that the idea could be to use a PLL to remove the ugly stuff from a DDS. In my experience, once you have the ugly stuff (noise, glitches, spikes) on your board, it is very hard to get rid of it. ReneArticle: 85037
The PCI spec addresses all your questions. There are two sections on lengths : Motherboard, where the maximum length of the tracks is defined in terms of time (to make sure the bus remains reflective within specific limits) and Expansion card, where the lengths of the tracks are specifically spelled out. Note that the high order 32 bits (for 64 bit implementations) have different length requirements, and for 64 bit implementations, you must alsso be careful about the relative length of #REQ64 and #RST (#REQ64 must still be a valid low when #RST is rising through a valid high) You can get the PCI spec from http://www.pcisig.com/specifications The lengths in each section vary depending on just which implementation you are attempting # bits Speed (MHz) 32 33 64 33 32 66 64 66 PCIX below - in the PCIX supplement 32 100 64 100 32 133 64 133 Cheers PeteSArticle: 85038
Hi Peter,
many thanks for the information, it's working now.
Frank
"Peter Ryser" <peter.ryser@xilinx.com> wrote in message
news:d7lm17$psd1@cliff.xsj.xilinx.com...
> Cacheline and bursts are two different type of transactions. The processor
> can only generate single word, four word cacheline, and eight word
> cacheline transactions but not burst transactions.
>
> Eight word cacheline transactions are generated for memory areas that are
> cacheable. Four word cacheline transactions are generated for
> non-cacheable memory on the instruction side. Single word transactions are
> generated for non-cacheable memory on the data side.
>
> Now, as for the data width - it depends. If your peripheral is on the PLB
> it can be either 32 bits or 64 bits wide. If your peripheral is on the OPB
> it has to be 32 bits wide. In any case you need to make sure that during
> the data phase the wdaddr input signals on the PLB are created correctly.
> Otherwise the processor will hang waiting for the transaction to complete
> and deliver data to all four words.
>
> The PPC405 processor block reference guide explains the different
> transaction types and the signals on the PPC core.
>
> - Peter
>
>
> Frank van Eijkelenburg wrote:
>> No I didn't. Can you give me more details about this? Does this mean that
>> the peripheral should support also bursts, or only bursts. What is the
>> data width of the peripheral. At this moment it is 32 bits, should this
>> be 64 bits?
>>
>> Frank
>>
>>
>> "Peter Ryser" <peter.ryser@xilinx.com> wrote in message
>> news:d74tqf$7vc1@cliff.xsj.xilinx.com...
>>
>>>When you wrote your peripheral did you take into account that it has to
>>>handle four-word cache line transactions? The instruction side of the
>>>processor will issue such a transaction to the peripheral when it comes
>>>out of reset.
>>>
>>>- Peter
>>>
>>>
>>>Frank van Eijkelenburg wrote:
>>>
>>>>Hi Peter,
>>>>
>>>>I am not able to use the debug halt signal. I am using a customized
>>>>board and it does not have buttons which I can use (I will give it a try
>>>>by using virtual IO with chipscope). I understand that the principle of
>>>>starting up like I described should work?! If I convert the generated
>>>>.elf file to a binary file, I see that the boot0 section is laid at the
>>>>correct address. I can also see here what value my user peripheral
>>>>should return ("4BFF7FE4"). It is still not working, I checked the
>>>>peripheral by placing it to another location and have brams from
>>>>0xffff0000 till 0xffffffff. So a normal startup is done and software is
>>>>running fine. Then I do a 32-bits read action to my peripheral and I
>>>>read what I expected to read. What could be wrong?
>>>>
>>>>Frank
>>>>
>>>>
>>>>"Peter Ryser" <peter.ryser@xilinx.com> wrote in message
>>>>news:d73j3d$afq1@cliff.xsj.xilinx.com...
>>>>
>>>>
>>>>>Frank,
>>>>>
>>>>>here is how to debug the setup.
>>>>>
>>>>>First of all, an opcode 4BFF7FE4 at address -4 (aka 0xfffffffc) as
>>>>>
>>>>>(gdb) x/x -4
>>>>>0xfffffffc: 0x4bff7fe4
>>>>>
>>>>>will resolve to the following instruction
>>>>>
>>>>>(gdb) x/i -4
>>>>>0xfffffffc: b 0xffff7fe0
>>>>>
>>>>>In other words, assuming your boot peripheral is correct, the processor
>>>>>will jump to 0xffff7fe0. That's where you need to map the .boot0
>>>>>section or more correctly _boot0.
>>>>>
>>>>>Now, to see what's happening you should bring the DEBUG_HALT signal of
>>>>>the PPC to a user IO pin, for example one of the push buttons on the
>>>>>board. The DEBUG_HALT signal allows stopping the processor, i.e. keep
>>>>>it at the reset vector after a reset or after loading the FPGA
>>>>>bitstream.
>>>>>Assert the DEBUG_HALT signal and load the bitstream. Connect with XMD.
>>>>>Deassert DEBUG_HALT. The PPC is still stopped because of the debugger.
>>>>>Single-step the processor. By following the PC you will be able to see
>>>>>what the PPC is doing. If something in your setup is wrong you will
>>>>>most likely end up at address 0x????0700, the exception vector address
>>>>>for an invalid instruction exception.
>>>>>
>>>>>To monitor the bus transactions instantiate ChipScope (BTW, instead of
>>>>>bringing the DEBUGH_HALT signal above to a user IO pin you could hook
>>>>>it up to a Virtual IO port) and trigger on the PLB request signal.
>>>>>
>>>>>If you try to minimize the boot code, i.e. not use a BRAM at the reset
>>>>>vector, you might want to have a look at application note XAPP571
>>>>>(http://www.xilinx.com/bvdocs/appnotes/xapp571.pdf).
>>>>>
>>>>>- Peter
>>>>>
>>>>>
>>>>>
>>>>>Frank van Eijkelenburg wrote:
>>>>>
>>>>>
>>>>>>I have made a powerpc system with a user peripheral connected to the
>>>>>>plb bus. The user peripheral has an address range from 0xffffff00 -
>>>>>>0xffffffff. At startup the powerpc starts executing from 0xfffffffc,
>>>>>>so my peripheral is accessed at startup. In case of a plb bus read
>>>>>>action, it always returns "4BFF7FE4" which is a jump to my boot0
>>>>>>section laid in bram. In the linkerfile I forced the boot0 section to
>>>>>>a specified address, so the jump should be correct anytime. However,
>>>>>>the system is not starting (no output from my uart port). Should the
>>>>>>described method work, or do I forget something? If it should work,
>>>>>>what could be wrong (I already tried to return "E47FFF4B" in case the
>>>>>>byte order may be incorrect, but it gave the same result).
>>>>>>
>>>>>>TIA,
>>>>>>Frank
>>>>>
>>>>
>>
>>
>
Article: 85039Rudolf Usselmann wrote: > > Sorry to bring up this old topic again. > > Does anybody know how easy/hard it is to enforce IP Laws in > Taiwan ? Technically they are still part of China. But how > does reality look like ? Anybody has any experience with IP > Protection/enforcement in Taiwan ? > > Horror/success stories ? No stories. The highly in awe regarded Philosopher Kung Ze (Confuzius over here) said 2000 years ago : "To become master, copy the master". This is deeply etched inside every chinese. Learn by copying ! Give them another century while awaiting the pope to advertize condoms against AIDS. ReneArticle: 85040
Hello all, Currently we use Windows and 32 bit Linux versions of ISE. We are looking for a way how to increase speed of design implementation. Has someone done any real-world comparison of implementeation (synthesis + map + p&r) run times between 32-bit and 64-bit ISE for Linux? Will upgrading to 64 bit Linux machines bring any shortening of design implementation run time? And if so, how much? At least some rough estimation, please. I would welcome something like... design implementation runtime on Athlon XP 3000+, 2GB RAM was 30 minutes, after upgrading to Athlon A64 3000+, 2GB RAM the same design took just 20 minutes to implement;) Thanks for all replies, JanArticle: 85041
On Fri, 03 Jun 2005 12:17:06 +0200, Jan Pech wrote: > Hello all, > > Currently we use Windows and 32 bit Linux versions of ISE. We are > looking for a way how to increase speed of design implementation. Has > someone done any real-world comparison of implementeation (synthesis + > map + p&r) run times between 32-bit and 64-bit ISE for Linux? Will > upgrading to 64 bit Linux machines bring any shortening of design > implementation run time? And if so, how much? At least some rough > estimation, please. > > I would welcome something like... design implementation runtime on > Athlon XP 3000+, 2GB RAM was 30 minutes, after upgrading to Athlon A64 > 3000+, 2GB RAM the same design took just 20 minutes to implement;) > > Thanks for all replies, > Jan The thing that makes the most difference, at least for simulations, is cache. The 3000+ has a 512K cache, get an A64 with a 1M cache and you'll see a huge difference. NCVerilog runs twice as fast on my 3400+ (1M cache,754 pin) as it does on my 3800+ (1/2M cache, 939 pin). http://www.polybus.com/linux_hardware/index.htmArticle: 85042
Good news we just updated the Gigabit System Reference Design (GSRD) with the hard Tri-mode EMAC (TEMAC) cores and this runs on the ML403. There is no license required to use the hard TEMAC and it will work fine if just need 10/100 or if you just need 1 Gig. More information can be found here: http://www.xilinx.com/gsrd And the updated design files can be found here: http://www.xilinx.com/esp/wired/optical/xlnx_net/gsrd_download.htm Ed kurapati wrote: > Hi Ed, > > Could u please tell me how o use tri-mode-ethernet MACs embedded in > Virtex 4 FX12 for Ethernet application. Is there any reference design > available that uses only embedded MACs but not Gigabit MAC(I suppose > that needs licence and given in ML403 reference design). > > Thank in advance > > with regards > Rajesh >Article: 85043
Hello,
why is there neither Windows XP Embedded nor Windows CE port
for the Nios2 processor? Does Altera plan to create such a port?
If not Nios, then which soft processor would you recommend me?
Best regards
Piotr Wyderski
Article: 85044On 27 May 2005 01:28:02 -0700, "Johnschool" <tanceqi@yahoo.com> wrote: >Hi Jonathan, No, not me; you're mailing to the newsgroup! > I just read the material about Flancter circuit. > Since the short pulse is shorter than one clock cycle, it is >impossible to connect the short pulse to SET_CE and RESET_CE. So I have >to connect the short pulse to SET_CLK, and the system clock to >RESET_CLK. Is this right? Thanks! I think that's the right idea. I don't have in front of me the document you're reading, so I'm not sure; but I think it's right. The Flancter is a twisted ring-of-2 with separate clocks on the two flops. An active edge on one of the clocks will make the two flops' outputs different; an active edge on the other clock makes the two flops' outputs the same. A simple XOR of the two outputs then tells you which of the two clocks happened most recently. Both flops can have a clock enable, but each enable must be in the clock domain of the corresponding flop's clock. The XOR'd output is an asynchronous signal, and it is sometimes necessary to resynch it back into one or the other clock domain using a traditional resynchroniser circuit. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 85045
Hi, I've got a big problem with a Altera Stratix Kit EP1S25. We have integrated it in our application... We have directly connected the +5V +3.3V +1.5V from a DC/DC converter What's happen : We have a kit which the Flash don't program all the time the FPGA at startup, only D8 led is ON (+3.3 V OK), D5 is OFF (CONF_DONE is not OK) Do you know if there's a know problem when start up the card... We have 5 cards in our application and not all the card boot corectly.. ThanksArticle: 85046
"Rene Tschaggelar" <none@none.net> wrote in message news:42a014b0$0$1161$5402220f@news.sunrise.ch... > I gleam that the idea could be to use a PLL to remove > the ugly stuff from a DDS. In my experience, once you > have the ugly stuff (noise, glitches, spikes) on your > board, it is very hard to get rid of it. > > Rene The ugly stuff is hard to remove if it's low frequency ugly stuff. If the jitter frequencies are above the PLL loop frequency, the ugly stuff will go away. The problem is in trying to extract the fundamental frequency +/- a few Hertz from an oscillator with the same frequency. In this situation there *will* be ugly stuff at a few Hertz that can't be filtered by the PLL. Using a completely unrelated (higher frequency) clock could produce a DDS clock at the desired fundamental frequency +/- a few Hertz with almost all the ugly stuff high in frequency if the unrelated clock is chosen well. A 100 MHz clock will have jitter frequencies at 32kHz and higher which would be cleaned up rather well by many zero delay buffers. The Hertz-offset ugly stuff would be about 3 ps peak-to-peak in this arangement. If bijoy really needs that 35.328 MHz as both input and (roughly) output frequencies, the DAC DDS approach is probably the cheapest in the end.Article: 85047
The reason why I'm asking is the following: I'm trying to design a hardware agent which ensures cache-coherency between multiple processors, using an invalidation or an update protocol. Therefor I planned to use OCM as Data Cache, as shown on page 26 (Figure 1-2) in the PPC405 Block Reference Guide. The hardware agent would then be located somewhere between the processor (D-Cache Controller) and the On-Chip Memory. So the actual question is: how does the processor use the OCM connected to the data cache controller? Does this approach make sense at all? :) What I want to achieve is, that the processor somehow "bypasses" the D-Cache Array inside the Data Cache Unit and uses only OCM, so that the hardware agent can react on data-writes to the cache (invalidate or update the corresponding cacheline in the other processors' caches). Do you think, this is possible? Thanks so far, PitArticle: 85048
Hi There, I have Orcad Express CIS 7.2 and I want to program Lattice ispLSI1016 using it. I already have the schematic for it in Orcad Express. Also I have the programmer for 44 pin isp1016. I was wondering if someone can guide me as to what steps I need to take after this. thanksArticle: 85049
Neither nios or nios2 have a MMU, so a full blown RTOS won't work. Eric
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