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Oh yeah, I think its usually called, generated.x. Cheers, JonArticle: 85151
Did you use the "Pipelined divider" with a setting of 1 result every clock? Every 8 clocks? I saw two versions of Pilelined Divider for the Core Generator when I did a quick search on the Xilinx website. There should be full data sheets there for referencing details. FPGAs do a decent job with carry chains. Since that structure is used often enough, it's pretty decent in speed. A test I ran a while back for my own implementation suggested I could get a 16/16 divider running with about 80 ns in one clock cycle without any constraints in a Spartan-2E device if I recall correctly. A faster speed grade Virtex-2 may perform much better. You *are* dividing by a variable, not a constant, right? john.deepu@gmail.com wrote: > Hi all, > I wanted to use a 32/16 divider circuit in one of my designs. I found > Synopsys designware provides Pipelined dividers and decided to use it. > I synthesised DW-divider and found a 3-stage pipeline required to meet > my timing requirement of 20MHz(50ns) in TSMC .13u technology. > > Since I wanted to FPGA prototyping for my asic, I thought of using Core > generator divider while synthesising for Xilnx FPGA.. > > Now the Interesting fact I found is, a 32/16 divider from Xlinx core > genrator can be synthesised(using XST synthesis)to 150Mhz easily for a > Virtex-2 (Xc2v2000)FPGA with just one stage pipeline.. > > At the same time DC-ultra 2004.06-1 is struggling with Designware > foundation divider for meeting a timing of 20MHz with 3 stage > pipeline.... > > I am confused.......... I always thought ASIC synthesis gives more > frequency for an RTL code... > > What I can assume is SYNOPSYS Designware divider is a very bad > implementation of divider... > > Any comments/Clues are welcome.. > > > Thanks > Deepu JohnArticle: 85152
Also, get "Design Warrior's Guide to FPGA" - a very good intro to the technology, workflow etc. There's probably 6-9 good books on Verilog and VHDL - for quick start get something tailored toward practical world design of synthesizable logic. Here's another excellent site: http://www.fpga4fun.com. 30 mins of browsing through it will tell you 85% of what you need to know about FPGAsArticle: 85153
Thanks Jon, for the quick reply. I could find generated.x when I ran Nios II. SunnyArticle: 85154
"Joe" <joe.ricky@gmail.com> wrote in message news:1118033673.908813.128110@g43g2000cwa.googlegroups.com... > Hey, > > I have USB1.1 hard IP and i want to interface this with ARM > processor using AMBA AHB Specification 2.0 for high speed operation. > The vendor of USB core is not supporting us becoz we have bought it > long back. We have only USB datasheet nothing else. Now you please tell > me is there any document to refer. > > Rgds... > Joe > dude what information are u looking for? The AMBA spec is readily available from ARM website. Whose USB core are u trying to implement? If u are asking for doumenation for that ... would you not have received that with the IP .. even if it was a long time ago. Does the USB core have an AMBA interface? Or is the interface something else that you want to modify to connect to an AMBA bus? What is the interface? We need more detail if we are going to help you. MikeArticle: 85155
Hi John,
> Now the Interesting fact I found is, a 32/16 divider from Xlinx core
> genrator can be synthesised(using XST synthesis)to 150Mhz easily for a
> Virtex-2 (Xc2v2000)FPGA with just one stage pipeline..
Not true, I'm afraid. The Coregen pipelined divider is really, really
pipelined. The pipeline depth (i.e. latency) of a divide will always be at
least one clock cycle per bit of dividend width (in your case, 32 clock
cycles). The field called "Clocks per division" is actually not very well
named; it is really the "initiation interval".
So, if you generate a 32/16 divider with Clocks per division set to '1', and
it runs at 150MHz, then you'll be able to do one instruction every clock
(6.66ns), but each one will take, say, 34 clock cycles (~226ns) to complete.
If you generate the same divider but with CPD set to '8', it will most
likely run at a similar speed and the latency will be about the same
(~226ns). However, you can now kick off only one division every eight cycles
(53ns). (The circuit will be considerably smaller than the first example.)
This compares favourably with your Synopsis example, which would appear to
take 50ns*3 = 150ns to do a divide (about 33% less than the Coregen one),
and does one division every 50ns (about the same as the coregen one). So,
Synopsis' divider is not rubbish, but it's nothing to shout about in
performance terms.
The Coregen divider doesn't currently allow you to vary the pipeline depth
manually (to get your 20MHz implementation, for example, by pulling out a
load of registers).However, you can - with care - run the divider on a
faster clock than the surrounding logic and rate match the two.
Hope this helps,
-Ben-
Article: 85156As student, want to search for a job and concentrate my study on it. Any advice for me?Thanks, EthanArticle: 85157
Piotr Wyderski wrote: > David Brown wrote: > >> You want a "free and efficient" cpu, yet you want a Windows port for >> it?? > > > Yes. :-) Thanks to MS Academic Alliance it is possible. Of course > the device will not be produced (i.e. there will exist a single specimen > of it, used by myself). > > Best regards > Piotr Wyderski > If you are an academic, I believe Altera have special prices and deals for academic use. I have no idea of the details, but it's worth checking out. Of course, that doesn't get you any nearer wince on an FPGA - but I personally wouldn't consider using wince for anything but a PDA, even if it were completely free of cost. If you really do try to port wince to an opencores cpu, you are going to have a big job on your hands - while some of the opencores cpus have good toolsets, they are almost exclusively gcc-based, and aimed at either no OS at all, or open source OS's. Trying to get wince working will be "educational", however, which is perhaps your aim here.Article: 85158
This is so important for me. Thank you very much!!!!Article: 85159
I've just formed a Yahoo group for users of the Xilinx/Digilent Spartan 3 Starter Kit: http://groups.yahoo.com/group/s3_kit It'll take a couple of days before it will show up in the group listings, but the above link should work for anyone wishing to join. Leon -- Leon Heller, G1HSM http://www.geocities.com/leon_hellerArticle: 85160
why another forum.... ? there is the official xilinx forum on spartan3 http://toolbox.xilinx.com/cgi-bin/forum (Spartan-3/3E FPGA Forum) please do not scatter the infos ! SandroArticle: 85161
It doesn't hurt anyone to have more than one forum, It might mean that folks have to browse more than one place to find what they need, but there is nothing OFFICIAL about the xilinx forum: it is for customer convenience, that is all. Austin Sandro wrote: > why another forum.... ? > there is the official xilinx forum on spartan3 > > http://toolbox.xilinx.com/cgi-bin/forum > (Spartan-3/3E FPGA Forum) > > please do not scatter the infos ! > > Sandro >Article: 85162
David is correct -- Piotr if you are in any way involved with an academic institution please visit the Altera University website... there are specific contact/enrollment pages for several countries. I believe (but could be wrong on this one) that the email alias university --at-- altera --dot-- com works as well. Back to the original topic: Yes, as already noted WinCE, like "full" Linux, needs a memory management unit, which Nios II doesn't currently offer. I cannot comment on future product features so please don't read anything into that statement either! As far as whether Nios II is free: I would contend, that for the hobbyist all you need is a board, a PC, and a programming cable... and there are boards available that are not so expensive, from $99US on up. The downloadable evaluation core provides complete functionality of Nios II and all peripherals provided that you maintain a JTAG link to your host PC (tethered mode). The only thing missing is the Micrium RTOS. Without the JTAG link you get a time-trial that times out after several hours. I personally think this is quite generous considering the amount of development that has gone into the product over the past 5+ years, and the amount of interesting things one can do with the product while connected via JTAG cable. Jesse Kempa Altera jkempa --at-- altera --dot-- comArticle: 85163
Austin Lesea wrote >It doesn't hurt anyone to have more than one forum, > >It might mean that folks have to browse more than one place to find what >they need, but there is nothing OFFICIAL about the xilinx forum: it is >for customer convenience, that is all The only hurt is to waste (?or spend ?) time going in many place... Sorry for declaring it OFFICIAL... simply I found it on xilinx site and so.... In my opinion's better to have the infos related to the s3 in a place! So I think is better to advertise the NON OFFICIAL xilinx s3 forum than to create a new one! Sandro (A satisfied s3-starter-kit user)Article: 85164
"Sandro" <sdroamt@netscape.net> wrote in message news:1118071856.347592.314250@g43g2000cwa.googlegroups.com... > Austin Lesea wrote >>It doesn't hurt anyone to have more than one forum, >> >>It might mean that folks have to browse more than one place to find what >>they need, but there is nothing OFFICIAL about the xilinx forum: it is >>for customer convenience, that is all > > The only hurt is to waste (?or spend ?) time going in many place... > Sorry for declaring it OFFICIAL... simply I found it on xilinx site and > so.... > > In my opinion's better to have the infos related to the s3 in a place! > > So I think is better to advertise the NON OFFICIAL xilinx s3 forum than > to create a new one! The Xilinx forums aren't specifically aimed at the Digilent board, hence this group. The Xilinx forum is obviously better for general S3 stuff. Leon LeonArticle: 85165
"Sandro" <sdroamt@netscape.net> wrote in message news:1118071856.347592.314250@g43g2000cwa.googlegroups.com... > Austin Lesea wrote >>It doesn't hurt anyone to have more than one forum, >> >>It might mean that folks have to browse more than one place to find what >>they need, but there is nothing OFFICIAL about the xilinx forum: it is >>for customer convenience, that is all > > The only hurt is to waste (?or spend ?) time going in many place... > Sorry for declaring it OFFICIAL... simply I found it on xilinx site and > so.... > > In my opinion's better to have the infos related to the s3 in a place! > > So I think is better to advertise the NON OFFICIAL xilinx s3 forum than > to create a new one! I've just checked, and three people have joined in the last few minutes! LeonArticle: 85166
>bijoy
>
>
One of the troubles with the Coregen cores is that you can't get to the
internal nodes in the design. That means for a filter that uses the
BRAM, you can't get to the other port to reload the coefficients. You
have two options: you can write your own filter (it isn't that hard to
do, just a little time consuming), or you might be able to use the
adaptive filter core instead: I think that leaves an external mechanism
for updating the coefficients.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 851671. I don't believe it can run 150MH without pipelines within the FPGA. 2. There are some hardcore of multipliers in the FPGA and it is used to do divide by multiplications. 3. Please post futher information about it. 4. For pipeline divide algorithm, every clock may permit to feed data with several clocks of delays to get the result. WengArticle: 85168
"Antti Lukats" <antti@openchip.org> schrieb im Newsbeitrag news:d814rs$573$05$1@news.t-online.com... > Hi > > help - please could somebody confirm if the latest uclinux kernel would work > with EDK 7.1 made system using MicroBlaze 4.0 ? > > I do have some problems, the 7.1 built hardware only works with ancient 2003 > made image, with any newer images I get errors and there is never any > bootmessage coming > > I was sure that 4.0 is OK as Gregs V4LX25 demo is made with EDK 7.1 but then > I checked the .MHS and there was still microblaze 3.0 used so I am wonder > why wasnt the MB upgraded to 4.0 ? > > thanks > > Antti > I am replying myself - 3 out 4 microblaze user are not able to use 4.0 for uClinux and all those 3 have downgraded to 3.0 1 out 4 reports no problems with 4.0, to my knowledge this one lucky user is working on linux host, all others are doing the EDK system on windows boxes. not sure where there 4.0 bugs come from and if they are related the host PC OS where the EDK is hosted. Antti PS after downgrading the microblaze to 3.0 www.hydraxc.com started to work fully with networking support!!Article: 85169
Look at C:\EDK\hw\XilinxProcessorIPLib\pcores\opb_bram_if_cntlr_v1_00_a\hdl\vhdl. There you get Code for bram_if_controller.Article: 85170
<praveen.kantharajapura@gmail.com> schrieb im Newsbeitrag news:1118032365.362384.278370@o13g2000cwo.googlegroups.com... > > I worked on this topic not too long ago, you CAN easyly detect multiple > > pressed keys withOUT having diodes in the matrix. > > All you need is a "walking one" scan. > > falk, as you know i am implementing this in a CPLD. > In my application i need multiple(two) key press detection. > As many of them are opposing my 36-bit approach for detecting two keys > pressed simultaneously, my question is how will u achieve multiple key > detection with a 6-bit approach. First of all, as some people noted, without having diodes in the matrix there are possibilities where you can't detect any pressed (or non-pressed) key to 100%. I thougt is was possible, until I had a look back on a few datasheets and used so scratch paper to get it clear. Ashes onto my head ;-) Second, the 6-bit approach wasn't my idea, though it is feasable. If you have only some of the keys to be pressed simultaneously (like you said some kind of SHIFT key), simply reserve one or two bits inside your code word to exlusively encode the state of this key. the rest uses simple binary encoding inside the 6 bit word. So make it easy and use a "standard" 8 bit code and use bit 7 and 6 to encode two s"shift keys" the rest use for the normal keys, which are usually not pressed simultaneously. Depending on the size of your CPLD, you could use a standard UART(inside your CPLD) to transmit your code to the microcontroller. Regards FalkArticle: 85171
Bijoy, Say you can generate 2^^25 = 33554432 Hz clock in the FPGA (or its double / quadruple). This means running NCO with 1 bps resolution is achieved. Now, how to do this??? 33554432 = 35328000 * (8192/8625) if you use a dedicated PLL for this fractional synthesys, like ICS307-03, fine. if not, we can do the following: 8192/8625 = (32/25) * (32/23) * (8/15) First term is done by DCM Second term is first division by FFs, then multiplication using DCM's CLKFX output. the same for the third one. you will have an inevitable jitter as a result of using CLKFX, but i think this is the best you can have. hope this is helpful. Vladislav "bijoy" <pbijoy@rediffmail.com> wrote in message news:ee8ea39.-1@webx.sUN8CHnE... > Hi I am using Spartan-3 fpga > > I need to generate 35.328 MHz clock > > I have an external xtal of 35.328 MHz feeding to FPGA. > > From this clock i need to generate 35.328 MHz square wave with fine > resolution. > > We need a resolution of 1Hz, that means i should be able to change the > square wave out put frequency by 1 Hz resolution. > > I tried to generate this by using DDS core provided by core-generator and > taking the MSBit of the sine wave samples given by the DDS. But the > spurious components generated using this method is too much for my > application to accept. > > Is there any-other way out ? > > ( This is for ADSL Modem appliaction. we currently use DDS provided by > Analog devices. > > So i thought of using FPGA for this purpose as an alternative solution. ) > > Thanks bijoyArticle: 85172
I am not familiar with Codelab but I would be surprised if you had to (gasp!) write your own linker script. For the Nios II IDE (just for comparison's sake), the project properties dialog allows you to assign a memory device in your system to each component of the linker script (.text, .rodata, .exceptions, etc.). When the project is built, the linker script is generated along with it. Jesse Kempa Altera jkempa --at-- altera --dot-- comArticle: 85173
14 week lead time for samples for the XC3S200. How can you prototype with that? It makes worry even more when it comes to manufacture where I might need quantity.Article: 85174
"Ben Twijnstra" <btwijnstra@gmail.com> wrote in message news:8ae63$42a22d01$d55db008$8159@news.chello.nl... > Wednesday. I've been to Dr Johnson's lectures before, and I've even found > his material appliccable to designs running as low as 32MHz. > Ben, Indeed, if you'd read the book ;-) , you'd know it's the rise time and length of the path that matters, not the toggle rate. Cheers, Syms.
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