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On Fri, 13 May 2005 12:48:21 -0700, Lukasz Salwinski <lukasz@ucla.edu> wrote:
>hello,
> there seems to be a plethora of textbooks on VHDL/Verilog
>available. But what about floorplanning ? Are there any
>resources (print/Web) available ?
>
>lukasz
There is some old floorplanning info on my website at:
http://www.fliptronics.com/floorplanning1.html
Plus the following is an example of a larger floorplanning
projects:
http://www.fliptronics.com/gallery.html
In particular, if you look at the MFILT design, (click on the picture
to get the "BIG Picture" of an extremely well packed design. The following
3 designs also show very dense designs that are all well beyond the ability
of the standard P&R tools to handle on their own.
What is great about the MFILT design, is that you can see detailed
schematics for a significant portion of the design, including the
floorplanning RLOCS by reading the patent, 6148313 at either
www.FreePatentsOnline.com
or
http://www.uspto.gov/patft/index.html
Philip
Philip Freidin
Fliptronics
Article: 84476Paul and John, Thanks very much for your replies! So, for 1.25Gbps I'd need to use the SERDES. I guess that means I have to use the PLL circuit to make the clock? If I had more than 1 of these links, how easy is it to ensure that they're all synchronised together. For example, I want to send bits a_1, a_2, a_3, a_4 etc. on I/O LVDS_A I want to send bits b_1, b_2, b_3, b_4 etc. on I/O LVDS_B I use the serdes to do this. Can I ensure that a_n appears at (more or less) the same time as b_n? I.e. that the shift registers in the two serdes are aligned? I know, I should read the bloody manual more carefully, but I couldn't find this on a first pass. Thanks, Syms. "Paul Leventis" <paul.leventis@utoronto.ca> wrote in message news:1116463566.371867.303600@g43g2000cwa.googlegroups.com... > Hi Symon, > > There is a hard serializer/deserializer circuitry available for the > left and right LVDS I/O banks. These SERDES blocks allow you to > deserialize/serialize by any factor between 4 and 10x. For example, > you could bring in a 4x data bus running at 312.5 Mhz. Or you can > bypass the SERDES block and use the DDR registers for a 2x SERDES. Or > bypass completely for 1x... but not at 1.25 Gbps. I don't know what > speed the SERDES/DDR I/O clock can run at or will run at when we update > this specification. I'm sure it will be published at the time. > > We also have dedicated Dynamic Phase Alignment (DPA) circuitry for > source-synchronous applications. The DPA block enables you to > eliminate channel-to-channel and clock-to-channel skew. It achieves > this by selecting the best clock phase to use for each I/O pair, > centering the sampling window in the eye. > > Regards, > > Paul Leventis > Altera Corp. >Article: 84477
Ken, I suggest you use Frequency Synthesis mode (where the 24 MHz min does not apply to the input, but rather to the output), and you multiply by 4 and divide by 1. That uses only one DCM, and gives you 40 MHz, which you can easily divide by 2 in a flip-flop. When you say "the input frequency will be held.." I assume that means you have a constant fequency for that time, then change to another frequency... DCMs do not like interruptions in the input signal. Adjusting to the slightly higher/lower frequency takes a few clock ticks. Peter Alfke, XilinxArticle: 84478
Mukesh, Be careful. When I first saw this post I thought it was a resume harvesting scam. What self-respecting recruitment company uses a free email account? Cheers, Syms.Article: 84479
Make sure that unused IO are tri-stated in your fpga design. --DalonArticle: 84480
Luke Darnell wrote: > Our current design uses clock swallowing to obtain lower frequency clocks. I'd like to implement this clocking behaviour (while still maintaining the phase relationahip between the clocks) inside a VIRTEX4 but don't know if this is possible. For example: > > I input a 44MHz clock. > > I generate a 22MHz clock with 25/75 duty cycle by gating every second 44MHz pulse. > > How can I maintain the phase relationship between the new 22Mhz clock and the origianl 44MHz clock ?? > > All the clock divide options of the DCM's and PMCD's will have 50/50 duty cycle outputs. Is there no method of obtaining a divided phase aligned non 50/50 duty cycle clock? > > regards, Luke darnell how about two bufgce's, both with the 44MHz as input, one always on the other on every other cycle? -LasseArticle: 84481
ARRON wrote: > my FPGA board is XILINX VIRTEX II pro of Memec Design, and the sdram controller IP core is OPB_SDRAM, I add the IP core when i generate a project at the BSB, I think it's wires are not wrong, BUT i don't know the flow of accessing SDRAM, can you help me ? You might want to read the fine data sheets for the SDRAM devices. Hint: Micron and Samsung have excellent data sheets. -aArticle: 84482
Spartan3 is not a processor...
With Spartan3 (and with other FPGA) You can design Your processor
or implement a processor disigned by someone but in each case
the "CPI" depend on how You (or someone) implemented the processor !
You can not implement a processor at all but simply design something
using sequential and combinatorial logic ("flip-flop", "and", "or",
"not" etc)
Sandro
Article: 84483Kolja, I think you meant "one instruction every 10 nanosecods". This thread addresses users who really do not understand the parallel nature of FPGAs. So, powers of ten are important to get right... :-) Peter Alfke, XilinxArticle: 84484
"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag news:1116528920.078592.56050@f14g2000cwb.googlegroups.com... > Kolja, I think you meant "one instruction every 10 nanosecods". > This thread addresses users who really do not understand the parallel > nature of FPGAs. > So, powers of ten are important to get right... :-) > Peter Alfke, Xilinx > Hi Peter, no Kolja did mean 10ms !! per instruction of 1MBIT lenght ;) so in that context the magnitutude is correct, but I agree its not to be understood so easily. 1MBit instruction widht is not usual anttiArticle: 84485
Amir, Why not go down the corridor at Brunel and ask the EE guys? I'm sure they could explain this stuff to you. From your posts I guess you're in the School of Information Systems, Computing and Mathematics? Cheers, Syms. <amir.intisar@gmail.com> wrote in message news:1116508772.460301.184420@o13g2000cwo.googlegroups.com... > Hi, > i am using the Spartan 3 (XC3S200) and the onboard clock on this > FPGA works at 50Mhz, 20ns. Does anyone know how many instructions this > FPGA can do in one cycle (20ns), in other words, what is the CPI(clocks > per instruction) of the SPartan3. > > I want to make a delay that lasts for 1 micro second by using an > incrementing counter. If the CPI for example was one, then i would have > to increment the counter 50 times to get a delay of 1 micro > second.(1*us / 20ns) > > Is that correct ????? thanks !!! >Article: 84486
I'm getting tired of poring over my code to find asynchronous inputs to my state machines that make them go "zero hot." Has anyone seen a context sensitive editor that would let me color my signals by the clocked process that created them? I guess another way to help in this endeavor would be a syntax checker that warns of inputs to state machines that are not synchronous to the same clock. Does that exist? regards, GaborArticle: 84487
> Hallo all, > > I'm trying to implement Jam Byte-Code player ......... Is there another alternative to loading up an ALTERA FPGA???? georgeArticle: 84488
Gabor wrote:
> I'm getting tired of poring over my code to find asynchronous
> inputs to my state machines that make them go "zero hot."
> Has anyone seen a context sensitive editor that would let me
> color my signals by the clocked process that created them?
> I guess another way to help in this endeavor would be a syntax
> checker that warns of inputs to state machines that are not
> synchronous to the same clock.
Another way is to use only clocked processes
and to synchronize the inputs that need it.
-- Mike Treseler
Article: 84489"GMM50" <george.martin@att.net> schrieb im Newsbeitrag news:1116533284.346210.236390@g43g2000cwa.googlegroups.com... > > Hallo all, > > > > I'm trying to implement Jam Byte-Code player ......... > > Is there another alternative to loading up an ALTERA FPGA???? > > george > sure! you can use either slave serial mode or make your own jtag "micro" loader. AnttiArticle: 84490
Hi Antti, Im wondering if i had your point correct, do you mean a 1MBit instruction, 1MBit in width. If this is the case, how would you ever store that instruction? I think Peter wouldnt like people to think that S3 are slow 100hz machines... cheersArticle: 84491
<jaxatwork@gmail.com> schrieb im Newsbeitrag news:1116535154.239883.45540@f14g2000cwb.googlegroups.com... > Hi Antti, Im wondering if i had your point correct, do you mean a 1MBit > instruction, 1MBit in width. If this is the case, how would you ever > store that instruction? > > I think Peter wouldnt like people to think that S3 are slow 100hz > machines... > > cheers > It wasnt me, but Kolja who talked about the comparison of like: 1Mbit wide instruction executing at 10ms per intruction. I think Kolja wanted to compare somewhat the FPGA versus processor (maybe not very succesfully explaining it) if I understood him correctly. This was far fethched comparison in any case. Sure FPGA run WAY fast. but if you reconfigure the FPGA in loop within 10 ms loop period then the 'instruction width' is same as bitstream length? :) maybe I cant explain it any better than the poster (Kolja) I did refer too, but I think I do understand kind of what he wanted to say. And in his context he did mean 10ms not 10ns. AnttiArticle: 84492
Mike Treseler wrote: > Gabor wrote: > > I'm getting tired of poring over my code to find asynchronous > > inputs to my state machines that make them go "zero hot." > > Has anyone seen a context sensitive editor that would let me > > color my signals by the clocked process that created them? > > I guess another way to help in this endeavor would be a syntax > > checker that warns of inputs to state machines that are not > > synchronous to the same clock. > > Another way is to use only clocked processes > and to synchronize the inputs that need it. > > > -- Mike Treseler The point is to find the "inputs that need it" without going crazy in a large design...Article: 84493
Hi Sankalp, Check out and/or post on the Nios forum .. http://www.niosforum.com/forum.htm. There's lots going on over there. -- Pete sankalp.singhal wrote: > hi puneet, > could u suggest me any links related to NIOS II and NIOS II > IDE ......Article: 84494
I would agree. Most recent FPGA families you get I/O registers generally for free and generally not much use for anything else. In some families you can even have 2 flip-flops in the I/O, potentially on different clocks, like in Spartan-3. You probably use far more resource using grey encoding, or some other handling scheme, than just registering the signals as they come into the FPGA. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Gabor" <gabor@alacron.com> wrote in message news:1116536411.513353.8930@z14g2000cwz.googlegroups.com... > > Mike Treseler wrote: >> Gabor wrote: >> > I'm getting tired of poring over my code to find asynchronous >> > inputs to my state machines that make them go "zero hot." >> > Has anyone seen a context sensitive editor that would let me >> > color my signals by the clocked process that created them? >> > I guess another way to help in this endeavor would be a syntax >> > checker that warns of inputs to state machines that are not >> > synchronous to the same clock. >> >> Another way is to use only clocked processes >> and to synchronize the inputs that need it. >> >> >> -- Mike Treseler > > The point is to find the "inputs that need it" without > going crazy in a large design... >Article: 84495
The included code is used to search a serial stream for a sync word and then set a data valid flag for the sync word and the next four words in the stream. Simulation works fine but the post-place and route simulation fails to set the data valid flag. I am assuming that this is a timing problem in detecting the sync pattern but not sure how to correct it. In addition ISE generates three warnings that I am not sure how to resolve. If anyone has the time to look this code over and offer suggestions? Thanks, JoelArticle: 84496
Here is an example of a very recent bullshitter: John Daane, president and CEO of Altera, claims that: "In 1983, Altera invented the first programmable logic device,..." He is not bothered by the fact that MMI invented the successful PAL business four years earlier, and Signetics had produced not-so-successful PLAs even before that. Such facts do not fit into John's view of the world, so he ignores them. That lack of concern for the truth - which even the liar must exhibit in order to lie - is what makes the bullshitter an even greater enemy of the truth than the liar. Peter AlfkeArticle: 84497
If you want to measure the input threshold, just implement an inverting data path from an input to an output, short the two pins together, and decouple them to ground with a capacitor. You now have an oscillator that switches around the threshold. Peter Alfke, XilinxArticle: 84498
Peter, with respect... Could you please provide a source for this quote since what I pick up from google is "Founded in 1983, Altera invented the first reprogrammable logic device..." If I recall, the PAL and PLA devices were one-time programmable. Less objectionable are those who rattle off inforamtion which they believe correct but missed a syllable when they spoke (or were heard). "Peter Alfke" <peter@xilinx.com> wrote in message news:1116537595.959273.273280@o13g2000cwo.googlegroups.com... > Here is an example of a very recent bullshitter: > John Daane, president and CEO of Altera, claims that: > > "In 1983, Altera invented the first programmable logic device,..." > > He is not bothered by the fact that MMI invented the successful PAL > business four years earlier, and Signetics had produced > not-so-successful PLAs even before that. Such facts do not fit into > John's view of the world, so he ignores them. > That lack of concern for the truth - which even the liar must exhibit > in order to lie - is what makes the bullshitter an even greater enemy > of the truth than the liar. > > Peter Alfke >Article: 84499
"Gabor" <gabor@alacron.com> wrote in message news:1116532777.398747.34350@o13g2000cwo.googlegroups.com... > I'm getting tired of poring over my code to find asynchronous > inputs to my state machines that make them go "zero hot." > > Has anyone seen a context sensitive editor that would let me > color my signals by the clocked process that created them? > I guess another way to help in this endeavor would be a syntax > checker that warns of inputs to state machines that are not > synchronous to the same clock. Does that exist? > > regards, > Gabor > Hi Gabor, As a born-again member of the Church of Synchronology, I would question your design philosophy. The bible of Synchronology, the inspired word of the supreme being Xtal, says thus:- Yeah, thou shalt synchronise everything to a masterclock on the way in to the FPGA to make new signals in a single clock domain (Genesis). Clock all your machines with this masterclock (Job). Retime stuff as needed on the way out of the FPGA (Exodus). More work up front, but I'll finish long before you, (Proverbs) and have a much more robust and reusable design, with easy constraints generation (Numbers) as you're now finding out. (Lamentations) Cheers, Syms.
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