Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
We have just bought a new Virtex4 based devleopment board, but were having alot of trouble with the on-chip block RAM. This same design run successfully on a Virtex2 board. We were running ISE 6.3. We just got ISE 7.1 and our problems have gone away. Just a warning to any who might be having problems with Virtex4 block RAMs and are using ISE 6.3, upgrade to ISE 7.1 ASAP. Luke DarnellArticle: 84601
Yes, if tou really (??) need such a long delay, build a 6-bit counter. which takes 6 flipflops. Your 3S200 chip has >3600 flip-flops, so you can easily afford it. But I am still amazed about the need for such a long delay... Peter Alfke, Xilinx ApplicationsArticle: 84602
gg, See below, Austin googlinggoogler@hotmail.com wrote: -snip- > > 1) do i need to supply a clock to the spartan 3, or is there an on chip > one? I have read the data sheets, prehaps not fully, but i couldnt see > any special pins to supply a clock to on there pinout. Best to have a local clock that can be used for whatever you desire. A string of inverters may be used in a pinch for a low accurcy local clock, but that is hardly useful if you actually need to do something useful. Connect the oscillator to one of the dedicated global clock input pins. One can supply an input to aqny pin, and route it where it is needed, but the dedicated clock input pins are he best for lowest skew/delay. > > 2)can i places all the chips for driving the jtag on the board > permentantly with the fpga, or is it good practice to keep this off > board? if so why? One jtag chain of all devices is usual. Simpler, easier, and more convenient than separate chains. > > I think ive got all the important elements sorted, it was just these > issues i was interested in, Have you checked out the support.xilinx.com Signal Integrity Central checklist for pcb design? http://www.xilinx.com/products/design_resources/signal_integrity/index.htm > > If anyone else can point me to a website with a basic schematic so that > I can verify my design, I would be very grateful :-) > > thanks > > David >Article: 84603
Luke Darnell wrote: > We have just bought a new Virtex4 based devleopment board, but were having > alot of trouble with the on-chip block RAM. This same design run > successfully on a Virtex2 board. We were running ISE 6.3. > > We just got ISE 7.1 and our problems have gone away. Just a warning to any > who might be having problems with Virtex4 block RAMs and are using ISE 6.3, > upgrade to ISE 7.1 ASAP. > > Luke Darnell Howdy Luke, I have two designs that I've brought over to V4 from a V2Pro... both worked fine with 6.3.3i, and both use a large number of the BRAM's in many different configurations (FIFO's, single port, and dual port). Is it possible the RAM mode (read-first vs. write-first) isn't set the way it needs to be? We've seen inconsistant results when it wasn't set correctly. Have fun, MarcArticle: 84604
Uwe Bonnes wrote: > Geogle <georgevarughese@indiatimes.com> wrote: > > Any idea why these special drivers are used ? > > Even simple parallel port access won't work without windrvr I guess! > > I was trying an old coolrunner board ( from the days of > > philips coolrunners ) which apparently has a parallel port JTAG > > interfae. Just trying to see if I could use that board. > > While the Xilinx hardware people are very attentive here, i never notice > anybody from the programming department listening here... Looks like they are all Microsoft Windows based developers. Most likely all linux support is provided by Wind/U guys. Thats my guess. BTW, I put a small FAQ at http://www.geocities.com/eda4linux/ise/ise.html. If it could be of use to anyone I will be gladto update it periodically. Thanks, GEorgeArticle: 84605
I only have the parallel III cable. Can I use it to download the bitstream to ML401?Article: 84606
> well usually i would agree that a dev board is allot less hassle, > however i recently got given a couple of spartan 3's and ive got > everything else in my junk box i need to design my own board, so there > is no cost issue involved, except my own which i am not concerned > about. Well huh, no cost issue ... I also have have spare components but the cost of the PCB manufacturing and assembly for just 1 board is pretty high depending on what you want to do (e.g. for a BGA spartan 3, you'll need like 6 layers board and 0402 decoupling on the back ) > As FPGA design is new to me (its something i really want to get into) I > was woundering whether you could prehaps clear me up some questions i > have? > > 1) do i need to supply a clock to the spartan 3, or is there an on chip > one? I have read the data sheets, prehaps not fully, but i couldnt see > any special pins to supply a clock to on there pinout. Use a xtal oscillator chip connected to one of the global clock. Depending on the devices you intend to put on your dev board, you may want to connect the other global clock for theses. Also, if you need de-skew, a DCM feed back pin might be needed. > 2)can i places all the chips for driving the jtag on the board > permentantly with the fpga, or is it good practice to keep this off > board? if so why? 1 jtag chain, the soft can handle that. > If anyone else can point me to a website with a basic schematic so that > I can verify my design, I would be very grateful :-) Well, for a FPGA, except for the power supply and configuration, the rest is up to you (depending on the device). And for the power supply of spartan 3, TI has good appnotes and for configuration, just look up the datasheet of the spartan 3, it's basically just pin to pin connection of the configuration PROM. The other bits are dependent on what devices you want on your devboard. Of you course you can connect all the I/O pins to connectors but be aware that some peripherals are not easy to add on a daughter board ( like RAM) SylvainArticle: 84607
Geogle <georgevarughese@indiatimes.com> wrote: > Uwe Bonnes wrote: > > Geogle <georgevarughese@indiatimes.com> wrote: > > > Any idea why these special drivers are used ? > > > Even simple parallel port access won't work without windrvr I > guess! > > > I was trying an old coolrunner board ( from the days of > > > philips coolrunners ) which apparently has a parallel port JTAG > > > interfae. Just trying to see if I could use that board. > > > > While the Xilinx hardware people are very attentive here, i never > notice > > anybody from the programming department listening here... > Looks like they are all Microsoft Windows based developers. Most likely > all linux support is provided by Wind/U guys. Thats my guess. The worker functions (xst and such) seem like normal C programs. Only the GUI and the interface to the programmer are Windows-burdened... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 84608
It is an FPGA Question?Article: 84609
Hi all, I've been working on a project that has uses a FSM and have run out of ideas about why it's not working. There are four states, an input from off chip triggers the change between most states, except the "00" state which automatically changes to the "01" state on the rising edge of the clock. However, after running the design for a while the state stops changing and is stuck in the "00" state, where it should automatically change regardless of the input. Any ideas as to why this is happening would be much appreciated. Included below is my code. Thanks! Jesse process(CLK) begin if(rising_edge(CLK)) then state <= nextState; end if; end process; process(CLK) begin if(rising_edge(CLK)) then case state is when "00" => nextState <= "01"; CLK_OUT_tmp <= '1'; stateo(2 downto 0) <= "100"; when "01" => CLK_OUT_tmp <= '0'; if(Din = '1') then nextState <= "11"; else nextState <= "10"; end if; stateo(2 downto 0) <= "101"; when "10" => CLK_OUT_tmp <= '0'; if(Din = '1') then nextState <= "00"; else nextState <= "10"; end if; stateo(2 downto 0) <= "110"; when "11" => CLK_OUT_tmp <= '0'; if(Din = '1') then nextState <= "11"; else nextState <= "00"; end if; stateo(2 downto 0) <= "111"; when others => nextState <= "00"; stateo(2 downto 0) <= "111"; end case; end if; end process;Article: 84610
First immediate thought - Is your input signal synchronous to your clock or guaranteed to meet setup and hold of your flip-flops. If not your state machine could be entering an unexpected state and staying there. You look like you are hard encoding the state values and this fairly unlikely to affect you unless your synthesis has added bits to state machine or has done a replication of bits. In which case the bits that you are monitoring may not be what the machine is operating on. Second thought - You have registered both next state and current state transactions. Most people only do the current state with next state as an asynchronous process. What you have done isn't wrong but you need to think that the values that you are working on are 2 clocks old and you need to take account of that. It is all to easy to lose track of where you are and what should happen. A good simulation is recommendation either as matchbox paper sketch or better with a proper simulator. John Adair Enterpoint Ltd. - Home of PCI Development Boards. http://www.enterpoint.co.uk "gralsto" <jralston@gmail-dot-com.no-spam.invalid> wrote in message news:Zt6dnYxMZLDZDAzfRVn_vA@giganews.com... > Hi all, > I've been working on a project that has uses a FSM and have run out of > ideas about why it's not working. There are four states, an input > from off chip triggers the change between most states, except the > "00" state which automatically changes to the "01" state on the > rising edge of the clock. However, after running the design for a > while the state stops changing and is stuck in the "00" state, where > it should automatically change regardless of the input. Any ideas as > to why this is happening would be much appreciated. Included below is > my code. > > Thanks! > Jesse > > process(CLK) > begin > if(rising_edge(CLK)) then > state <= nextState; > end if; > end process; > > process(CLK) > begin > if(rising_edge(CLK)) then > case state is > when "00" => > nextState <= "01"; > CLK_OUT_tmp <= '1'; > stateo(2 downto 0) <= "100"; > > when "01" => > CLK_OUT_tmp <= '0'; > if(Din = '1') then > nextState <= "11"; > else > nextState <= "10"; > end if; > > stateo(2 downto 0) <= "101"; > > when "10" => > CLK_OUT_tmp <= '0'; > if(Din = '1') then > nextState <= "00"; > else > nextState <= "10"; > end if; > stateo(2 downto 0) <= "110"; > > when "11" => > CLK_OUT_tmp <= '0'; > if(Din = '1') then > nextState <= "11"; > else > nextState <= "00"; > end if; > stateo(2 downto 0) <= "111"; > > when others => > nextState <= "00"; > stateo(2 downto 0) <= "111"; > end case; > end if; > end process; >Article: 84611
I think, even with this double registering of states the FSM shouldnt hang in state "00". it will be good if you have a reset signal to start your fsm in a known state. the present code dosent have an initial state for the fsm. And also remove your clock event in your second process and make it sensitive only to state.Article: 84612
This use is neither standard nor tested. See the -Wa,OPTION switch in the documentation: http://ghdl.free.fr/ghdl/Passing-options-to-other-programs.html#Passing-options-to-other-programs Tristan.Article: 84613
Hi, I have made a simple design for a powerpc. The code is running from bram and starts at 0xFFFF_0000, because I am using interrupts (when using interrupts the code needs to be 64 kB aligned). The ppc starts always at 0xFFFF_FFFC. The simplest thing to do is defining a bram space which starts at 0xFFFF_0000 and ends at 0xFFFF_FFFF. This will take 32 brams, while my application is less the 64 kB (it could fit into 12 brams). So about 20 brams are not used by application and not available for other purposes. To reduce the used brams I have added a second bram controller which starts at 0xFFFF_C000 and ends at 0xFFFF_FFFF. I also changed the linker script and now I am saving 8 brams. The whole design is running fine. The second bram controller is starting at 0xFFFF_C000 because the minimum required size was 16 kB. However, it should only contain the boot and the boot0 sections. So 1 bram should also more than enough. My question is: how can I save more brams? Do I have to make my own plb device which lays from 0xFFFF_F800 to 0xFFFF_FFFF? If so, how can I make it initialized with the boot and boot0 sections (how can I get this bram automatically in the bmm file which is generated by XPS and used by ISE)? TIA, FrankArticle: 84614
The clock might stop running. How did you know that the state is stuck at "00"? Jim "gralsto" <jralston@gmail-dot-com.no-spam.invalid> wrote in message news:Zt6dnYxMZLDZDAzfRVn_vA@giganews.com... > Hi all, > I've been working on a project that has uses a FSM and have run out of > ideas about why it's not working. There are four states, an input > from off chip triggers the change between most states, except the > "00" state which automatically changes to the "01" state on the > rising edge of the clock. However, after running the design for a > while the state stops changing and is stuck in the "00" state, where > it should automatically change regardless of the input. Any ideas as > to why this is happening would be much appreciated. Included below is > my code. > > Thanks! > Jesse > > process(CLK) > begin > if(rising_edge(CLK)) then > state <= nextState; > end if; > end process; > > process(CLK) > begin > if(rising_edge(CLK)) then > case state is > when "00" => > nextState <= "01"; > CLK_OUT_tmp <= '1'; > stateo(2 downto 0) <= "100"; > > when "01" => > CLK_OUT_tmp <= '0'; > if(Din = '1') then > nextState <= "11"; > else > nextState <= "10"; > end if; > > stateo(2 downto 0) <= "101"; > > when "10" => > CLK_OUT_tmp <= '0'; > if(Din = '1') then > nextState <= "00"; > else > nextState <= "10"; > end if; > stateo(2 downto 0) <= "110"; > > when "11" => > CLK_OUT_tmp <= '0'; > if(Din = '1') then > nextState <= "11"; > else > nextState <= "00"; > end if; > stateo(2 downto 0) <= "111"; > > when others => > nextState <= "00"; > stateo(2 downto 0) <= "111"; > end case; > end if; > end process; >Article: 84615
Hello! Is there any hardware documentation to RISCWatch of PPC405 in Xilinx devices? I look for waveforms describe the signals of the interface. Is there any JTAG vendor specific commands used to debug the processor? Thanks!!! krzysiekArticle: 84616
This looks very similar to convolution. I suggest looking at cores that can do this. Regards, Luc On Sun, 22 May 2005 13:29:24 -0400, "Andrew Lohbihler" <andrewl@rogers.com> wrote: >Hi , > >I'm looking for a core in VHDL that does a vector product. Basically the >following calculation: > >Out = Coeff(1) * In(1) + Coeff(2) * In(2) + ... +Coeff(n) * In(n) > >for n=15 or more. > >Note that input signal "In(i)" is not a time delayed signal, but rather a >"present" time vector of data. Hence using a FIR core or similar would not >do this. The input and coefficients are 12-bit minimum. I'm looking for a >readily available core that is optimized for latency and space, preferrably >a Xilinx core or other that allows for variable coefficient sizes and vector >lengths. > >Anything would be helpful. Thanks, > >Andrew >Article: 84617
Luke,
Can you be more specific what kind of trouble you had (have) with the
block ram or can you provide a testcase if you have isolated the problem
to brams
Thanks,
Aurash
Luke Darnell wrote:
>We have just bought a new Virtex4 based devleopment board, but were having alot of trouble with the on-chip block RAM. This same design run successfully on a Virtex2 board. We were running ISE 6.3.
>
>We just got ISE 7.1 and our problems have gone away. Just a warning to any who might be having problems with Virtex4 block RAMs and are using ISE 6.3, upgrade to ISE 7.1 ASAP.
>
>Luke Darnell
>
>
--
__
/ /\/\ Aurelian Lazarut
\ \ / System Verification Engineer
/ / \ Xilinx Ireland
\_\/\/
phone: 353 01 4032639
fax: 353 01 4640324
Article: 84618
An example in Verilog:
always @(posedge Clk_36MHz)
begin // counting 0-24, inclusive
count <= count + (enable ? -5'd24 : +5'd1);
enable <= (count==5'd24);
out_clk <= enable | (count<5'd12);
if( enable )
begin
// do everything here at
// 1.44 MHz, no gated clock
end
end
A gated clock would be:
wire ClkGated = Clk36MHz | ~enable;
always @(posedge ClkGated)
begin
// do everything at 1.44 MHz with severe clock skew
end
Which - it appears you know - isn't a great way to go.
"Marco" <marcotoschi_no_spam@email.it> wrote in message
news:d6plfi$o79$1@news.ngi.it...
<snip>
> > > What I could do?
<snip>
> > Since the ratio of 1.44 MHz / 50 MHz is 18/625, you could use one DCM in
> > frequency synthesis mode to get an 18/25 multiplier (36 MHz). Use that
> > for your internal clock WITH a clock-enable for the whole thing once
> > every 25 cycles. Also use that clock enable to drive an IOB register
> > high which you then deassert 12 or 13 36 MHz clocks later for 48%/52%
> > duty cycle.
> >
> > Clean, workable.
<snip>
Article: 84619Hello eveyone, I have a design involving a Lattice ispMACH4384. The pinout is already fixed. I have to make a 5:1 24bit MUX. Unfortunately, the output pins are all located in GLB H, J and K. As the expert clearly sees, the 24bit MUX overloads the input signal capabilities of the GLBs (36 max.). So I want to split up the MUX into two cascaded MUXes. I tried the VHDL attribute syn_keep, but this is ignored by the fitter tools. How can I prevent the node collapsing for this 2 MUXes? Iam using ispLEVER with Synplify. Regards FalkArticle: 84620
I remember a few years ago we would have to run ISE PAR several times
in order to meet timing. One we had a decent layout, we would lock it
down because of the chance of never being able to reproduce it.
Does ISE still suffer nondeterministic placement?
Also, how much has ISE PAR improved since 5.1/6.1?
-Tom
Article: 84621Falk Brunner schrieb: > Hello eveyone, > > I have a design involving a Lattice ispMACH4384. The pinout is already > fixed. I have to make a 5:1 24bit MUX. Unfortunately, the output pins are > all located in GLB H, J and K. As the expert clearly sees, the 24bit MUX > overloads the input signal capabilities of the GLBs (36 max.). So I want to > split up the MUX into two cascaded MUXes. I tried the VHDL attribute > syn_keep, but this is ignored by the fitter tools. How can I prevent the > node collapsing for this 2 MUXes? Iam using ispLEVER with Synplify. > > Regards > Falk Why do you want to use the KEEP attribute at all ? What does the fitter do you want to prevent, why do you want to prevent that? Some code? Rgds Andr=E9Article: 84622
Hi I have parallel III cable and I tried to connect to JTAG interface port on ML403 board but I found it difficult to connect because of insufficient spacing between pins. any help please.. byeArticle: 84623
Hi all, FPGA are fun to work with ... when the tools work. New versions of the tools come out, then serice packs, but there is no light that the tools would actually work better. This is towards Xilinx tools. I used lately also Quartus 4.2 for several desings and dont recall having any tool related issues at all. http://wiki.openchip.org/index.php/ISE there are some my current identified problems with ISE 7.1, unfortunatly backing up to 6.3 doesnt also work for me as the most needed feature has a problem on 6.3 - chipscope core inserter makes the working design a non working design. I can not belive that everything do try todo with Xilinx tools is so weird that nobody else (e.g. xilinx internal testing team) has ever tried that. But with almost anything I touch I see the tools either crash or not properly working. Some issues are minor, and I can figure out some workarounds, that takes time, but if the problem can be circumvented its ok. Some issues are more fatal. At the moment the current state (of xilinx tools) really doesnt look like the next service pack would resolve the major issues (those I am aware of, there are mort likely many more of them). At the very present moment I am really in not good mood as I need to verify some designs VERY URGENTLY and the tools just fail there where I need them. AnttiArticle: 84624
If you have a spare i/o pin attach the intermediate mux o/p to that. It is a dirty trick but usually works. I used to do something like this in the old days with Intel (later Altera) flexlogic which had a 24V10 structure and forever was running out of block fan-in signals. I don't often see problem now with the CPLDs I tend to use. Similar vein - if you can register an intermediary o/p then you can get the same result. You can use opposite clock edges if your design uses a clocked o/p and the device supports if you want to avoid an extra clock latency. You can also look at synthesiser switches but I'm slightly rusty of Synplify to tell you exactly the switches. Taking some of the logic to files lower in your structure and ensuring no boundry optimisation can work as well. You can also instantiate components such as final OR for the intermediate term may also give the desired result. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:3fec7lF7b2ljU1@individual.net... > Hello eveyone, > > I have a design involving a Lattice ispMACH4384. The pinout is already > fixed. I have to make a 5:1 24bit MUX. Unfortunately, the output pins are > all located in GLB H, J and K. As the expert clearly sees, the 24bit MUX > overloads the input signal capabilities of the GLBs (36 max.). So I want > to > split up the MUX into two cascaded MUXes. I tried the VHDL attribute > syn_keep, but this is ignored by the fitter tools. How can I prevent the > node collapsing for this 2 MUXes? Iam using ispLEVER with Synplify. > > Regards > Falk > > >
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z