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I am using an altera cyclone, and want to use the internall pll to divide by 10 a clock. The megawizard plug in manager (form quartusII 4.1 SP2) give the following error messages : "Cannot implement the requested pll, cause : post divider max count exceeded" but the divider counter should be 10, and it possible values are from 1 to 32. So what is the problem ?Article: 76551
GL wrote: > I am using an altera cyclone, and want to use the internall pll to > divide by 10 a clock. > The megawizard plug in manager (form quartusII 4.1 SP2) give the > following error messages : > "Cannot implement the requested pll, cause : post divider max count > exceeded" > but the divider counter should be 10, and it possible values are from 1 > to 32. > So what is the problem ? What is your input frequency?Article: 76552
Hello! Is it safe to configure a FPGA with 1.8 VCCIO standard set (i.e. LVCMOS18) and supply the VCCIO pads by 3V3? I am going to switch a power supply from 3V3 to1V8 several seconds after the configuration. Vref pads are not used. Best regards, krzysiekArticle: 76553
I have this:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
Library UNISIM;
use UNISIM.vcomponents.all;
entity lupicrudi is
Port ( clk : in std_logic;
clkx2 : out std_logic;
clkout : out std_logic);
end lupicrudi;
architecture Behavioral of lupicrudi is
signal dummy: std_logic;
signal trosky: std_logic;
begin
BUFG_inst : BUFG
port map (
O => trosky, -- Clock buffer output
I => dummy -- Clock buffer input
);
clkx2 <= trosky;
CLKDLLE_inst : CLKDLLE
generic map (
CLKDV_DIVIDE => 4.0,
DUTY_CYCLE_CORRECTION => FALSE,
FACTORY_JF => X"C080",
STARTUP_WAIT => FALSE)
port map (
CLK2X => dummy,
CLKDV => clkout,
CLKFB => trosky,
CLKIN => clk,
RST => '0'
);
end Behavioral;
It doesn't work. clkx2 output is ok but clkout is always high.
what is wrong with this source?
I use an xc2s50e and ise webpack 6.3.02.
thanks
--
Mastupristi?
Article: 76554piet@parsec.co.za avait soumis l'idée : > GL wrote: >> I am using an altera cyclone, and want to use the internall pll to >> divide by 10 a clock. >> The megawizard plug in manager (form quartusII 4.1 SP2) give the >> following error messages : >> "Cannot implement the requested pll, cause : post divider max count >> exceeded" >> but the divider counter should be 10, and it possible values are from 1 >> to 32. >> So what is the problem ? > > What is your input frequency? My input frequency is 20 Mhz... and my output would be 2Mhz -- Ceci est une signature automatique de MesNews. Site : http://www.mesnews.netArticle: 76555
"Rune Christensen" <rune.christensen@adslhome.dk> wrote in message news:41b42d96$0$81682$edfadb0f@dread14.news.tele.dk... > Hello > > Do anyone have some examples of connecting a FPGA to the isa bus? > > I'm looking for how to connect to the interrupt lines. > - Pulse length (minimum, maksimum)? > - Pulse polarity (positive I think)? > > Thanks > Rune Christensen Apart from the fact that ISA signals are 5V and I hope you have already addressed that, I can remember these points (it's been years since my last ISA design with and FPGA...) -Pulse Polarity: You should send a Positive voltage for the interrupt -Pulse length: There is no minimum or maximum!! You should keep the IRQ high till you recieve the acknowlege from the interrupt handler. But there is no interrupt acknowlege line on ISA!? So in practice, you should use something like a D flip-flop and connect the output to the IRQ line. When you reach the interrupt routine, the software should write to a port to clear this flip-flop using its asyc reset (or sync reset: the one that is simpler for you). Now, you may ask how on earth would it be possible to share the same interrupt line between different cards? but the answer would be a long story.... Best Regards ArashArticle: 76556
Another question regarding the NCO... Does any of you guys knows the algorithm for calculating the jitter frequency on the NCO output (MSbit) . I know that the jitter magnitude is + - [reference clock period / 2] and I know that I can see it (the frequency) also in a Spectrum analyzer but I will be glad to have a formula for calculating it in advance. Thanks again, Moti.Article: 76557
Sean Durkin wrote: > Rudolf Usselmann wrote: >> >> Just upgraded ISE and EDK to 6.3 from 6.2. We use a small SoC >> consisting of a microblaze, SDRAM/DDRAM controllers and RS232 >> (uartlite). >> >> We use various development boards from Memec-Insight with >> Virtex 1000 and VP20. We always use microblaze CPU, and >> depending on the development board SDRAM or DDRAM controllers. >> >> Anyway, after the upgrade, the soc seems to be broken. Looks >> like the UART output is somewhat garbled. I don't want to >> debug the SoC again, just because I upgraded the tools. > Garbled UART output sounds like the baudrate may be incorrect. Maybe the > UART-settings somehow got lost/changed during the upgrade? Or maybe they > changed the name of the parameter that sets the baudrate in the latest > version of the UART-core. > Is the UART the only problem and everything else is working fine? > > cu, > Sean Sorry, I was not very clear. The UART prints half of the message ok, than skips a lot than again a few readable words ... I did check all the obvious things like baud rate etc. Thats not it. There seems some fundamental difference. The SoC seems to "hang" as well. Like may be something in the software changed ... it still does compile clean, and I did re-compile everything ... I spend two days trying to figure out what was wrong, than switched back to EDK 6.2. Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 76558
usrdr@yahoo.co.uk wrote in news:1102324732.066813.273510 @c13g2000cwb.googlegroups.com: > Hi, > I'm thinking to purchase xess fpga board (XSA and XST-2). I don't know > I should buy which one. All XSA boards have almost same features. What > do you think about it? > Thanks to all > > >From a price standpoint, you only have two choices to consider: XSA-200 @ $149: 200K-gate FPGA, 32 MByte SDRAM, 2MByte Flash, 9-bit VGA XSA-3S1000 @ $199: 1M-gate FPGA, 32 MByte SDRAM, 2MByte Flash, 9-bit VGA The XSA-200 uses a Spartan2 FPGA that is 5V-tolerant and so this board is compatible with the XST-2. The 3S1000 uses a Spartan3 FPGA that is NOT 5V- tolerant, so you will have to wait for the new XST-3.0 Board in 2005. -- ---------------------------------------------------------------- Dave Van den Bout XESS Corp. PO Box 33091 Raleigh NC 27636 Phn: (919) 363-4695 Fax: (801) 749-6501 devb@xess.com http://www.xess.comArticle: 76559
Check the Xilinx support page: Here's a link to one of the answers: http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=12995 The short answer is that VirtexE and SpartanIIE devices share the same IDCODE. I ran into this problem also, but once I found out it was okay that the two devices had the same IDCODE I just ignored the warning messages. Everything worked fine. Hope this helps, Jeremy Mastupristi wrote: > I use a Spartan2E xc2s50e, but when I configure it using Parallel Cable IV > JTAG, it is recognised as a VirtexE xcv50e!!! > > Obviously my .bit file is configured as xc2s50e and there is no problem when > I configure the flash xcf01s. When I try to configure directly the fpga it > gives me a warning, but works fine. > > The problem is when I try to use Chipscope pro: > COMMAND: configure 1 "C:\Lavori\menfis\ACQ3000\FPGA\acq3000.bit" 0 > ERROR: Configuration Failed: > > Done Pin is low > INFO: Found 0 Core Units in the JTAG device Chain. > > > I think the problem is that it recognise an xcv50e, while .bit file is > configured for xc2s50e. > > How can I make it recognise correctly my spartan2e? > > thanks > > -- > Mastupristi?Article: 76560
Tip: if you can arrange that units sourcing the bus drive 0's when "tristated", either by using flip-flop outputs (use the built-in synchronous reset functionality) or using logic that can be finagled to output 0, then you can simply 'or' these sources together. This can be cheaper in gates or levels of logic than using a general purpose n-bit m-source multiplexer. Ex-100%-of-TBUFs-user, Jan GrayArticle: 76561
>>> I am using an altera cyclone, and want to use the internall pll to >>> divide by 10 a clock. >>> The megawizard plug in manager (form quartusII 4.1 SP2) give the >>> following error messages : >>> "Cannot implement the requested pll, cause : post divider max count >>> exceeded" >>> but the divider counter should be 10, and it possible values are from >>> 1 to 32. So what is the problem ? >> >> >> What is your input frequency? > > > My input frequency is 20 Mhz... and my output would be 2Mhz > Read chapter 6 of the Cyclone manual. fout = fINx(M/(NxG0)) and fVCO = fINx(M/N) now M can be from 2 to 32 and N and G0 from 1 to 32. fVCO must be between 300 and 800 MHz. since fIN is 20MHz M must be at least 15 when N = 1. Other option is M>=30 and N=2. fOUT is desired to be 2MHz thus G0 must be 150 when M=15 or 300 when M = 30 so this is not possible... If you want to divide 20MHz by 10 you'll need a counter to do that. Just count from 4 to 0 and on 0 alternate the outputclock and start counting again from 4. Hope this helps, JanArticle: 76562
krzysiek, Since the IO driver is selected by choosing the number of transistors to drive in parallel (drive strength) a driver configured for 1.8V LVCMOS will be much stronger when operated at 3.3V. I believe you will have to choose you IO standard carefully so as to not have too many signal integrity problems. If you download the encrypted hspice models, and can simulate, you could actually see just how much stronger the 1.8V driver is when operated at 3.3V. Conversely, you could choose a 3.3V driver that you want for later operation, and then see just how weak it gets when operating from 1.8 volts. I believe this is a better choice. Austin Krzysztof Szczepanski wrote: > Hello! > > Is it safe to configure a FPGA with 1.8 VCCIO standard set (i.e. LVCMOS18) > and supply the VCCIO pads by 3V3? > I am going to switch a power supply from 3V3 to1V8 several seconds after the > configuration. > Vref pads are not used. > > Best regards, > krzysiek > >Article: 76563
Hi, Sorry it took so long, but here it is, a module that will record RGB video data to TIFF files. A small testbench is also provided: http://www.fpga-games.com/cx2600/tiff/ I hope it helps somebody, I found it useful. I'd like to thank everyone for their input on this topic. EricArticle: 76564
"Rudolf Usselmann" <russelmann@hotmail.com> wrote in message news:cp0to8$53k$1@nobel.pacific.net.sg... > > Just upgraded ISE and EDK to 6.3 from 6.2. We use a small SoC > consisting of a microblaze, SDRAM/DDRAM controllers and RS232 > (uartlite). > > We use various development boards from Memec-Insight with > Virtex 1000 and VP20. We always use microblaze CPU, and > depending on the development board SDRAM or DDRAM controllers. > > Anyway, after the upgrade, the soc seems to be broken. Looks ...another sad story... I think I can honestly say that I have spent at least 6 full weeks "fighting with EDK". My estimate is that anyone who is responsible to maintain several EDK based SoC systems should count with minimum 1 week of extra time spent fixing up the projects when doing minor updates of EDK. That is sad. Its wasted time. Time that no-one pays for. Maybe the situation gets better with EDK 7, I can only hope. The above is my opinion and I stick to it. Maybe others have been more lucky, but I started with V2PDK 1.5 then EDK, pretty much all versions used! There is no way not to update and update has always been painful. AnttiArticle: 76565
"Moti" <moti@terasync.net> wrote in message news:1102341075.941696.112870@c13g2000cwb.googlegroups.com... > Another question regarding the NCO... > > Does any of you guys knows the algorithm for calculating the jitter > frequency on the NCO output (MSbit) . > I know that the jitter magnitude is + - [reference clock period / 2] > and I know that I can see it (the frequency) also in a Spectrum > analyzer but I will be glad to have a formula for calculating it in > advance. > > Thanks again, Moti. It's a bit involved to find the largest jitter components but I've worked the problem in the past and found a direct correlation between my expected jitter components and the FFT of the NCO output. Effectively, your jitter components are at the offsets between the frequency of your NCO and the best fractions that approximate your NCO output-to-input frequency ratio (and the harmonics thereof). If you can figure the closest fractions in sequency, you can get your main jitter components. There is some mixing among these frequencies but it tends to be significantly lower than the main peaks in the scenarios I ran.Article: 76566
"Dave Vanden Bout" <devb@xess.com> wrote in message news:Xns95B7628A18065devbxesscorp@24.25.9.42... > usrdr@yahoo.co.uk wrote in news:1102324732.066813.273510 > @c13g2000cwb.googlegroups.com: > > > Hi, > > I'm thinking to purchase xess fpga board (XSA and XST-2). I don't know > > I should buy which one. All XSA boards have almost same features. What > > do you think about it? > > Thanks to all > > > > > > From a price standpoint, you only have two choices to consider: > > XSA-200 @ $149: 200K-gate FPGA, 32 MByte SDRAM, 2MByte Flash, 9-bit VGA > XSA-3S1000 @ $199: 1M-gate FPGA, 32 MByte SDRAM, 2MByte Flash, 9-bit VGA I would go with 3S1000! the S200 is just enough for Microblaze SoC and too small for GPL Sparc SoC, sure the 3S IO's are not 5v tolerant any more so care should be taken if connecting to 5V peripherals AnttiArticle: 76567
Hi Jhon, thanks for your reply, altough I have to admit that I didnt entirely understood how to actually caluculate the frequency. Best regards, MotiArticle: 76568
"Rudolf Usselmann" <russelmann@hotmail.com> wrote in message news:cp0to8$53k$1@nobel.pacific.net.sg... > > > Just upgraded ISE and EDK to 6.3 from 6.2. We use a small SoC > consisting of a microblaze, SDRAM/DDRAM controllers and RS232 > (uartlite). > > We use various development boards from Memec-Insight with > Virtex 1000 and VP20. We always use microblaze CPU, and > depending on the development board SDRAM or DDRAM controllers. > > Anyway, after the upgrade, the soc seems to be broken. Looks > like the UART output is somewhat garbled. I don't want to > debug the SoC again, just because I upgraded the tools. > > Does anybody know of any known gotchas ? We are using the > latest service packs for all the tools from the xilinx web > site. We really wanted to migrate to 6.3 as we would like to > support Virtex 4 as well. > > Any pointers/suggestions, appreciated. > > Best Regards, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and Synthesis > It doesn't surprise me. It seems everytime I've upgraded, something breaks, an IP goes to deprecated, goes obsolete, they find a new way to connect it. Sounds like your problem is more insideous. I've gone to the Memec sight, sometimes they have revisions to their reference designs that helps me figure out the new hard to find MHS syntax for different configurations. I've skipped the MicroBlaxe update cycle for EDK6.2, believing it was a waste of time since it would probably break when I upgraded to EDK6.3. Maybe it was the right decision. I looked at the below sight, and they have not posted an upgrade to EDK6.3i either. http://www.itee.uq.edu.au/~jwilliams/mblaze-uclinux/Downloads/platforms.html I realize the above is not much help, but I appreciate your frusteration. Good luck, -NewmanArticle: 76569
Arash Salarian wrote: (snip regarding ISA interface) > -Pulse Polarity: You should send a Positive voltage for the interrupt > -Pulse length: There is no minimum or maximum!! You should keep the IRQ high > till you recieve the acknowlege from the interrupt handler. But there is no > interrupt acknowlege line on ISA!? So in practice, you should use something > like a D flip-flop and connect the output to the IRQ line. When you reach > the interrupt routine, the software should write to a port to clear this > flip-flop using its asyc reset (or sync reset: the one that is simpler for > you). Now, you may ask how on earth would it be possible to share the same > interrupt line between different cards? but the answer would be a long > story.... I thought ISA was edge triggered, which is the reason it is hard to share IRQ lines. Newer ones are level triggered so that the request will stay after the first is serviced, and be processed later. -- glenArticle: 76570
Antti Lukats wrote: > > [lots of snipped] > > > Rick, hmmm... care to comment? > > > see synthesis and timing reports above :) > > > > This shows that my approach will run twice as fast. It produces two > > results rather than one and so can be constrained to require two clock > > periods. You need to set your timing constraints to reflect that. The > > only paths that don't run at the half clock rate are the output mux > > running into accfast and the phase control signal. Set the path delay > > on the accsingle and accdouble paths to be *two* clock periods (except > > for the enable from phase). > > :) ok, well your code "AS IS" did not synthesise so I tried mind guess an > fix to get it synthesize, posible making an error in the guess work. > YES, calculating 2 bits per clock is a solution, this is also what I > suggested in one of my earlier posts > > I presented the synthesis (and timing) of the code "as you wrote" it (after > fix) I dont see the output mux in your code, and I did not add it either > > generically I agree similar approuch (if code is correct) runs about twice > the speed The output mux is the two assignments to accfast, one when phase is '0' and the other when phase is '1'. I took another look at the code and I don't see anything that would not synthesize. What did the tool complain about? > > But your timing numbers show both designs running at over 200 MHz which > > is the OPs requirement, IIRC. Did you have to do any floorplanning? > > Also, are these numbers post ROUTE or the output from synthesis? Timing > > results from synthesis are worthless. I would like to see the details > > on the critical path in each case. > > I posted both synthesis estimate and post place and route timings, in any > case both approuch are 210MHz + > > No floorplanning, just set clock constraint to 5ns nothing more I only see one timing value for each example. What were the critical paths in each design? > > The logic for my code should be a minimum of 97 LUTs. Your result is > > only 34 slices which is a maximum of 68 LUTs. I suspect there is some > > problem so that the code does not synthesize correctly (possibly in the > > code). > > yes, possible i corrected your code incorrectly :( > > > I have not looked at the CLB details of the newer Xilinx FPGAs. An > > adder still requires 1 LUT per bit, right? inc_value is a signal and > > not a constant, right? > > I used all signal 32 bit wide, inc_value as input port That should work. Can you post the code you worked with? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76571
Hendra wrote: > Thomas Reinemann <thomas.reinemann@mb.uni-magdeburg.de> wrote > >>Classical approaches teach logic elements and logic minimation, but this is >>counterproductive. > Why does the academic community still teach methods that are not used > in the industry, such as K-Map? Why do we teach addition in first grade if everyone has hand calculators to do it? I do think it is still useful to know how to at least simple logic minimization by hand. (In case you are lost on a desert island with a pile of TTL chips.) It is useful to have at least some idea how much logic will be generated for different designs, or even if they are synthesizable at all. (FF's that trigger on both edges, for example.) In many cases I prefer HDL to GUI schematic entry tools. It just takes too much work moving around little rectangles and getting all the lines to go the right way. It is nice to have a tool that will generate a schematic from HDL, though. -- glenArticle: 76572
Jan De Ceuster a couché sur son écran : >>>> I am using an altera cyclone, and want to use the internall pll to >>>> divide by 10 a clock. >>>> The megawizard plug in manager (form quartusII 4.1 SP2) give the >>>> following error messages : >>>> "Cannot implement the requested pll, cause : post divider max count >>>> exceeded" >>>> but the divider counter should be 10, and it possible values are from 1 >>>> to 32. So what is the problem ? >>> >>> >>> What is your input frequency? >> >> >> My input frequency is 20 Mhz... and my output would be 2Mhz >> > > Read chapter 6 of the Cyclone manual. > > fout = fINx(M/(NxG0)) > and fVCO = fINx(M/N) > > now M can be from 2 to 32 and N and G0 from 1 to 32. fVCO must be between 300 > and 800 MHz. > since fIN is 20MHz M must be at least 15 when N = 1. Other option is M>=30 > and N=2. > > fOUT is desired to be 2MHz thus G0 must be 150 when M=15 or 300 when M = 30 > so this is not possible... > > If you want to divide 20MHz by 10 you'll need a counter to do that. Just > count from 4 to 0 and on 0 alternate the outputclock and start counting again > from 4. > > Hope this helps, > Jan thanks a lot, i am now less stupid than yesterday ... :D -- Ceci est une signature automatique de MesNews. Site : http://www.mesnews.netArticle: 76573
I have a PAL16V8 and I know I can program in verilog or vhdl... But what I need use for obtaining a programming_file and what circuit I need to use for programm the chip (I'm new in this domain...I used only fpga). Thanks,Article: 76574
"rickman" <spamgoeshere4@yahoo.com> wrote in message
news:41B49989.E7D9EFBC@yahoo.com...
> Antti Lukats wrote:
> >
> > [lots of snipped]
> > > > Rick, hmmm... care to comment?
> > > > see synthesis and timing reports above :)
> > >
[snip]
> > I used all signal 32 bit wide, inc_value as input port
>
> That should work. Can you post the code you worked with?
> --
> Rick "rickman" Collins
Rick you can try your own code with XST it complains about the sll at least!
Maybe there is better(read proper fix) to main
the timings I posted I always posted synthesis estimae and post P&R timings
news posting did change the text aligne so was hard to read
below is what I used (fast-do-not-think-at-all .. fixed) from your code
----------------------------------------------------------------------------
---
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dds is
Port ( clk : in std_logic;
rst : in std_logic;
inc_value : in std_logic_vector(31 downto 0);
fout : out std_logic);
end dds;
architecture Behavioral of dds is
signal accsingle : std_logic_vector(31 downto 0);
signal accdouble : std_logic_vector(31 downto 0);
signal accfast : std_logic_vector(31 downto 0);
signal phase : std_logic;
begin
process (clk, rst)
begin
if rst = '1' then
phase <= '0';
accsingle <= (others =>'0');
accdouble <= (others =>'0');
accfast <= (others =>'0');
elsif clk'event and clk ='1' then
phase <= not phase;
if (phase = '0') then
accfast <= accsingle;
else
accfast <= accdouble;
accsingle <= accdouble + inc_value;
accdouble <= accdouble + (inc_value(30 downto 0) & '0');
end if;
end if;
end process;
fout <= accfast (accfast'high);
end Behavioral;
------------------------------------------------------------------
below is DDSX in 2X mode there is no mux, 2 bits are calculated per clock
need external mux or serializer
------------------------------------------------------------------
//
// DDSX 2x Coyright 2004 OpenChip
//
// 2 DDS phase bits per single clock
// to be used with external (to this module) 2 bit
// deserializer running at 2X the clock of this module
//
`define DDSX_PHASE_WIDTH 32
`define DDSX_ACCU_WIDTH 32
`define DDSX_SERDES_WIDTH 2
module ddsx_2x(
clk,
rst,
load, // not used
phase, // phase increment
txdata, // output bits, need to be serialized at 2X clock
debug_next_accu // for simulation
);
input clk;
input rst;
input load;
input [`DDSX_PHASE_WIDTH-1:0] phase;
output [`DDSX_SERDES_WIDTH-1:0] txdata;
output [`DDSX_ACCU_WIDTH-1:0] debug_next_accu;
//
// Accumulator, on each clock advances 20 clocks !
//
reg [`DDSX_ACCU_WIDTH-1:0] accu;
//
// phase shifts for 2 steps
//
wire [`DDSX_PHASE_WIDTH :0] phase_2;
//
// Calc phase shifts for all steps
//
assign phase_2 = {phase[`DDSX_PHASE_WIDTH-1:0], 1'b0};
//
// Adder outputs
//
wire [`DDSX_ACCU_WIDTH-1:0] accu_p1;
wire [`DDSX_ACCU_WIDTH-1:0] accu_p2;
assign accu_p1 = accu + phase;
assign accu_p2 = accu + phase_2;
//
// Combine 2 next steps into one 2 bit word for high speed serdes
//
assign txdata[`DDSX_SERDES_WIDTH-1:0] = {
accu_p2 [`DDSX_ACCU_WIDTH-1],
accu_p1 [`DDSX_ACCU_WIDTH-1]};
//
// advance 2 clocks!
//
always @(posedge clk)
if (rst) accu <= `DDSX_ACCU_WIDTH'b0;
else accu <= accu_p2;
assign debug_next_accu = accu_p2;
endmodule
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