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I have seen a few low cost($100-$200) fpga boards with 400k Spartan 3's, but nothing with 1million gates yet. I would think with the supposedly low price of the Spartan 3 that such boards would have made an appearance by now. Does anyone know if such a board exists yet.Article: 76001
swamydp@yahoo.com (swamy) wrote in message >following error messages were generated by Modelsim 5.7G >SE PLUS. Any pointers would be helpful. > > # ** Error: (vsim-3043) system_init.v(9): Unresolved reference to > 'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_00. Where are your block rams instantiated? I've not been able to get things like this to work with LUT roms unless they were directly in the top-level module. If I put the instantiations in a sub-module, I get the same sort of error where it can't find the component the INIT is supposed to be associated with. This was actually only a synthesis (XST) problem for me, as the non-Xilinx simulator (iverilog) was able to match the defparam's with sub-module instantiated memories. So right now, I'm passing the index for a lookup table up to the top-level, and passing the result back down... It's ugly, though worth remembering that the whole thing gets squashed flat before synthesis anyway (my guess is the problem is that the names don't get adjusted properly during this flattening). ChrisArticle: 76002
"DB" <javaguy11111@gmail.com> wrote in message news:85472d99.0411220559.531d4b6b@posting.google.com... > I have seen a few low cost($100-$200) fpga boards with 400k Spartan > 3's, but nothing with 1million gates yet. I would think with the > supposedly low price of the Spartan 3 that such boards would have made > an appearance by now. Does anyone know if such a board exists yet. ASFAIK its coming up from xilinx/digilent (not 100% sure) I think some others have similar plans before that there are several XC3S1500 boards avail from avnet and memec AnttiArticle: 76003
You are unlikely to get a bus switch in anything other that surface mount. We use this technique on our Broaddown2 product and it works well. If you don't have to operate at high speed then you can consider using a series resistor but only if the Vcco of the Spartan-3 is guaranteed less than 3.3V. The input of the S3 should not go above 4.05V( from memory) and the protection diodes will present a rise over Vcco of about 0.7V. Going the other way from S3 to 8051 check the input voltage levels. they may be CMOS levels and if so might expect 4.0V (at worst) for a "high" input. You will not achieve 4.0V from S3 and pullup may be needed. The S3 will probably draw current from a pullup if connected to 5V so you will need to look at the ratio of pullup to series resistor values. If you are looking at small number of lines, at lowish speed, then you may be able to use something like back to back RS232 drivers to do a level shift. Or you could also use discrete mosfets. Bus switches are essentially mosfets. Slightly rusty on this area but I think we are talking n-channel with gate connected to Vcc. Cut off voltage depends on mosfet type. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Lawrence Kiss" <lkiss80@hotmail.com> wrote in message news:41a15113$1_1@127.0.0.1... > I would like to integrate an 8051 microcontroller to a spartan 3 development > board. For input port I know I need to add a series resistor. However for > the output ports, I have read posts and app notes about using the > quickswitch product. The only problem is the package that they come in. I > have been wire wrapping most of my pins thus far and have not found any > level shifting solutions that comes in a DIP package (that can be wire > wrapped). So here is my question: instead of using the level shifter, can > I just directly connect my Spartan 3 output port to an input port on my 8051 > and have a pull-up resistor to 5V on the same net? My idea is that for low > outputs I would just output a low logic level, but for a high output, I > would create the VHDL code to output a high impedance (Z)... Does anyone > think this will work, or am I just crazy? > > Thanks for any suggestions! > > Larry > > > > Posted Via Usenet.com Premium Usenet Newsgroup Services > ---------------------------------------------------------- > ** SPEED ** RETENTION ** COMPLETION ** ANONYMITY ** > ---------------------------------------------------------- > http://www.usenet.comArticle: 76004
Thanks for your feedbacks. From your emails and some test that I have done, I can conclude that due to the fact that the 18x18 multipliers are signed multipliers, some considerations have to be kept in mind to synthesize the 'right' number of multipliers. The following pairs of packages and types work as expected: use ieee.std_logic_signed.all; type signed use ieee.std_logic_signed.all; type std_logic_vector use ieee.numeric_std.all; type signed imlementing the multiplication of two 18 bits wide operands in just one 1 18x18 multiplier. However the following combinations use ieee.numeric_std.all; tpye unsigned use ieee.std_logic_unsigned.all; type std_logic_vector are implemented in 3 18x18 multipliers when the operands are 18 bits wide. crisArticle: 76005
Have a look at Broaddown2 we do that exactly that as do some of our compeditors. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "ksy" <helloone@kornet.net> wrote in message news:cnn1sl$9ff$1@news.hananet.net... > Hello All, > > Is it possible to use spartan3 for 5V PCI interface? > I seems that there is no problem to use for 3.3V PCI interface. > > Thanks in advance. > > > >Article: 76006
Maciejos wrote: > There is quartz generator 80MHz connected to GCLK input. It is driven by 5V > but I used the voltage divider (2 resistors) to connect it to xc3s50. Huh? You take an 80 MHz clock through a 2:1 resistive voltage divider? Have you looked at the signal on the Spartan GCLK pin? I would expect massive attenuation of the high frequency component due to the input pin's parasitic capacitance. If you really have to do this, you will almost certainly need a compensating capacitor on the series resistor to get the signal rise time within spec. An oscillator that will run on 2.5 V would be a much better choice. JonArticle: 76007
Trenz Electronic provides a nice, very small Spartan-3 module
and a carrier board with all the stuff to build a complete computer
with an FPGA. Not that cheap, but a complete solution:
http://www.trenz-electronic.de/prod/proden20.htm
Almost complete... You need a CPU. If you like Java you can now
use JOP on this board. Trenz provided a board for the porting of JOP
and here it is:
Download JOP from http://www.jopdesign.com/download.jsp
and follow these Steps:
* Compile the ISE project under ../xilinx/trenz
* Download JOP to the board
* Connect a serial cabel from the board to your PC
* Open a command prompt in ../java/target
* Change the COM-port in doit.bat
* type:
doit test test Clock
Now your first Java program runns on JOP/Spartan-3 Trenz board!
Martin
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/
Article: 76008"Jim Wu" <nospam@nospam.com> wrote in message news:<cnkuh6$qn02@cliff.xsj.xilinx.com>... > "Steven Sharp" <sharp@cadence.com> wrote in message > news:3a8e124e.0411181905.575b897e@posting.google.com... > > > Some simulators actually let you write a NUL byte > > out with %c, which avoids this nastiness. > > I know NCVerilog can do this, but not all simulators work this way. NC-Verilog didn't work this way originally either. We added this capability in response to user requests. Perhaps other simulator vendors would also be willong to do this if they got enough requests. In the meantime, the basic workaround you suggested should work.Article: 76009
Eric Crabill <eric.crabill@xilinx.com> wrote in message news:<419E423B.E41CDB7F@xilinx.com>... > > Are you saying that a more concise way to do > this would be with a relative seek? I don't > have a good reference for these system tasks, > the best I could come up with is what I put > above, based on reading some web material. What you came up with should work. It even has the advantage of being clearer in some ways, and doesn't rely on the implementation correctly following the LRM in writing out 32-bit chunks with %u. But a relative seek is more concise. The third argument to $fseek is 0 for a seek relative to the start of the file, 1 for a seek relative to the current position in the file, and 2 for a seek relative to the end of the file. This assumes that your simulator has implemented $fseek correctly, of course. > But this: > > > $fseek(fd, -3, 1) > > Seems much more concise... It's equivalent? Should be.Article: 76010
"Elmo" <ikeepthespiritalive@freenet.de> wrote in message news:cnsnbt$bp2$1@news.cs.tu-berlin.de... > Hello and thanks Allan! > > I just browsed through the recent thread. But let me pick up your question, > anyhow: Yes, I want to be able to write to individual bytes and precharge > one of the chips while I am performing a different operation on the other > chip, i.e. I want one DIMM to load some data into memory and the other one > to read data from the memory to any sort of interface. What are the aspects > I must consider in connecting the DIMMs??? Take GREAT care if parallelling them: You might end up with SI problems. (I'd opt for separate lines if you have the I/Os) And remember termination resistors/supply.... As well as matching delays. /AArticle: 76011
http://groups.google.com/groups?q=vhdl+modelsim+library+simprim+error
-- Mike Treseler
Article: 76012I created a custom opb component using the create peripheral wizard. Im using the IP2BUSxferAck to provide a 4 wait states for reads and writes. During reads, the CS pulse created by the OPB component is about extended as it should be. The problems is during writes... the CS pulse short as if NO wait states are beign added. Except for bringing out the required signals (address, ack, data), no changes where made to the vhdl file generated by the wizard. RichArticle: 76013
> AFAIK, IOs are pull-down/pull-down/None during configuration based on > configuration options, Mode pins and maybe hotswap-enable, default > is pull-down. I tried pulling the reset pin high. But that doesn't help in configuration mode. Perhaps if the pullup was on before the configuration?Article: 76014
Brad, The HSWAP_EN pin turns on all IO pullups prior to DONE, or leaves the IOs float. Austin Brad Smallridge wrote: >>AFAIK, IOs are pull-down/pull-down/None during configuration based on >>configuration options, Mode pins and maybe hotswap-enable, default >>is pull-down. > > > I tried pulling the reset pin high. But that doesn't help in configuration > mode. > Perhaps if the pullup was on before the configuration? > > >Article: 76015
Thanks for the reply Peter. My 8051 specifies a minimum high logiv level at .7*VCC = 3.5V. What is the gaurentee that the Spartan 3 will ever output a 3.3V signal? I would think that I need to pull up to VCC=5V not 3.3V. Larry "Peter Seng" <NOSPAM@seng.de> wrote: > >"Lawrence Kiss" <lkiss80@hotmail.com> schrieb im Newsbeitrag >news:41a15113$1_1@127.0.0.1... >> I would like to integrate an 8051 microcontroller to a spartan 3 >development >> board. For input port I know I need to add a series resistor. However >for >> the output ports, I have read posts and app notes about using the >> quickswitch product. The only problem is the package that they come in. >I >> have been wire wrapping most of my pins thus far and have not found any >> level shifting solutions that comes in a DIP package (that can be wire >> wrapped). So here is my question: instead of using the level shifter, >can >> I just directly connect my Spartan 3 output port to an input port on my >8051 >> and have a pull-up resistor to 5V on the same net? My idea is that for >low >> outputs I would just output a low logic level, but for a high output, I >> would create the VHDL code to output a high impedance (Z)... Does anyone >> think this will work, or am I just crazy? >> >> Thanks for any suggestions! >> >> Larry >> >> >> >> Posted Via Usenet.com Premium Usenet Newsgroup Services >> ---------------------------------------------------------- >> ** SPEED ** RETENTION ** COMPLETION ** ANONYMITY ** >> ---------------------------------------------------------- >> http://www.usenet.com > > > >Why not running the 8051 at 3V3 ??? >There are lot of 3V3 compatible 8051 MCU´s / CPU´s .... > > >with best regards, > >Peter Seng > > >############################# >SENG digitale Systeme GmbH >Im Bruckwasen 35 >D 73037 Goeppingen >Germany >tel +7161-75245 >fax +7161-72965 >eMail p.seng@seng.de >net http://www.seng.de >############################# > > ----== Posted via Newsfeed.Com - Unlimited-Uncensored-Secure Usenet News==---- http://www.newsfeed.com The #1 Newsgroup Service in the World! >100,000 Newsgroups ---= 19 East/West-Coast Specialized Servers - Total Privacy via Encryption =---Article: 76016
Richard, Are you inhibiting posted writes? From what you've described, it seems to me that the IPIF is configured for posted writes. There is a signal on the IPIC (IP2Bus_PostedWrInh) which inhibits posted writes, thereby requiring a full handshake transfer for writes. Matt Richad Klosinski wrote: > I created a custom opb component using the create peripheral wizard. > Im using the IP2BUSxferAck to provide a 4 wait states for reads and > writes. During reads, the CS pulse created by the OPB component is > about extended as it should be. The problems is during writes... the > CS pulse short as if NO wait states are beign added. Except for > bringing out the required signals (address, ack, data), no changes > where made to the vhdl file generated by the wizard. > > RichArticle: 76017
Lawrence Kiss wrote: > My 8051 specifies a minimum high logiv level at .7*VCC = 3.5V. What is the > gaurentee that the Spartan 3 will ever output a 3.3V signal? I would think > that I need to pull up to VCC=5V not 3.3V. Many processors have more strict Vih for clock and reset inputs, which can easily be 0.7Vcc, though that would be unusual for other inputs. Otherwise, if Vih-Vil is not too large you can use a diode or two, along with a pull up resistor, to shift the voltage up as appropriate. If there are protection diodes on the outputs of the Spartan, you won't be able to get them much higher than the output supply voltage. -- glenArticle: 76018
Hi Rich, The OPB slave template generated by Create Peripheral Wizard assumes posted write transactions by default. If you want to implement acknowledged write transactions, you'll need to assert the IP2Bus_PostedWrInh (posted write inhibit). See opb_ipif_v3_01_a datasheet for detail explaination. thanks, yong Richad Klosinski wrote: > I created a custom opb component using the create peripheral wizard. > Im using the IP2BUSxferAck to provide a 4 wait states for reads and > writes. During reads, the CS pulse created by the OPB component is > about extended as it should be. The problems is during writes... the > CS pulse short as if NO wait states are beign added. Except for > bringing out the required signals (address, ack, data), no changes > where made to the vhdl file generated by the wizard. > > RichArticle: 76019
Hello Chris The BRAMs are instantiated deep within some wrapper files produced by simgen in Xilinx EDK. I fixed the problem in my design by UNCHECKING the Mixed language simulator option in options->project options->HDL and Simulation of the EDK software. Somehow the Modelsim simulator is not able to override VHDL model parameters using defparam. I read on some website that defparam cannot be used to override VHDL generic variables. so defparams may not work for mixed language simulations. Unchecking results in simgen now generating all the files in verilog and defparams of system_conf module can override any parameter in the low level verilog design files. Also flattening the design removes hierarchial information, so you may have to run XST with the option of maintaining the hierarchy for structural simualtions but I could not figure out how to do that in Xilinx EDK. so for now I am running behavioural simulations. I hope the above helps. Swamy cs_posting@hotmail.com (Chris Stratton) wrote in message news:<ae2ff5ca.0411220634.54a1dd4d@posting.google.com>... > swamydp@yahoo.com (swamy) wrote in message > > >following error messages were generated by Modelsim 5.7G > >SE PLUS. Any pointers would be helpful. > > > > # ** Error: (vsim-3043) system_init.v(9): Unresolved reference to > > 'ramb16_s2_s2_0' in system.bram_block_0.bram_block_0.ramb16_s2_s2_0.INIT_00. > > Where are your block rams instantiated? > > I've not been able to get things like this to work with LUT roms > unless they were directly in the top-level module. If I put the > instantiations in a sub-module, I get the same sort of error where it > can't find the component the INIT is supposed to be associated with. > This was actually only a synthesis (XST) problem for me, as the > non-Xilinx simulator (iverilog) was able to match the defparam's with > sub-module instantiated memories. > > So right now, I'm passing the index for a lookup table up to the > top-level, and passing the result back down... It's ugly, though > worth remembering that the whole thing gets squashed flat before > synthesis anyway (my guess is the problem is that the names don't get > adjusted properly during this flattening). > > ChrisArticle: 76020
"Bob" <nimby1_notspamm_@earthlink.net> wrote in message news:<Gwcod.8180$pK6.1111@newsread2.news.atl.earthlink.net>... > Just use the series resistor to limit the 8051->S3 high-level current. > > In the S3->8051 direction, you don't need anything since LVTTL (3.3V supply) > has exactly the same logic thresholds as TTL (5V supply). That should work with most logic familiers - if he has to talk to 5v devices that really need a higher input voltage, he should be able to use widely available 74-whatever-xx DIP package buffers or inverters in a 3.3v volt-compatible logic family as stand-in level translators. Of course, why not simply move the "8051" into the FPGA?? ChrisArticle: 76021
What are the procedures for adding signals to the simulation? I have been going to the SIGNALS pane, and clicking on add to wave signals in design. Then, since that seems to give me everything, I start deleting most of them. Seems inefficient. Also what does region mean in add signal in region? I also tried to save dataset, but when I loaded the file back, nothing seemed to happen. Is this all suppose to be done with the wavedo files? b r a d @ a i v i s i o n . c o mArticle: 76022
http://groups.google.com/groups?q=modelsim+add+wave
-- Mike Treseler
Article: 76023In article <9e825b8b.0411220805.3b0ab84e@posting.google.com>, cristian <cas7406@yahoo.com> wrote: >Thanks for your feedbacks. >However the following combinations >use ieee.numeric_std.all; tpye unsigned >use ieee.std_logic_unsigned.all; type std_logic_vector > >are implemented in 3 18x18 multipliers when the operands are 18 bits >wide. I assume synthesis tools are smarter than I am about these things, but I'd have thought an 18x18 unsigned multiplier was a 17x17 unsigned multiplier, 35 AND gates, some wire and a three-input 35-bit-wide adder: (2^17a + b) (2^17c + d) = 2^34*a*c + 2^17*(ad+bc) + bd where a and c can only take on the value 0 and 1, so you can multiply by them using an AND gate. Though the DSP blocks on Xilinx chips seem to have some extra outputs and inputs beyond the multiplier alone, so it may be that cascading DSP blocks, using two of them as things much less complicated than multipliers, saves time if there are no resource constraints. Does the synthesis do something different if you instantiate N+1 18x18 unsigned multipliers on a chip with 3N hardware multipliers? TomArticle: 76024
mike_treseler wrote: > What happens if you ignore the startup block > and just modify the process template to > use that reset signal like this > > p: process (reset, clk) > begin > if reset = '1' then > dout <= (others => '0'); > elsif rising_edge(clk) then > if sync_reset = '1' then -- where needed > dout <= (others => '0'); > else > dout <= din; > end if; > end if; > end process; > > That ought to synth and route fine and even > sim the same as before. Err.. That's functionally correct, but how does it help to get Synplify to use the reset inputs for synchronous reset? Hamish -- Hamish Moffatt R&D Engineer Data Networks Division Agilent Technologies +61 3 9210 5782 (T210 5782) Tel
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