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Thanks, I am going to try integrating this into my
existing TIFF file writer and I'll let you know
how it works out for me. I really appreciate the
thought you put into it.
Eric
Jim Wu wrote:
>
> A typo, fn should have been defined as "reg [10*8:1] fn;".
>
> "Jim Wu" <nospam@nospam.com> wrote in message
> news:cngs9m$jq2@cliff.xsj.xilinx.com...
> > Try this (tested in mti 5.8e):
> >
> > module wr_bin ();
> >
> > reg [7:0] data;
> > reg [10*8:0] fn;
> > reg [7:0] seq;
> >
> > integer fd;
> > integer i, j;
> >
> > initial begin
> >
> > for (j = 0; j < 8; j = j + 1) begin
> > seq = 8'h30 + j;
> > fn = {"frame", seq, ".tif"};
> > fd = $fopen(fn, "wb");
> > for (i = 0; i < 256; i = i + 1) begin
> > data = i;
> >
> > if (data == 0) begin
> > $fwriteb(fd, "%u", data);
> > $fseek(fd, 1, 0);
> > end
> > else
> > $fwriteb(fd, "%c", data);
> > end
> >
> >
> > $fclose(fd);
> > end
> >
> > $display("Done");
> > $finish;
> > end
> >
> > HTH,
> > Jim
> > jimwu88NOOOSPAM@yahoo.com (remove capital letters)
> > http://www.geocities.com/jimwu88/chips
> >
> > "Eric Crabill" <eric.crabill@xilinx.com> wrote in message
> > news:419BDA61.4AF0BC09@xilinx.com...
> > >
> > > Dude, you rock!!! Since I'm using Modelsim at home
> > > for my hobby projects, this will work fantastic...
> > > Now I can write out TIFF files direct from Verilog.
> > >
> > > Let me ask another question, if you don't mind. Do
> > > you (or anyone reading) know if it's possible to
> > > open files with dynamic file names? By that, I
> > > mean instead of using the string "test.bin" in $fopen
> > > is there a way to form a string with a 2D reg and
> > > then pass that as the file name? I tried playing
> > > around with this, but the simulator I was using at
> > > the time did not like anything but actual strings...
> > >
> > > My desire is to have a loop, that writes each display
> > > frame to a separate file, with names like:
> > >
> > > frame01.tif
> > > frame02.tif
> > > frame03.tif
> > > frame04.tif
> > > and so on...
> > >
> > > Thanks, I appreciate your help,
> > > Eric
> > >
> > > Jim Wu wrote:
> > > >
> > > > > Hi,
> > > > >
> > > > > Well, let me know if you figure this one out. I had
> > > > > a similar issue -- I wanted a Verilog simulation to
> > > > > write out a TIFF file. I couldn't find a way to write
> > > > > out a binary file, so wrote out ASCII data values to
> > > > > text file and then post-processed it into a binary
> > > > > TIFF file using a small program I wrote in C.
> > > >
> > > > The attached code is kind of kludge, but it works, with modelsim 5.8e
> > > > anyway.
> > > >
> > > > HTH,
> > > > Jim
> > > > jimwu88NOOOSPAM@yahoo.com (remove capital letters)
> > > > http://www.geocities.com/jimwu88/chips
> > > >
> > > > module wr_bin ();
> > > >
> > > > reg [7:0] data;
> > > >
> > > > integer fd;
> > > > integer i;
> > > >
> > > > initial begin
> > > > fd = $fopen("test.bin", "wb");
> > > >
> > > > for (i = 0; i < 256; i = i + 1) begin
> > > > data = i;
> > > >
> > > > if (data == 0) begin
> > > > $fwriteb(fd, "%u", data);
> > > > $fseek(fd, 1, 0);
> > > > end
> > > > else
> > > > $fwriteb(fd, "%c", data);
> > > > end
> > > >
> > > > $fclose(fd);
> > > > $display("Done");
> > > > $finish;
> > > > end
> > > >
> > > > endmodule
> >
> >
Article: 75901
You're welcome.
I didn't try this myself, but theoretically it should work: if you need
"seq" to be more than 1 digit, you can try swrite* tasks.
Jim
"Eric Crabill" <eric.crabill@xilinx.com> wrote in message
news:419CE33E.503B4253@xilinx.com...
> Thanks, I am going to try integrating this into my
> existing TIFF file writer and I'll let you know
> how it works out for me. I really appreciate the
> thought you put into it.
>
> Eric
>
> Jim Wu wrote:
> >
> > A typo, fn should have been defined as "reg [10*8:1] fn;".
> >
> > "Jim Wu" <nospam@nospam.com> wrote in message
> > news:cngs9m$jq2@cliff.xsj.xilinx.com...
> > > Try this (tested in mti 5.8e):
> > >
> > > module wr_bin ();
> > >
> > > reg [7:0] data;
> > > reg [10*8:0] fn;
> > > reg [7:0] seq;
> > >
> > > integer fd;
> > > integer i, j;
> > >
> > > initial begin
> > >
> > > for (j = 0; j < 8; j = j + 1) begin
> > > seq = 8'h30 + j;
> > > fn = {"frame", seq, ".tif"};
> > > fd = $fopen(fn, "wb");
> > > for (i = 0; i < 256; i = i + 1) begin
> > > data = i;
> > >
> > > if (data == 0) begin
> > > $fwriteb(fd, "%u", data);
> > > $fseek(fd, 1, 0);
> > > end
> > > else
> > > $fwriteb(fd, "%c", data);
> > > end
> > >
> > >
> > > $fclose(fd);
> > > end
> > >
> > > $display("Done");
> > > $finish;
> > > end
> > >
> > > HTH,
> > > Jim
> > > jimwu88NOOOSPAM@yahoo.com (remove capital letters)
> > > http://www.geocities.com/jimwu88/chips
> > >
> > > "Eric Crabill" <eric.crabill@xilinx.com> wrote in message
> > > news:419BDA61.4AF0BC09@xilinx.com...
> > > >
> > > > Dude, you rock!!! Since I'm using Modelsim at home
> > > > for my hobby projects, this will work fantastic...
> > > > Now I can write out TIFF files direct from Verilog.
> > > >
> > > > Let me ask another question, if you don't mind. Do
> > > > you (or anyone reading) know if it's possible to
> > > > open files with dynamic file names? By that, I
> > > > mean instead of using the string "test.bin" in $fopen
> > > > is there a way to form a string with a 2D reg and
> > > > then pass that as the file name? I tried playing
> > > > around with this, but the simulator I was using at
> > > > the time did not like anything but actual strings...
> > > >
> > > > My desire is to have a loop, that writes each display
> > > > frame to a separate file, with names like:
> > > >
> > > > frame01.tif
> > > > frame02.tif
> > > > frame03.tif
> > > > frame04.tif
> > > > and so on...
> > > >
> > > > Thanks, I appreciate your help,
> > > > Eric
> > > >
> > > > Jim Wu wrote:
> > > > >
> > > > > > Hi,
> > > > > >
> > > > > > Well, let me know if you figure this one out. I had
> > > > > > a similar issue -- I wanted a Verilog simulation to
> > > > > > write out a TIFF file. I couldn't find a way to write
> > > > > > out a binary file, so wrote out ASCII data values to
> > > > > > text file and then post-processed it into a binary
> > > > > > TIFF file using a small program I wrote in C.
> > > > >
> > > > > The attached code is kind of kludge, but it works, with modelsim
5.8e
> > > > > anyway.
> > > > >
> > > > > HTH,
> > > > > Jim
> > > > > jimwu88NOOOSPAM@yahoo.com (remove capital letters)
> > > > > http://www.geocities.com/jimwu88/chips
> > > > >
> > > > > module wr_bin ();
> > > > >
> > > > > reg [7:0] data;
> > > > >
> > > > > integer fd;
> > > > > integer i;
> > > > >
> > > > > initial begin
> > > > > fd = $fopen("test.bin", "wb");
> > > > >
> > > > > for (i = 0; i < 256; i = i + 1) begin
> > > > > data = i;
> > > > >
> > > > > if (data == 0) begin
> > > > > $fwriteb(fd, "%u", data);
> > > > > $fseek(fd, 1, 0);
> > > > > end
> > > > > else
> > > > > $fwriteb(fd, "%c", data);
> > > > > end
> > > > >
> > > > > $fclose(fd);
> > > > > $display("Done");
> > > > > $finish;
> > > > > end
> > > > >
> > > > > endmodule
> > >
> > >
Article: 75902If I want the Linux version of BaseX, do I have to do something special when I order it? Or is there just a single product that includes both Windows and Linux versions? The online store doesn't seem to have any provision for specifying the platform. I'd hate to spend the money and wind up with a version I can't use. Thanks, Eric [If you want to reply by private email, please remove the obvious spam-proofing from my email address.]Article: 75903
Austin Lesea <austin@xilinx.com> writes: > Spartan 3 has clamp diodes that always prevent the voltage on the pin > from being more than a diode drop above Vcco (or below ground). > > So, if Vcco is 3.3V, and the diode drop is ~ 0.5V at the current thru > the 270 ohms, then the max V is 3.8V, well below the abs max limit of > 4.05V in the data sheet. > > But, take care, as if you have Vcco = 3.45V, then you are getting > uncomfortably close to the 4.05V abs max limit. If I want to drive a Spartan 3 input from 5V TTL (not CMOS), such as an SN74LS14, do I need a series resistor, and if so, what value? The data sheet gives a typical output voltage of 3.4V at -0.4 mA (which is the recommended maximum Ioh). They don't give a maximum Voh. Since it's bipolar, it's obviously less than the supply rail. I suppose I could size the series resistor as if it were a 5.5V CMOS output, but I'd prefer to use a lower value if it can be guaranteed not to exceed the maximum current of the S3 clamp diode. Thanks, EricArticle: 75904
Eric, I would run a spice or IBIS simualtion of the driver into an open. Then you would know. Austin Eric Smith wrote: > Austin Lesea <austin@xilinx.com> writes: > >>Spartan 3 has clamp diodes that always prevent the voltage on the pin >>from being more than a diode drop above Vcco (or below ground). >> >>So, if Vcco is 3.3V, and the diode drop is ~ 0.5V at the current thru >>the 270 ohms, then the max V is 3.8V, well below the abs max limit of >>4.05V in the data sheet. >> >>But, take care, as if you have Vcco = 3.45V, then you are getting >>uncomfortably close to the 4.05V abs max limit. > > > If I want to drive a Spartan 3 input from 5V TTL (not CMOS), such as > an SN74LS14, do I need a series resistor, and if so, what value? The > data sheet gives a typical output voltage of 3.4V at -0.4 mA (which is > the recommended maximum Ioh). They don't give a maximum Voh. Since > it's bipolar, it's obviously less than the supply rail. I suppose I > could size the series resistor as if it were a 5.5V CMOS output, but > I'd prefer to use a lower value if it can be guaranteed not to exceed > the maximum current of the S3 clamp diode. > > Thanks, > EricArticle: 75905
"Jac Athow" <jaxato@gmail.com> wrote in message news:7704390c.0411160025.3338ab0e@posting.google.com... > Im just beginning to read about Chipscope from Xilinx, and up to now, > Im impressed by the product, and how easy it is to use. But the > obvious question that comes to my mind is that... > > Is this doable; to extend the capture mem of ICON by connecting it > somehow to external async SRAM. For our purpose (~5MHZ clk), which is > slow by BRAM standard, it would be just a waste to spend all the bram > of my XCV300 on the ILA. I think it is actually feasible, > disconnecting the busses going to the BRAM, maybe using FPGA editor, > from the ICON core and reroute them to external ram, but without > proper documentation, this might take a while. > > Has anyone done something like that? the closest we have done are 1) connecting a custom VIO like core to ICON 2) connecting a custom core to ICON allowing the ICON to be used to download brams blocks 3) collecting data from ILA using custom Analyzer style application what you want todo, is not directly doable. ICON is basically a JTAG HUB, it allows up to 15 cores to be "inserted" into the JTAG chain (using the xilinx BSCAN primitive) the actual "work" is done inside the cores connected to ICON, in most of the cases the ILA core, in order to use external RAM you would need to write your own "ICON compatible" ILA core AnttiArticle: 75906
Mike Treseler wrote: > > Hamish Moffatt wrote: > > > Just over two years ago, Allan Herriman posted about having synchronous > > AND asynchronous resets in Xilinx FPGAs. > > http://groups.google.com/groups?hl=en&lr=&threadm=3dc210cc.14049401%40netnews.agilent.com&rnum=11&prev=/groups%3Fq%3Dsynchronous%2Breset%2Bstartup%2Bgroup:comp.arch.fpga%26hl%3Den%26lr%3D%26start%3D10%26sa%3DN > > > > > So, has anyone found any new workarounds since then? > > I still like Alan Fitch's recomendation in the thread above. > Don't use the gsr. > > A real reset signal allows for clean, portable code > for synthesis and simulation. What exactly is a "real" reset signal? There are times when you *need* an async reset, such as handling a failed clock situation or making sure a circuit is put into a known good state with a minimum delay (for safety or to prevent damage to equipment) when you are running with a slow clock. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 75907
On Thu, 18 Nov 2004 11:05:45 -0800, Eric Smith wrote: > Austin Lesea <austin@xilinx.com> writes: >> Spartan 3 has clamp diodes that always prevent the voltage on the pin >> from being more than a diode drop above Vcco (or below ground). >> >> So, if Vcco is 3.3V, and the diode drop is ~ 0.5V at the current thru >> the 270 ohms, then the max V is 3.8V, well below the abs max limit of >> 4.05V in the data sheet. >> >> But, take care, as if you have Vcco = 3.45V, then you are getting >> uncomfortably close to the 4.05V abs max limit. > > If I want to drive a Spartan 3 input from 5V TTL (not CMOS), such as > an SN74LS14, do I need a series resistor, and if so, what value? The > data sheet gives a typical output voltage of 3.4V at -0.4 mA (which is > the recommended maximum Ioh). They don't give a maximum Voh. Since > it's bipolar, it's obviously less than the supply rail. I suppose I > could size the series resistor as if it were a 5.5V CMOS output, but > I'd prefer to use a lower value if it can be guaranteed not to exceed > the maximum current of the S3 clamp diode. > > Thanks, > Eric Is 74LS still available? Why would you use it and who still makes it?Article: 75908
I picked up and installed my USB Blaster cable today and was looking forward to working through a NIOSII tutorial and communicating proprely with the eval board. However when I'd installed the cable and tried to run through one fo the tutorials I got the following error... make: *** [do_delete_placeholder_warning] Error 1 After some messing about I got a report saying that I had more than one cygwin1.dll on my machine and that I should delete all but the latest. I did this and now compiling I get make: *** [do_delete_placeholder_warning] Error 255 I get this error for all the tutorial designs/applications. Has anyone else sen anything like this, and can anyone suggest how to fix this? I've spent the night looking at it and am about to start pulling hair out. Tonight is the first time I've seen this problem, and I have re-booted since installing the USB Blaster. OP is win2K. Thanks in advance for any help, Nial ------------------------------------------------ Nial Stewart Developments Ltd FPGA and High Speed Digital Design Cyclone Based 'Easy PCI' proto board www.nialstewartdevelopments.co.ukArticle: 75909
Eric Smith wrote: > Austin Lesea <austin@xilinx.com> writes: > >>Spartan 3 has clamp diodes that always prevent the voltage on the pin >>from being more than a diode drop above Vcco (or below ground). >> >>So, if Vcco is 3.3V, and the diode drop is ~ 0.5V at the current thru >>the 270 ohms, then the max V is 3.8V, well below the abs max limit of >>4.05V in the data sheet. >> >>But, take care, as if you have Vcco = 3.45V, then you are getting >>uncomfortably close to the 4.05V abs max limit. > > > If I want to drive a Spartan 3 input from 5V TTL (not CMOS), such as > an SN74LS14, do I need a series resistor, and if so, what value? The > data sheet gives a typical output voltage of 3.4V at -0.4 mA (which is > the recommended maximum Ioh). They don't give a maximum Voh. Since > it's bipolar, it's obviously less than the supply rail. I suppose I > could size the series resistor as if it were a 5.5V CMOS output, but > I'd prefer to use a lower value if it can be guaranteed not to exceed > the maximum current of the S3 clamp diode. In theory, you are probably OK electrically. In practice you need to watch the production to make sure no one does a 'Heck, 74LVC14 (etc) are the same as 74LS14', replacement :), plus LS14 have to be getting near EOL.... -jgArticle: 75910
Laurent Gauch <laurent.gauch@DELETEALLCAPSamontec.com> writes: > Could you please tell me how works the interface with Impact and > Quartus? Through SVF. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 75911
A: Jeopardy. Q: What is my favorite quiz show? -- Greg readgc.invalid@hotmail.com.invalid (Remove the '.invalid' twice to send Email) - -- > A: Because it messes up the order in which people normally read text. > Q: Why is top-posting such a bad thing? > A: Top-posting. > Q: What is the most annoying thing on usenet and in e-mail?Article: 75912
Hi, I would like to run my program (too big) from external memory. I don't know how to configure my project in Xilinx Platform Studio to complie it correctly. What parameter should I modify or is there any configureation file I should creat? Any suggestion or help is greatly appreiciated! Thanks YongjieArticle: 75913
Hamish Moffatt wrote: > > So, has anyone found any new workarounds since then? > I helped someone chase down that same problem with the then-current Synplify (7.x???) about a year ago; IIRC, the closest thing to a workaround was to delete the async portion of the "IF" and use an initialized signal instead. This generated more compact hardware that synthesizes and simulates identically, but lacks an explicit async reset signal to tug during sim. I don't have Synplify at hand to confirm this, so my recall may be a bit fuzzy. BTW, XST also supports using initialized signals to specify post-config register states. > >One known solution for synth is instantiating the FDRs >manually, but then you don't get async resets in simulation. > That hardcoded internal-to-the-model-with-no-outside-control initialization in the UNISIM library has always baffled me; occasionally enough so to hack up the primitive models that I'm using to add a proper GSR input instead. ( Also, if you look closely at the Synplify RTL viewer for the version of your code with the STARTUP block, I believe you'll see that Synplify uses its' own special post-synth simulation models of the FFs which include a GSR input ) BrianArticle: 75914
"Jim Wu" <nospam@nospam.com> wrote in message news:<cngkbn$4m1@cliff.xsj.xilinx.com>... > > if (data == 0) begin > $fwriteb(fd, "%u", data); > $fseek(fd, 1, 0); > end > else > $fwriteb(fd, "%c", data); Shouldn't that be $fseek(fd, -3, 1), to seek backwards 3 bytes from the current position to compensate for having written a 4-byte binary word instead of 1 byte? With $fseek(fd, 1, 0), you are seeking to the second byte in the file, which is only correct if you were at the start of the file when you wrote the NUL byte. Some simulators actually let you write a NUL byte out with %c, which avoids this nastiness.Article: 75915
Brian Davis wrote:
> Hamish Moffatt wrote:
>>So, has anyone found any new workarounds since then?
> I helped someone chase down that same problem with the
> then-current Synplify (7.x???) about a year ago; IIRC,
> the closest thing to a workaround was to delete the async
> portion of the "IF" and use an initialized signal instead.
>
> This generated more compact hardware that synthesizes and
> simulates identically, but lacks an explicit async reset
> signal to tug during sim.
>
> I don't have Synplify at hand to confirm this, so my recall
> may be a bit fuzzy. BTW, XST also supports using initialized
> signals to specify post-config register states.
Do you mean initialised as in
signal x: std_logic_vector(7 downto 0) := (others => '1');
or
attribute INIT of x: signal is "00000000";
I tried the former and couldn't see any sign of Synplify using the
initial value.
signal sa_int: std_logic_vector(7 downto 0) := (others => '1');
p2a: process (clk)
begin
if rising_edge(clk) then
sa_int <= din;
end if;
end process;
So I've found that leaving the async reset input disconnected at synth
time (except to the STARTUP block) definitely helps with sync resets,
but for anything without sync resets, initial values are lost.
You could argue that anything that depends on a preset value should have
sync resets anyway, but that's not something I can change quickly in a
few hundred thousand lines of code...
thanks
Hamish
--
Hamish Moffatt
R&D Engineer
Data Networks Division
Agilent Technologies
+61 3 9210 5782 (T210 5782) Tel
Article: 75916Mike Treseler wrote: > Hamish Moffatt wrote: > >> Just over two years ago, Allan Herriman posted about having >> synchronous AND asynchronous resets in Xilinx FPGAs. >> http://groups.google.com/groups?hl=en&lr=&threadm=3dc210cc.14049401%40netnews.agilent.com&rnum=11&prev=/groups%3Fq%3Dsynchronous%2Breset%2Bstartup%2Bgroup:comp.arch.fpga%26hl%3Den%26lr%3D%26start%3D10%26sa%3DN > > > >> >> So, has anyone found any new workarounds since then? > > > I still like Alan Fitch's recomendation in the thread above. > Don't use the gsr. > > A real reset signal allows for clean, portable code > for synthesis and simulation. True, but that isn't an easy thing to change when you have a huge library of existing code. I'm only asking for the synthesis tool to produce an optimal and correct result! Hamish -- Hamish Moffatt R&D Engineer Data Networks Division Agilent Technologies +61 3 9210 5782 (T210 5782) TelArticle: 75917
rickman wrote:
> What exactly is a "real" reset signal?
One that comes in on a device pin.
> There are times when you *need*
> an async reset, such as handling a failed clock situation or making sure
> a circuit is put into a known good state with a minimum delay (for
> safety or to prevent damage to equipment) when you are running with a
> slow clock.
I agree.
-- Mike Treseler
Article: 75918Hi guy, you know nucleus RTOS? how much money? i wold like load on microblaze softprocessor....you that what you say? thanks bssArticle: 75919
Petter Gustad <newsmailcomp6@gustad.com> wrote: : tony.p.lee@gmail.com (T Lee) writes: : > How about creating a ethernet to jtag cable replacement? : I've made my own Ethernet based programmer. Works on virtually any OS : and does not require a device driver. Also works with Xilinx Impact : and Altera Quartus. Any chance to see the design or maybe buy units? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 75920
"Yongjie Liu" <yongjie@home.net> wrote in message news:20041118192043.7531.YONGJIE@home.net... > Hi, > > I would like to run my program (too big) from external memory. I don't > know how to configure my project in Xilinx Platform Studio to complie it > correctly. What parameter should I modify or is there any configureation > file I should creat? 1 you need to modify (or create new) the linker script! good luck with that! for one who is not writing C programs all the day this may be quite a pain there are some example linker scripts I think, but you end up modifying them anyway 2 you need some means of loading the program into the external memory, this maybe even more complex than setting up the linker script during debug you can load the ext memory with XMD, but for standalone operation some boot option is needed, that is you need to copy the program from some nonvolatile media into the external memory, again for this also some examples exist, but they need to modified for your purpose the steps 1, 2 above can easily take 2 man-weeks of time. Ok I agree, getting program into extram and loading running from XMD can be achived in few hours, a production quality bootloader solution can take up to 2 weeks easily. in EDK dir there are some example scripts, also some reference desings include linker scripts, be aware that the linker scripts for microblaze and powerpc are quite different! the minimal you need todo is to define one big chunk for extmem in linker script, and possible adjust the program start address AnttiArticle: 75921
"T. Irmen" <tirmen@gmx.net> wrote in message news:cnb98v$u6u$1@online.de... > Hi, > > I´m asking me if the REFCLK has a closer relationship to the recovered clock > than mentioned in the user guide. > > Could this be possible: Using a fixed osc. with a frequ. of 100MHz as > REFCLK. Receiving data with a variable datarate? > > TXCLK= 50..100MHz (TX) ----- fiber ------> RXRECCLK = (50..100MHz), > REFCLK=100MHz > > Does the recovered clock has phase jumps, nice duty cycle etc - in other > words: is it possible to use that clock as an input clock for an external > clock synthesizer? one word: NO the initial CDR lock range is +-100ppm as per RocketIO/X datasheet if you need to recover data with variable bit rate this maybe doable using rocketIO in raw serdes mode and doing oversampling. you need to sample about 4-5 times per data bit and you need custom data recovery circuitry. Some xilinx application use that technology. For your application I guess its not suitable. AnttiArticle: 75922
"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:419d18e4$0$1061$db0fefd9@news.zen.co.uk... > I picked up and installed my USB Blaster cable today > and was looking forward to working through a NIOSII > tutorial and communicating proprely with the eval board. > > However when I'd installed the cable and tried to run > through one fo the tutorials I got the following error... > I had more than one cygwin1.dll on my machine and that > I should delete all but the latest. I did this and now the cygwin compatibility DLL is one major incompatibility issue :( lots of tools install cygwin somewhere, then you get new tools that require newer version, and maybe install the new one, and then you are doomed. its the best to get latest cygwin and keep it in c:\cygwin\ but.. some tools may need to use some special version of cygwin and may not like the newer one, in that case you need to hide the new version as you complaints otherwise. Deleting the cygwin1.dll from the tool folder(s) and trying to use the cygwin1.dll from c:\cygwin\ sometimes does not work -- sometimes I think its faster easier and cheaper to buy a fresh new PC for every FPGA toolchain. Get new PC install one application and use it for that applicaton. an old windows installation gets some so garbaged with different dll releases different drivers for security dongles. etc, a possible nightmare unfortunatly I dont know the quick answer for your problem, so the painful path possible, reinstall everything try again, if no help get temporary new empty PC/windows install there, verify it works there then try to duplicate the install on the workstation AnttiArticle: 75923
Antti Lukats wrote:
> but.. some tools may need to use some special version of cygwin and may not
> like the newer one, in that case you need to hide the new version as you
> complaints otherwise. Deleting the cygwin1.dll from the tool folder(s) and
> trying to use the cygwin1.dll from c:\cygwin\ sometimes does not work
>
> -- sometimes I think its faster easier and cheaper to buy a fresh new PC for
> every FPGA toolchain. Get new PC install one application and use it for that
> applicaton.
>
> an old windows installation gets some so garbaged with different dll
> releases different drivers for security dongles. etc, a possible nightmare
Shared/duplicated .dlls are a weak point for a windows host.
Sometimes I think it may be faster easier and cheaper to bite
the bullet and try Altera's linux host software.
-- Mike Treseler
Article: 75924"Nial Stewart" <nial@nialstewartdevelopments.co.uk> wrote in message news:<419d18e4$0$1061$db0fefd9@news.zen.co.uk>... > I picked up and installed my USB Blaster cable today > and was looking forward to working through a NIOSII > tutorial and communicating proprely with the eval board. > > However when I'd installed the cable and tried to run > through one fo the tutorials I got the following error... > > make: *** [do_delete_placeholder_warning] Error 1 > > After some messing about I got a report saying that > I had more than one cygwin1.dll on my machine and that > I should delete all but the latest. I did this and now > compiling I get > > make: *** [do_delete_placeholder_warning] Error 255 > > I get this error for all the tutorial designs/applications. > > > Has anyone else sen anything like this, and can anyone > suggest how to fix this? I've spent the night looking at > it and am about to start pulling hair out. > > Tonight is the first time I've seen this problem, and I > have re-booted since installing the USB Blaster. OP is > win2K. > > > Thanks in advance for any help, > > Nial > > > ------------------------------------------------ > Nial Stewart Developments Ltd > FPGA and High Speed Digital Design > Cyclone Based 'Easy PCI' proto board > www.nialstewartdevelopments.co.uk Did you try the NIOS forum? www.niosforum.com Rgds André
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