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"woko" <wkopp@gmx.net> wrote in message news:6502961c.0411250001.5038423c@posting.google.com... > Hello! > > I want to revitalise a question at was asked in 2001, because I hope > something changed during the time. > > How can a AT49LV001 flash by programmed through a XC9536XL CPLD and > its JTAG-connector with really low cost? > > All address, data and control pins are connected to the CPLD, so ISP > via JTAG should be possible.I'm sure there are lots of tools available > at this time for programming, but still I don't want to pay >10k USD. > > Does anyone know if it's possible to program at flash with JAMPLAYER > sw from altera? How much effort would it be to implement flash > algorithms? how much would you be ready to pay? there is/was some example JAM application from some russian site, not sure if the site is online any more. it contained some flash functions. I have not tested them though. writing an JAM app is one choice, doing it from scratch isnt very complicated either. I have an Win32 application that programs an AMD flash that is connected to 2 different PLDs and part of the pins to Altera PLD that is not in jtag chain, so in order to program the flash I load the altera fpga (simple 1 wire from pld to flash bridge) then use JTAG scan to program the flash. the application is in Delphi6, source code could relativly easy to adopted for board. AnttiArticle: 76126
Comments inserted inline... seannstifler69@hotmail.com (Stifler) wrote in message news:<bf780a06.0411221720.4284a56f@posting.google.com>... > I would not even consider using a high-speed I/O part unless I see it > working for real on a board. And with some characterization data to > back it up. That's because engineers have been burned too many times > for claims of serial I/O greatness only to be left without working > silicon when it comes times for the rubber to hit the road. Which is why I made the pinch of salt comment > > Who cares about seeing info under NDA? 6.25 Gbps and above I/O is too > critical to count on some powerpoint presentation that claims great > I/O performance. Agreed 100% -- at the point when a hardware decision has to be made. > > You can get a Xilinx V2 Pro X today and verify for yourself if it > meets your needs in the lab. Real silicon operating at 10 Gbps on a > real board. Case closed with no decision for me unless I can see a > Stratix II running on a real board. Or Stratix II GX (which doesn't exist yet). Xilinx undoubtedly have a technology lead now as far as CDR is concerned, so Altera will have to improve theirs. Very few applications need (or can cope with) 10Gb/s now (and using these rates in practice is not trivial) but many need 3Gb/s, so you could say that Xilinx are ahead of the CDR market and Altera are in line with with the market. If Altera have a faster solution by the time it's generally needed that's fine, if not they'll be in trouble -- so I'm pretty sure it will happen. > > With Xilinx you don't even need to have all the great equipment > yourself. You can go to a rocket lab and see for yourself. > > Also, I would much prefer to run a 10 Gbps device at 6.25 than a 6.25 > Gbps device at 6.25 Gbps. I'll take all the extra margin any day. > Given a free choice *and all other things being equal*, I'd agree. But... Are you seriously suggesting that I go to a happy all-Altera customer and tell them that they'll have to switch over to Xilinx if they want to use our technology? I can tell you what the outcome would be, and it wouldn't involve Xilinx...:-) Ian > > Ian & Hilda Dedic <news.nospam@dedics.co.uk> wrote in message news:<3099tbF2te2tsU1@uni-berlin.de>... > > Hi Austin > > > > Obviously there is more margin if you're not pushing the transceiver so > > hard, and being in the IC business I always take "real-soon-now" with a > > large pinch of salt. > > > > But in the timescales we're looking at it seems that there will be > > solutions from both the biggest FPGA vendors, which always helps when > > talking to customers who might exclusively use one or the other...:-) > > > > Cheers > > > > IanArticle: 76127
Grégory Mermoud wrote: > Hi all! > > I wonder if I can use LUT to control LI, LT, RI and RT in Xilinx Bus > Macro for partial reconfiguration. I use Spartan2 and ISE6.3.01i SP2. > Has someone ever experienced any problems by using this method ? > > Grégory Definitely no. I try to control LI, LT, RI and RT from FPGA pads and it works well now. GrégoryArticle: 76128
"Fred" <Fred@nospam.com> wrote in message news:<41a49114$0$1067$db0fefd9@news.zen.co.uk>... > I see that Micron SDRAMs are claimed to support Concurrent auto precharge. > Is this a common feature amongst SDRAMs? > > I'm using a sample of a ICSI SDRAM at present and this feature isn't > mentioned in the data sheet. Is it safe for me to presume it doesn't > support Concurrent auto precharge? > > I am trying to write and read blocks of 4 words and don't really want to > extend the buffering to accommodate an 8 word burst! Hi, do you mean that you want to precharge for example bank A while still accessing bank B ? Rgds AndréArticle: 76129
"Ted Lechman" <eastwood132@yahoo.com> schreef in bericht news:b89924f9.0411241040.21037060@posting.google.com... > Does anyone know of any MIL-Qualified RTOS to run on uBlaze or Nios2? > I normally work with uCLinux, but in this case the MIL > contractor/customer needs something that has gone through a MIL > qualification process to pry them away from single-board x86 > computers. > > Does anyone have any experience in this?? > > Thanks I know uCOS-II is DO-178B certified, but this is for avionics. It also complies to most rules of MISRA. See www.micrium.com JeroenArticle: 76130
Hello! I have made a Ethernet board with CS8900 chip for Cyclone NIOS Development Kit and it works very strange. I have written code using HAL and programed flash. When I restarted board (pushed the button "power reset") and code from flash loaded to FPGA it doesn't work, but when I using SignalTap II Logic Analyzer and programed chip from there it works. Maybe somebody knows what it is the problem? Thank you.Article: 76131
It really depends heavily on your implementation and what you include in the
controller. It can be really small if you are clever about how it is
implemented. I've done LCD and CRT controllers in devices as small as the old
Xilinx 2064, which had only 64 CLBs, no carry chains and no internal memory
(used a static RAM outside the device). If you want to support more complicated
features such as multi-display support, color, graphics support etc, it can
quickly run into a much much bigger device. You needn't do the whole design
before estimating the gates, but you do have to go far enough that you have the
design partitioned into small enough blocks that you can count the registers and
fan in (through logic) to each register. From there, you can get a fairly
accurate resource count. Keep in mind that if your pixel rate is low enough,
you can take advantage of a higher than pixel rate clock by time sharing some of
the hardware to reduce the area.
Mouarf wrote:
> hello all,
>
> For a hobbyist purpose, I want to drive an LCD display (320x240) with a CPLD
> or FPGA in a standalone device (weather station). I've already played with
> FPGA and VHDL for some projects but I was never involved in the hardware
> part of such projects.
>
> The CPLD would have to read data (bitmap picture) from a dual port RAM and
> write it to the 4 bit data input of the LCD controller (+control lines,
> clock...). On the other side of the RAM, a microcontroller will update
> sometimes the content of the picture to be displayed.
>
> I would like to know how to estimate the number of gate needed for the
> project in order to buy the cheapest CPLD that fits the number of gate.
>
> Do I need first to design the VHDL part and synthetize to know the number of
> gate and then choose the CPLD?
>
> I do not really understand the difference between CPLD and FPGA and what is
> better for me.
>
> For a CPLD, the configuration is non volatile and in the FPGA it is
> volatile so a reconfiguration is needed on each start (via configuration
> EEPROM or JTAG programming) but the FPGA is much more powerfull. Correct?
>
> Is a CPLD enough for my project? I'm turning around Xilinx XC9536 which
> seems to be very often used nowadays, is it a good choice for this project?
>
> Many thanks by advance.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 76132On Thu, 25 Nov 2004 13:05:14 +0100, Mouarf wrote: > hello all, > > For a hobbyist purpose, I want to drive an LCD display (320x240) with a CPLD > or FPGA in a standalone device (weather station). I've already played with > FPGA and VHDL for some projects but I was never involved in the hardware > part of such projects. > > The CPLD would have to read data (bitmap picture) from a dual port RAM and > write it to the 4 bit data input of the LCD controller (+control lines, > clock...). On the other side of the RAM, a microcontroller will update > sometimes the content of the picture to be displayed. > > I would like to know how to estimate the number of gate needed for the > project in order to buy the cheapest CPLD that fits the number of gate. > > Do I need first to design the VHDL part and synthetize to know the number of > gate and then choose the CPLD? > > I do not really understand the difference between CPLD and FPGA and what is > better for me. > > For a CPLD, the configuration is non volatile and in the FPGA it is > volatile so a reconfiguration is needed on each start (via configuration > EEPROM or JTAG programming) but the FPGA is much more powerfull. Correct? > > Is a CPLD enough for my project? I'm turning around Xilinx XC9536 which > seems to be very often used nowadays, is it a good choice for this project? > > > Many thanks by advance. Since this a learning experience for you I'd suggest that you design, simulate and synthesize it before you attempt to build any hardware. The best way to get a feel for what a logic family is capable of is to try a number of designs. After a while you'll be able to look at a project and know what the right device is.Article: 76133
Hello,
Do you guys know about any open-source 386 compliant IP Core ? I've
heared that there are some patents pending on 386 and it is illegall to
produce 386 clones : > I'm an confused - is it a hoax or not ? If not - why
there are no open-source 386 IP Cores available ?
greetings!
Marcin Olak
Article: 76134In article <fc23bdfc.0411250242.2446ba92@posting.google.com>, Nahum Barnea <nahum_barnea@yahoo.com> wrote: >The problem is that the pullup is very slow (300 ns) and the host interrupt >service routine is accessed again for nothing. As someone who has worked on a lot of device drivers I can't say I've ever seen a card that consistently produces double interrupts. I haven't gone and measured INTx rise times either. The result seems plausible, though. Figure an ~8.2k pullup (that's Rtyp for pullups in the PCI 2.1 spec, don't have X handy), 3 slots (at about 5p each) each with a card (allowed 10p each) gives you 45p*8.2k is ~350ns. OTOH, I've never seen a motherboard that was high-end enough to have PCI-X 66 that didn't also use an IO APIC that allowed each INTx pin to be routed individually, though. -- Ben Jackson <ben@ben.com> http://www.ben.com/Article: 76135
Marcin Olak wrote: > Hello, > > Do you guys know about any open-source 386 compliant IP Core ? I've > heared that there are some patents pending on 386 and it is illegall to > produce 386 clones : > I'm an confused - is it a hoax or not ? If not - > why there are no open-source 386 IP Cores available ? Maybe the reason is that a 386 is much more complicated than an 8086. vax, 9000 > > greetings! > Marcin OlakArticle: 76136
Paul, Thanks for the reply. I disagree with pretty much everything you say, but you are cvertainly entitled to offer a defense. Thanks for admitting that you did not compare similar speed grade parts. Austin Paul Leventis (at home) wrote: > Hi Austin, > > I believe Dave has addressed the overall question on benchmarking > methodology. I'd like to address a few specific benchmarking questions in > your posting (which I believe are addressed in the links David provided). > > >>What speed grades were compared (e.g. their fastest with our mid-grade)? > > > We always produce at a comparison of the fastest speed grades available in > the software, and we will sometimes publish other comparisons with explicit > indications of speed grade. Our philosophy is that if a speed grade is not > in software, users can't design to it, and thus it is not real. When a new > speed grade becomes available (from either vendor), we re-measure our > benchmarks. > > Note that sometimes speed grades appear in the software that are > difficult/impossible to actually get from the vendor. We do not factor this > into our benchmarking results. This is can be an advantage for competitors, > since we haven't had a speed grade availability issue that I know of. > > >>What were the settings of the synthesis tools (e.g. their default vs our >>default -- we default for speed of synthesis, theirs for a compromise of >>performance)? > > > We do apples to apples comparisons. We usually use a 3rd party synthesis > tool, same version, same settings for both chips. If we are trying to > compare architecture speeds, we push synthesis for speed (for both > architectures). > > We also sometimes publish results using the available integrated sythesis. > This is particularly relevant in the low-cost market where CAD tool costs > can be a factor. If we are comparing architectural speed, we select the > settings (for both tools) that yield the best speed results. We do not > cripple either tool, and we go as far as running many experiments to try to > determine the best settings for our competitors' tools. > > >>What effort was made to use device specific features (e.g. theirs a lot, >>ours a little)? > > > We make a fairly signficant effort. We do not go as far as rearchitecting > the design to be specifically optimised for a chip. We try to standardize > the HDL between the target architectures, with exception of "cores" such as > explicitly instantiated memories, multiplier/accumulator blocks, PLL/DCMs, > etc. > > Does this mean for a given design we've extracted the most we can? I'd say > no, since that would require an enormous engineering effort on (typically) > poorly documented designs (all we get is the HDL, and sometimes it's been > anonymized). But our benchmark set comprises designs that were originally > targeted to our chips of current and past generations, competitors chips, > ASICs, vanilla HDL, etc, so there will probably be headroom left in both > architectures under comparison. > > >>What choice of device was made (e.g. their only one choice, versus our >>three options to best fit: LX for logic, SX for DSP, and FX for networking >>and comms)? > > > We select the smallest device that fits the design, since we believe that > our customers would likely do so as well. The whole Virtex-4 alphabet soup > issue is new. But since only LX is available, its moot for now -- no point > comparing to a family that is not available. > > As for FX, that's a non-issue as we're talking about core fabric > performance. Stratix GX and your FX parts offer additional hard IP that > will factor into some customer's decisions, and probably in a way that no > amount of benchmarking will be able to quantify. > > >>The "speed superiority" claims appeared three days after we announced the >>availability of three V4 parts as engineering samples.....compared to >>their unavailability. Hey it ain't fun when your foundry can't supply the >>parts to you, is it? > > > I'm not quite sure which three days you are referring to, but the primary > reason for the timing of our release was availablity of ISE support for > Virtex-4. We can't benchmark against a chip that doesn't exist in the > software. If we knew we had a 39% performance advantage earlier, do you > think we would have sat on it? > > I'm not sure what its like when a foundry can't supply us parts Austin, so I > can't feel your pain. Sorry. We have one fabulous fab partner in TSMC, and > it's the only one we need. > > Regards, > > Paul Leventis > Altera Corp. > >Article: 76137
Ian, Most customers are not stupid: if they see their competition using Xilinx, and beating them, they are unlikely to remain so fixated on a particular vendor. I understand that there are Altera customers who are so committed, that they will not consider any other solution. The oppsoite is true, as well. I don't think we need to discuss it here. More intersting are folks who want the best features, performance, support, software, cores, and tools. And are willing to examine all vendors. Those are the ones I want to reach. By the way, there are customers who believe that in order to keep both vendors alive, they have to intentionally switch every so often. Austin Ian Dedic wrote: > Comments inserted inline... > > seannstifler69@hotmail.com (Stifler) wrote in message news:<bf780a06.0411221720.4284a56f@posting.google.com>... > >>I would not even consider using a high-speed I/O part unless I see it >>working for real on a board. And with some characterization data to >>back it up. That's because engineers have been burned too many times >>for claims of serial I/O greatness only to be left without working >>silicon when it comes times for the rubber to hit the road. > > > Which is why I made the pinch of salt comment > > >>Who cares about seeing info under NDA? 6.25 Gbps and above I/O is too >>critical to count on some powerpoint presentation that claims great >>I/O performance. > > > Agreed 100% -- at the point when a hardware decision has to be made. > > >>You can get a Xilinx V2 Pro X today and verify for yourself if it >>meets your needs in the lab. Real silicon operating at 10 Gbps on a >>real board. Case closed with no decision for me unless I can see a >>Stratix II running on a real board. > > > Or Stratix II GX (which doesn't exist yet). Xilinx undoubtedly have a > technology lead now as far as CDR is concerned, so Altera will have to > improve theirs. Very few applications need (or can cope with) 10Gb/s > now (and using these rates in practice is not trivial) but many need > 3Gb/s, so you could say that Xilinx are ahead of the CDR market and > Altera are in line with with the market. If Altera have a faster > solution by the time it's generally needed that's fine, if not they'll > be in trouble -- so I'm pretty sure it will happen. > > >>With Xilinx you don't even need to have all the great equipment >>yourself. You can go to a rocket lab and see for yourself. >> >>Also, I would much prefer to run a 10 Gbps device at 6.25 than a 6.25 >>Gbps device at 6.25 Gbps. I'll take all the extra margin any day. >> > > > Given a free choice *and all other things being equal*, I'd agree. > But... > > Are you seriously suggesting that I go to a happy all-Altera customer > and tell them that they'll have to switch over to Xilinx if they want > to use our technology? > > I can tell you what the outcome would be, and it wouldn't involve > Xilinx...:-) > > Ian > > >>Ian & Hilda Dedic <news.nospam@dedics.co.uk> wrote in message news:<3099tbF2te2tsU1@uni-berlin.de>... >> >>>Hi Austin >>> >>>Obviously there is more margin if you're not pushing the transceiver so >>>hard, and being in the IC business I always take "real-soon-now" with a >>>large pinch of salt. >>> >>>But in the timescales we're looking at it seems that there will be >>>solutions from both the biggest FPGA vendors, which always helps when >>>talking to customers who might exclusively use one or the other...:-) >>> >>>Cheers >>> >>>IanArticle: 76138
"newman5382" <newman5382@aol.com> wrote in message news:R5lpd.68810$8G4.37498@tornado.tampabay.rr.com... > > "Mouarf" <mouarf@chezmoi.fr> wrote in message > news:41a5ca7c$0$17590$636a15ce@news.free.fr... > > hello all, > > > > For a hobbyist purpose, I want to drive an LCD display (320x240) with a > > CPLD or FPGA in a standalone device (weather station). I've already played > > with FPGA and VHDL for some projects but I was never involved in the > > hardware part of such projects. > > > > The CPLD would have to read data (bitmap picture) from a dual port RAM and > > write it to the 4 bit data input of the LCD controller (+control lines, > > clock...). On the other side of the RAM, a microcontroller will update > > sometimes the content of the picture to be displayed. > > > > I would like to know how to estimate the number of gate needed for the > > project in order to buy the cheapest CPLD that fits the number of gate. > > > > Do I need first to design the VHDL part and synthetize to know the number > > of gate and then choose the CPLD? > > That is my preference. IMHO, CPLD's can be a real pain if one > underestimates the size and or fan-in. Also, the implementation is more > sensitive to the pin out selected. > As a point of reference (FPGA), a monochrome EL display (160x120) used > > 486/4992 (9%) LE ACEX1K EP1K100FI256-2 > 40,960/49152 (83%) memory bits (two frames in DP RAM) > > -- not a particularly good LE to DP RAM ratio. > > > > > I do not really understand the difference between CPLD and FPGA and what > > is better for me. > > Some CPLD's have really low power. Most FPGA's have on board memory > that can be conveniently utilized. A uP with dual port ram, and logic could > be > packaged in a single FPGA chip to drive the LCD display. I've seen some > FPGA > evaluation boards that claim to do this. The Xilinx website has some boards > and > links to other vendors that sell this stuff. You may be able to get some > other > data points from this in order to estimate the amount of logic needed. > > > > > For a CPLD, the configuration is non volatile and in the FPGA it is > > volatile so a reconfiguration is needed on each start (via configuration > > EEPROM or JTAG programming) but the FPGA is much more powerfull. Correct? > > There was some talk about someone having an FPGA with configuration flash on > board the FPGA, but I can neither confirm nor deny this assertion. An FPGA > can > be configured from non-volatile storage via a uP too. I believe Lattice does have non-volatile FPGAs. I suspect they're a bit pricey. http://www.latticesemi.com/products/fpga/xpga/index.cfm Best wishes, --Phil Martel > > > > > Is a CPLD enough for my project? I'm turning around Xilinx XC9536 which > > seems to be very often used nowadays, is it a good choice for this > > project? > > > I would estimate the amount of Dual Port RAM bits required to see if I could > get rid of the discrete dual port RAM by using resources in the FPGA. If a > suitable > FPGA can be found with a good DP RAM to LE ratio, I would further research > the > cost in an attempt to justify using an FPGA, which I think would be more fun > :,) > > -- Newman > > > > > Many thanks by advance. > > > > > > > >Article: 76139
wkopp@gmx.net (woko) writes: > How can a AT49LV001 flash by programmed through a XC9536XL CPLD and > its JTAG-connector with really low cost? What would you consider low cost for a product like this? It's not very difficult to do if you have some programming experience. You have to know the position of the pld in the jtag chain, you have to parse the bsdl file for the cpld, you need to know which pins are connected to the flash (possibly parse the edif netlist for the board or make a separate description) and then generate patterns which will control the pins connected to the flash to generate write commands with the data you want to write. Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 76140
"vax, 9000" <vax9000@gmail.com> wrote in message news:co5cnd$hg4$1@charm.magnus.acs.ohio-state.edu... > Marcin Olak wrote: > > > Hello, > > > > Do you guys know about any open-source 386 compliant IP Core ? I've > > heared that there are some patents pending on 386 and it is illegall to > > produce 386 clones : > I'm an confused - is it a hoax or not ? If not - > > why there are no open-source 386 IP Cores available ? > > Maybe the reason is that a 386 is much more complicated than an 8086. there is no free or open-source 386 there is no free or open-source 86 :( all what is available is commercial I have a partial 86 (some assembly programs working) but that project is on ice AnttiArticle: 76141
Marcin Olak wrote: > Hello, > > Do you guys know about any open-source 386 compliant IP Core ? I've > heared that there are some patents pending on 386 and it is illegall to > produce 386 clones : > I'm an confused - is it a hoax or not ? If not - why > there are no open-source 386 IP Cores available ? > > greetings! > Marcin Olak > > > Why bother with 80386? With other CPU architectures you can run your CPU faster, get better system performance, and use less LUT in your FPGA. 80386 was available around 1985 (?), so if there is any patents they should have expired. I think design patents only last 14 years in US (please let me know if it is wrong!) and can be different in other countries. JoeArticle: 76142
Hello,
> Why bother with 80386?
Anyone can write programmes for embedded systems with 386 processor
using tools, everybody's familliar with. It's just mere PC-AT. No additional
knowledge needed to program it.
> With other CPU architectures you can run your
> CPU faster, get better system performance, and use less LUT in your
> FPGA.
In some cases time-to-market factor may have the biggest priority : )
greetings!
Marcin Olak
Article: 76143"Antti Lukats" <antti@case2000.com> wrote in message news:co5far$sl4$04$1@news.t-online.com... > > "vax, 9000" <vax9000@gmail.com> wrote in message > news:co5cnd$hg4$1@charm.magnus.acs.ohio-state.edu... >> Marcin Olak wrote: >> >> > Hello, >> > >> > Do you guys know about any open-source 386 compliant IP Core ? I've >> > heared that there are some patents pending on 386 and it is illegall to >> > produce 386 clones : > I'm an confused - is it a hoax or not ? If not - >> > why there are no open-source 386 IP Cores available ? >> >> Maybe the reason is that a 386 is much more complicated than an 8086. > > there is no free or open-source 386 > there is no free or open-source 86 > :( Well there is a semi-free simulation one :-) As soon as I have some more time I will add the synthesizable version. See http://www.ht-lab.com/freecores/cpu8086/cpu86.html Regards, Hans. > all what is available is commercial > I have a partial 86 (some assembly programs working) but that project is > on > ice > > Antti > > >Article: 76144
I'm looking for a rad-tolerant, non-volatile (preferably programmable at once) FPGA or CPLD, for a new project (a satellite instrument). After searching the Web, I've found out that Actel manufactures micro antifuse FPGAs. These would be fine, but I would like to know if are there any other alternatives besides Actel FPGAs. The device should have around 2500 user gates or more. Reliability is a concern to us, and availability of a similar or equivalent, in System Programmable (ISP), part would be a plus. Any single chip solution (preferably non-reprogrammable, to avoid unintentional program changes, due to radiation) would be fine, including CPLDs. P.S: ASICs (Field Gate Arrays) would be OK, provided it cost less than US$10,000.00 and takes less than a month or two to be fabricated. In case we opt for an ASIC, only around 3-5 units would be produced. If you are willing to help, you can e-mail me directly: maaf _att_ dea.inpe.br (replace the _att_ by an @) Best Regards, Marcio --------------------------------------------------- Marcio Afonso Arimura Fialho Junior Electronic Engineer DEA - Divisão de Eletrônica Aeroespacial INPE - Instituto Nacional de Pesquisas Espaciais (Brazilian National Institute for Space Research).Article: 76145
"Hans" <hansydelm@no-spam-ntlworld.com> wrote in message news:Lxspd.877$wc5.776@newsfe5-gui.ntli.net... > > "Antti Lukats" <antti@case2000.com> wrote in message > news:co5far$sl4$04$1@news.t-online.com... > > > > "vax, 9000" <vax9000@gmail.com> wrote in message > > news:co5cnd$hg4$1@charm.magnus.acs.ohio-state.edu... > >> Marcin Olak wrote: > >> > >> > Hello, > >> > > >> > Do you guys know about any open-source 386 compliant IP Core ? I've > >> > heared that there are some patents pending on 386 and it is illegall to > >> > produce 386 clones : > I'm an confused - is it a hoax or not ? If not - > >> > why there are no open-source 386 IP Cores available ? > >> > >> Maybe the reason is that a 386 is much more complicated than an 8086. > > > > there is no free or open-source 386 > > there is no free or open-source 86 > > :( > > Well there is a semi-free simulation one :-) As soon as I have some more > time I will add the synthesizable version. > > See http://www.ht-lab.com/freecores/cpu8086/cpu86.html > > Regards, > Hans. yes, I know the above, but that only precompiled simulation, not match for those who want to use it in FPGA AnttiArticle: 76146
Your claims of 39% performance advantage for Stratix II over V4 are a lie. I don't believe a word of it. You don't give any proof for your wild claims. My guess is that here is how it works. Step 1. Grab a bunch of customer designs submitted to correct the thousands of bugs contained in your software. Step 2. Software engineers fine tune all your fitting and routing algorithms to make the best possible performance on these designs. Step 3. Run these designs again and again with different fitting and routing settings to zero in on the best result possible. Step 4. After these designs are fine tuned for Altera p&r, run the design through the Xilinx software one time with no special efforts to get good results. Step 5. Pick V4 devices that are of a slower speed grade than your Stratix II device. Fastest SII vs. middle V4. Step 6. Lie about how great your benchmarking methodology is. Step 7. Trot out a Ph.D. professor at the U of T that I believe was made a millionaire by Altera when they bought his company to say how fair and great you are. Step 8. Have a web seminar on Dec. 7 with same Altera made millionaire to try and get people to believe your lies. Eric Cleage is gone. I would have expected you to become more honest in your marketing efforts after that. http://www.altera.com/corporate/news_room/releases/corporate/nr-marketing_reorg.html "Paul Leventis \(at home\)" <paulleventis-news@yahoo.ca> wrote in message news:<sdydnUiyB9In7TjcRVn-ow@rogers.com>... > Hi Varun, > > I think that the simple answer is that a purchase for a single design cannot > be made purely off of general benchmarking results. You need to evaluate > the performance of our chips (and any others) for your design and its > requirements. And you need to factor in other chip features and performance > parameters, the price you can get from your distributor/fae, the packaging > choices, device availability, etc. > > Let's step away from questions of benchmarking validity, averaging methods > and such. In the end, we get a spread of results. If your design happens > to be one of the designs that experiences equivalent performance (or say you > are the data point at the extreme left in Figure 1 at > http://www.altera.com/products/devices/performance/high_performance/per-high_performance_fpga.html), > then our 39% means nothing to you. > > All benchmarking results do is provide you with some guidance of what to > expect. Based on our Stratix II benchmarking results, you can expect a chip > that will likely outperform Virtex-4. This could mean that you hit your > performance target in one and not the other. Or it could mean that you can > buy a cheaper speed grade in Stratix II but need a more expensive speed > grade in Virtex-4. Similarly, you can expect Cyclone II to be ~60% faster > than Spartan-3. > > If you only have time to try one chip, I think it should be Stratix II or > Cyclone/Cyclone II (depending on your needs), given the average results we > see. If you have time to try two chips, I still think you should just buy > ours ;-) -- but I will grudgingly accept that you will probably try out what > Xilinx has to offer too :-) > > Does that mean Stratix II is the right chip for you? Not necessarily.Article: 76147
http://www.universalscan.com "woko" <wkopp@gmx.net> wrote in message news:6502961c.0411250001.5038423c@posting.google.com... > Hello! > > I want to revitalise a question at was asked in 2001, because I hope > something changed during the time. > > How can a AT49LV001 flash by programmed through a XC9536XL CPLD and > its JTAG-connector with really low cost? > > All address, data and control pins are connected to the CPLD, so ISP > via JTAG should be possible.I'm sure there are lots of tools available > at this time for programming, but still I don't want to pay >10k USD. > > Does anyone know if it's possible to program at flash with JAMPLAYER > sw from altera? How much effort would it be to implement flash > algorithms? > > regards, > > WolfgangArticle: 76148
Hi Stifler, A pleasure hearing from you again. I probably should ignore your entire post, but here I go... > Step 4. After these designs are fine tuned for Altera p&r, run the > design through the Xilinx software one time with no special efforts to > get good results. We expend considerable effort to get the best results we can out of Xilinx P&R. I know that's hard to believe, but its what we do. > Step 5. Pick V4 devices that are of a slower speed grade than your > Stratix II device. Fastest SII vs. middle V4. Please tell me how to select a faster V-4 device in the software and we'll benchmark against it. If you don't like the comparison, derate our result by the speed difference between -3 and -4 Stratix II devices. We will still be winning by ~25%. But I think the comparison is valid as it stands; if you need an FPGA with the most speed, the "fast" speed grade for V4 is not an option given that it isn't shipping nor is it in the software. > Step 7. Trot out a Ph.D. professor at the U of T that I believe was > made a millionaire by Altera when they bought his company to say how > fair and great you are. > Step 8. Have a web seminar on Dec. 7 with same Altera made millionaire > to try and get people to believe your lies. Dr. Brown is a Senior Director in our Toronto office and oversees (amoung other things) benchmarking and performance analysis. He is also a professor at the University of Toronto who's done a lot of fundamental work in FPGA research. He also wrote a pretty good textbook on digital design. He's good at a lot of things, but lying really isn't one of them. Steve was not part of any company acquired by Altera; we have more than one U of T professor working for us. Regards, Paul Leventis Altera Corp.Article: 76149
Hi Glen, > Be very careful when you read benchmark numbers, and always > use geometric mean. For your reference, the +39% Stratix II vs. Virtex-4 benchmark result uses geometric mean. The A vs. B and B vs. A result you give is one motivation. Another is that if you use arithmetic average, a large outlier will heavily skew results, whereas in geometric mean, the impact is less. Paul Leventis Altera Corp.
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