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[lots of snipped] > > Rick, hmmm... care to comment? > > see synthesis and timing reports above :) > > This shows that my approach will run twice as fast. It produces two > results rather than one and so can be constrained to require two clock > periods. You need to set your timing constraints to reflect that. The > only paths that don't run at the half clock rate are the output mux > running into accfast and the phase control signal. Set the path delay > on the accsingle and accdouble paths to be *two* clock periods (except > for the enable from phase). :) ok, well your code "AS IS" did not synthesise so I tried mind guess an fix to get it synthesize, posible making an error in the guess work. YES, calculating 2 bits per clock is a solution, this is also what I suggested in one of my earlier posts I presented the synthesis (and timing) of the code "as you wrote" it (after fix) I dont see the output mux in your code, and I did not add it either generically I agree similar approuch (if code is correct) runs about twice the speed > But your timing numbers show both designs running at over 200 MHz which > is the OPs requirement, IIRC. Did you have to do any floorplanning? > Also, are these numbers post ROUTE or the output from synthesis? Timing > results from synthesis are worthless. I would like to see the details > on the critical path in each case. I posted both synthesis estimate and post place and route timings, in any case both approuch are 210MHz + No floorplanning, just set clock constraint to 5ns nothing more > The logic for my code should be a minimum of 97 LUTs. Your result is > only 34 slices which is a maximum of 68 LUTs. I suspect there is some > problem so that the code does not synthesize correctly (possibly in the > code). yes, possible i corrected your code incorrectly :( > I have not looked at the CLB details of the newer Xilinx FPGAs. An > adder still requires 1 LUT per bit, right? inc_value is a signal and > not a constant, right? I used all signal 32 bit wide, inc_value as input port > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 76526
Sirish, I sucessfully programmed the Spartan with Parallel IV cable with the bridge, i'm sorry to have bothered you with this question, since within 4h i found a manual describing what u said, still thanks a lot for replying. I encountered some problems downloading the pci bridge design though, at first the data transfer rate over the cable was set at 5 MHz, stopping the download process and crashing my PC, when I had put it on 2.5 MHz it still didn't worked, eventually i have put it on 200 KHz and this worked just fine. iMPACT allows u to set the rate. Good luck to you, and thanks for the help ! Greetings, Paolo "Sirish" <sirishka_no_spam@hotmail.com> schreef in bericht news:coi6h4$1ep$1@nntp.msstate.edu... > Paolo, > > As far as I understand, the board comes with the Spartan loaded with the > "pass-thru" bit file. This allows the board to be tested/used without > plugging it into a PCI slot. So, till you are able to load the bridge > program > onto the spartan, the board will not be seen by the PC. > I have placed an order for a JTAG4 cable, but haven't received it yet. Plan > to > try it again after i am able to program the spartan. > > -Sirish > > "Mindroad" <mindroad@hotmail.com> wrote in message > news:41ab6362$0$13480$ba620e4c@news.skynet.be... > > System : Win XP (Fresh install) > > > > Read the user's guide multiple times to ensure correct jumper settings. > > The board is configured for SelectMAP programming mode JP8 shunted > > The board is configed in master-serial mode for PROM programming of > SPARTAN > > bridge : JP9 open > > Other jumpers have default values, triple checked > > > > The S1 and S2 dipswitches : > > S1 : all on off ... CF card loads position 0 normally > > S2 : all on off as described in user guide > > > > inserted the card into 32bit PCI slot > > for normal PCI use at present time > > > > booted PC > > followed driver installation instructions, windriver6.inf installed by => > > wdreg -inf "location of inf file" install > > then copied avpci...inf file to WINDOWS/INF directory then rebooted. > > > > Accessed PCI Utility : no board connected > > > > Tried to manually install the avpci driver, still nothing detected ... > > Checked PCI slots, and no extra entries in ID list of device wether or not > > the device is connected to the bus > > > > Has somebody experienced this problem ? > > Could it be the PROM not longer contains the config file for the bridge or > > should i look for answers in another direction > > > > Thx in advance, > > > > Paolo > > > > > >Article: 76527
Check our web site www.mvd-fpga.com at MVD Products => Perfidia; ( second posting, the first never appears ) Walter. "Nicholas Weaver" <nweaver@soda.csua.berkeley.edu> a écrit dans le message de news:coikr1$11p9$1@agate.berkeley.edu... > I'm doing a pretty complex state machine, which is perfect for in > memory (blockRAM based) encoding. > > Before I go through and build my own state machine compiler out of > python hack-scripts or Excel macros, does someone already have such a > compiler available? > -- > Nicholas C. Weaver. to reply email to "nweaver" at the domain > icsi.berkeley.eduArticle: 76528
"rickman" <spamgoeshere4@yahoo.com> wrote in message news:41B35233.F5D96004@yahoo.com... > Antti Lukats wrote: > > > > "rickman" <spamgoeshere4@yahoo.com> wrote in message > > news:41B32744.70D3A95F@yahoo.com... > > > Moti Cohen wrote: > > > > > > > > Hello all, > > > > I've a design that contains a NCO (Numerically controlled oscillator). > > > > The NCO consists of a 32'bit accumulator. when i write the accumulator > > > > straight forward like this - [snip] > The logic for my code should be a minimum of 97 LUTs. Your result is > only 34 slices which is a maximum of 68 LUTs. I suspect there is some > problem so that the code does not synthesize correctly (possibly in the > code). > > I have not looked at the CLB details of the newer Xilinx FPGAs. An > adder still requires 1 LUT per bit, right? inc_value is a signal and > not a constant, right? > > Rick "rickman" Collins hm... out of curiosity I did check DDSX ipcore in 2X mode (that is calculating 2 bits per clock), the following stats are for - 32 bit wide accumulator - 32 bit variable phase increment value Synthesis: Selected Device : 3s1500fg320-5 Number of Slices: 33 out of 13312 0% Minimum period: 4.577ns (Maximum Frequency: 218.508MHz) Post P&R Timing: Timing constraint: TS_clk = PERIOD TIMEGRP "clk" 5 nS HIGH 50.000000 % ; 497 items analyzed, 0 timing errors detected. (0 setup errors, 0 hold errors) Minimum period is 4.657ns. ---------------------------------------------------------------------------- ---- All constraints were met. Design statistics: Minimum period: 4.657ns (Maximum frequency: 214.731MHz) So DDSX ipcore can calculate 2 bits per clock (to be muxed or serialized) at max frequency 214MHz using 33 Slices! Ok, lets add one more slice for the mux or shifter that comes to 34 slices :) DDSX ipcore (in 2x mode) runs completly at 0.5 x DDS frequency! So if the FPGA fabric can run a 2 bit shifter at 400MHz then the DDS would run at virtual 400MHz Real 400MHz is only used in one slice doing the shift or not at all when the DDR iocell uses 2 phases of the clock. Antti PS just did run timing check on the 10GHz version of DDSX no problems either :) Sure 10GHz only with V4FX or V2ProX (using GT10 as serializer)Article: 76529
Hi Rickman, I wrote -> > there is only one thing bothering me in your code - the "accsingle" > register is sampled on each rising edge of clock and therefore > does not improves the setup time (and therefore the frequency & clk > rate) i suppose that it should be sampled on every 2'nd clock You wrote -> Yes, both accsingle and accdouble are sampled on the rising edge of the clock, but only when phase is high and so only *every other* clock That's what I ment : as to my understanding accdouble is indeed being sampled every other clock but, accsingle is samped on every clock as follows : when phase = '1' accsingle is being updated : accsingle <= accdouble + inc_value when phase = '0' accsingle is getting sampled : accfast <= accsingle so it seems to me that it is getting sampled one clock edge after it is being changed (via the large logic block) , am I wrong or missing something ??..Article: 76530
Hello all, I'm curious to hear some comments on the following idea. I had a bus interface (total of 9, 16 bit wide registers) that I had originally designed a large bus multiplexer for. The select lines were coded into a 9 bit vector "000000001" when the first register was addressed, "000000010" when the second register was addressed, and so on, all controlled via address lines, chip selects, and read strobes. This seemed to produce a fair amount of logic, and slower speeds so I thought of using the 9 bit select vector to control internal tristates i.e. : data <= register1 when sel(0) = '1' else (others 'Z'). data <= register2 when sel(1) = '1' else (others 'Z'). data <= register3 when sel(2) = '1' else (others 'Z'). Since I haven't seen this done before in my searches I was curious to see some comments on it. Pros, cons, is it an acceptable means to accomplish this or should I stick to the bus multiplexer. All comments are appreciated. I'm using a Spartan II just in case anyone is interested. Thanks JasonArticle: 76531
I'm not certain about the Xilinx parts, but in many FPGA's there is no tri-state capability in internal logic (onl;y in the IO blocks). So, whilst the synthesis should make your idea work, it will in truth create something similar to the MUX "Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote in message news:O4Psd.15588$dC3.197817@news20.bellglobal.com... > Hello all, > > I'm curious to hear some comments on the following idea. I had a bus > interface (total of 9, 16 bit wide registers) that I had originally > designed > a large bus multiplexer for. The select lines were coded into a 9 bit > vector > "000000001" when the first register was addressed, "000000010" when the > second register was addressed, and so on, all controlled via address > lines, > chip selects, and read strobes. This seemed to produce a fair amount of > logic, and slower speeds so I thought of using the 9 bit select vector to > control internal tristates i.e. : > > data <= register1 when sel(0) = '1' else (others 'Z'). > data <= register2 when sel(1) = '1' else (others 'Z'). > data <= register3 when sel(2) = '1' else (others 'Z'). > > Since I haven't seen this done before in my searches I was curious to see > some comments on it. Pros, cons, is it an acceptable means to accomplish > this or should I stick to the bus multiplexer. All comments are > appreciated. > > I'm using a Spartan II just in case anyone is interested. > > Thanks > > Jason > >Article: 76532
Just upgraded ISE and EDK to 6.3 from 6.2. We use a small SoC consisting of a microblaze, SDRAM/DDRAM controllers and RS232 (uartlite). We use various development boards from Memec-Insight with Virtex 1000 and VP20. We always use microblaze CPU, and depending on the development board SDRAM or DDRAM controllers. Anyway, after the upgrade, the soc seems to be broken. Looks like the UART output is somewhat garbled. I don't want to debug the SoC again, just because I upgraded the tools. Does anybody know of any known gotchas ? We are using the latest service packs for all the tools from the xilinx web site. We really wanted to migrate to 6.3 as we would like to support Virtex 4 as well. Any pointers/suggestions, appreciated. Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 76533
newman5382 wrote: > Hey, > I was considering purchasing a DS-KIT-2VP20FF1152-SF eval board from > Memec. > > http://www.insight.na.memec.com/Memec/iplanet/link1/VirtexIIPro_FF1152_2.pdf > > I thought about getting a Virtex4 board, but I have not seen one with > the > Power PC yet. > I need to commit a purchase before the end of the year. > I've already got some of their mezzanine boards and system ACE adapter. > I thought the Rocket I/O might be fun to play with. > I want board resources to boot u-boot and Linux. > It looks like I get a pretty good EDK bundle deal with this package. > Maybe I should go with a P30? > > If anybody can comment on the Pro's and Con's before I commit the > purchase, I would appreciate it very much. > > -Thanks, > > Newman We use the VP20 development boards from Memec-Insight. Overall we are very please with the boards. The biggest problems we had with Memec-Insight themselves. We ordered two boards, first got one Rev 1 board with a -5 FPGA (that had ENG SAMPLE stamped on it), even though they promote it with a -6 FPGA. A few weeks later we got a Rev 2 board with a -6 FPGA. After several weeks we where able to exchange the Rev 1 board, but now got a Rev 3 board (even though we asked for a Rev 2 board). It was important to us to have two 100% identical boards so we can load the same bit file on them. The Rev 3 uses a ATMEL Flash and a CPLD, the Rev 2 a Platform Flash from Xilinx .... Anyway, not a big deal, just an inconvenience. If you are just getting one board it will probably not matter. Nice development platform, we make a lot of the P160 expansion boards and love it. Best Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 76534
Rudolf Usselmann wrote: > > Just upgraded ISE and EDK to 6.3 from 6.2. We use a small SoC > consisting of a microblaze, SDRAM/DDRAM controllers and RS232 > (uartlite). > > We use various development boards from Memec-Insight with > Virtex 1000 and VP20. We always use microblaze CPU, and > depending on the development board SDRAM or DDRAM controllers. > > Anyway, after the upgrade, the soc seems to be broken. Looks > like the UART output is somewhat garbled. I don't want to > debug the SoC again, just because I upgraded the tools. Garbled UART output sounds like the baudrate may be incorrect. Maybe the UART-settings somehow got lost/changed during the upgrade? Or maybe they changed the name of the parameter that sets the baudrate in the latest version of the UART-core. Is the UART the only problem and everything else is working fine? cu, SeanArticle: 76535
hi, I was working on configuring an Spartan2E FPGA. I used Xilinx 6.2 for developing my VHDL module. I was using the JTAG cable given with the development board. I just followed the steps given in the manual like "Generate Programming file", and used "Configure Device(IMPACT)". But it was saying the error "done did not go high". I did not understand the error, and also I don't know how to check this 'done' signal. I would really appreciate if any one can give guidance on how to check with this error. Thanks, ViswanArticle: 76536
Hendra wrote: > Thomas Reinemann <thomas.reinemann@mb.uni-magdeburg.de> wrote > >> Classical approaches teach logic elements and logic minimation, but this >> is counterproductive. > > Why does the academic community still teach methods that are not used > in the industry, such as K-Map? I don't know the right translation, but I would it call mental or cerebral inertia. You are right, but youself said a beginner shall start with schematics. We all have been taught in this way. Just now these paradigms have to be replaced. Bye TomArticle: 76537
"Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote in message news:O4Psd.15588$dC3.197817@news20.bellglobal.com... > Hello all, > > I'm curious to hear some comments on the following idea. I had a bus > interface (total of 9, 16 bit wide registers) that I had originally designed > a large bus multiplexer for. The select lines were coded into a 9 bit vector design a bus(mux) to use internal tristate (TBUFs') can reduce the logic by significant amount, but for the new(current) technologies (S3/V4) TBUFs are no longer available so you end up using logic resources resources if targetting new families. for S2/E there internal tristate (TBUF) based mux saves logic anttiArticle: 76538
Yes it can, look in the .ll (logic allocation) file for the appropriate addresses Good luck, GerdArticle: 76539
Hi, I'm thinking to purchase xess fpga board (XSA and XST-2). I don't know I should buy which one. All XSA boards have almost same features. What do you think about it? Thanks to allArticle: 76540
Hello Do anyone have some examples of connecting a FPGA to the isa bus? I'm looking for how to connect to the interrupt lines. - Pulse length (minimum, maksimum)? - Pulse polarity (positive I think)? Thanks Rune ChristensenArticle: 76541
Rune Christensen wrote: > Hello > > Do anyone have some examples of connecting a FPGA to the isa bus? > > I'm looking for how to connect to the interrupt lines. > - Pulse length (minimum, maksimum)? > - Pulse polarity (positive I think)? Google is your friend. You need to pay attention to whether their voltage levels are compatible. My 386 PC has a 5v logic. The lines are 5v when they are logically '1'. vax, 9000 > > Thanks > Rune ChristensenArticle: 76542
I've slightly modified it and the 720 version isn't bad now but run times on
the following setup are still bad. It looks a bit pointless as a design but
as you can probably guess it was aimed at getting a real, in the field,
power consumption.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity TEST_POWER is
Port ( OUT_LINES : out std_logic_vector(260 downto 1);
CLOCK : in std_logic;
RESET : in std_logic);
end TEST_POWER;
architecture a0 of TEST_POWER is
CONSTANT VEC_SIZE : INTEGER:=7150;
CONSTANT IOSIZE : INTEGER:=260;
SIGNAL XOR_INPUT : STD_LOGIC_VECTOR(VEC_SIZE DOWNTO 1);
SIGNAL SHIFT_REG : STD_LOGIC_VECTOR(VEC_SIZE DOWNTO 0);
begin
XORGEN : FOR I IN 1 TO VEC_SIZE GENERATE
BEGIN
XOR_INPUT(I) <= SHIFT_REG(I) XOR SHIFT_REG(I-1);
END GENERATE;
PROCESS(RESET,CLOCK)
BEGIN
IF (RESET = '1') THEN
SHIFT_REG <= (OTHERS => '1');
OUT_LINES <= (OTHERS => '0');
ELSIF (CLOCK'EVENT AND CLOCK ='1') THEN
SHIFT_REG <= XOR_INPUT & (NOT SHIFT_REG(0));
OUT_LINES((IOSIZE - 1) downto 1) <= SHIFT_REG((IOSIZE - 1) DOWNTO 1);
OUT_LINES((IOSIZE)) <= SHIFT_REG(VEC_SIZE);
END IF;
END PROCESS;
John
end a0;
"Subroto Datta" <sdatta@altera.com> wrote in message
news:ca4d800d.0412031630.2e98268a@posting.google.com...
> "John" <placename@remove_fpga_people.co.uk> wrote in message
news:<1102069745.41459.0@iris.uk.clara.net>...
> > I have been running a shift register design through a web version of
Quartus
> > 4.1 (SP2). Depending on the size of shift register either the tools
don't
> > complete (I waited 30 mins and gave up) or on smaller shifts of 720 I
get a
> > design that is a large size and it takes a long time to implement.
> >
> > Has anyone else seen this problem ? Or know of any tool switches that
need
> > set to solve this ?
> >
> > I have selected large enough Cyclone part and before anyone asks I am
> > running a reasonable machine. An Athlon64 3000 with 512 MByte of memory
for
> > those that want the detail. I have run the same design (large version)
on
> > Spartan-3 / ISE and it less than 3 minutes to do the same.
> >
> > John
>
> John,
> We would like to investigate this further and help you. It would
> help if you would send me the source that you used or post it here.
>
> Thanks
> - Subroto Datta
> Altera Corp.
Article: 76543It is only 45 CLBs if you don't use a reset. The point of this design was as a power test, to fill a device, and subsequently get a genuine accurate power reading. Xilinx have a hugh advantage on shift registers with SRL16s which I believe Altera can't easily mimic due to patent issues. Someone from Altera can tell me if I am wrong in this. The 720 version was done with the help of Wizards and not the code posted elsewhere and came to about 1100 LEs. With a variation of the code posted it started to get better. John "Walter Gallegos" <walter@chasque.apc.org> wrote in message news:10r3bcj5p2pt259@news.supernews.com... > 720 stages shift register need 45 Xilinx CLBs; but how many Altera LEs ? > > Walter. > > > "Subroto Datta" <sdatta@altera.com> a écrit dans le message de > news:ca4d800d.0412031630.2e98268a@posting.google.com... > > "John" <placename@remove_fpga_people.co.uk> wrote in message > news:<1102069745.41459.0@iris.uk.clara.net>... > > > I have been running a shift register design through a web version of > Quartus > > > 4.1 (SP2). Depending on the size of shift register either the tools > don't > > > complete (I waited 30 mins and gave up) or on smaller shifts of 720 I > get a > > > design that is a large size and it takes a long time to implement. > > > > > > Has anyone else seen this problem ? Or know of any tool switches that > need > > > set to solve this ? > > > > > > I have selected large enough Cyclone part and before anyone asks I am > > > running a reasonable machine. An Athlon64 3000 with 512 MByte of memory > for > > > those that want the detail. I have run the same design (large version) > on > > > Spartan-3 / ISE and it less than 3 minutes to do the same. > > > > > > John > > > > John, > > We would like to investigate this further and help you. It would > > help if you would send me the source that you used or post it here. > > > > Thanks > > - Subroto Datta > > Altera Corp. > >Article: 76544
I use a Spartan2E xc2s50e, but when I configure it using Parallel Cable IV JTAG, it is recognised as a VirtexE xcv50e!!! Obviously my .bit file is configured as xc2s50e and there is no problem when I configure the flash xcf01s. When I try to configure directly the fpga it gives me a warning, but works fine. The problem is when I try to use Chipscope pro: COMMAND: configure 1 "C:\Lavori\menfis\ACQ3000\FPGA\acq3000.bit" 0 ERROR: Configuration Failed: Done Pin is low INFO: Found 0 Core Units in the JTAG device Chain. I think the problem is that it recognise an xcv50e, while .bit file is configured for xc2s50e. How can I make it recognise correctly my spartan2e? thanks -- Mastupristi?Article: 76545
http://www.ardice.com/Computers/Programming/Graphics/Libraries/OpenGL/Add-on_Libraries/Article: 76546
Yes they do. Our Broaddown2 supports PCI. It is pinned out to use the Xilinx core or do your own. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Kiran M" <kiran@fepis.com> wrote in message news:1102089345.D18s2RiqkblBrcuczfXY9Q@teranews... > Hi everybody. I want to start experimenting with fpga hardware. I > have experience with simulating RISC processors in modelsim. I want > to know which dev board would be a good starting point. There seem to > be many boards out there but i want one with pci interface. Do > spartan3 boards come with pci ?Article: 76547
Mastupristi a écrit: > The problem is when I try to use Chipscope pro: > COMMAND: configure 1 "C:\Lavori\menfis\ACQ3000\FPGA\acq3000.bit" 0 > ERROR: Configuration Failed: > > Done Pin is low > INFO: Found 0 Core Units in the JTAG device Chain. I'm having the same problem with an XC3S. I've worked around it by configuring the device with Impact and then using ChipScope. > I think the problem is that it recognise an xcv50e, while .bit file is > configured for xc2s50e. I noticed this a few years ago when I used XC2S parts. It puzzled me at first but since it worked I didn't mind. That is absolutely NOT a problem. -- ____ _ __ ___ | _ \_)/ _|/ _ \ Adresse de retour invalide: retirez le - | | | | | (_| |_| | Invalid return address: remove the - |_| |_|_|\__|\___/Article: 76548
I believe some early Spartan-2e chips came up as Virtex-E. I think they came off the same line and/or mask set for first deliveries. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Mastupristi" <cialdi_NO_SP@AM_firenze.net> wrote in message news:20041206113707.00006ded.cialdi_NO_SP@AM_firenze.net... > I use a Spartan2E xc2s50e, but when I configure it using Parallel Cable IV > JTAG, it is recognised as a VirtexE xcv50e!!! > > Obviously my .bit file is configured as xc2s50e and there is no problem when > I configure the flash xcf01s. When I try to configure directly the fpga it > gives me a warning, but works fine. > > The problem is when I try to use Chipscope pro: > COMMAND: configure 1 "C:\Lavori\menfis\ACQ3000\FPGA\acq3000.bit" 0 > ERROR: Configuration Failed: > > Done Pin is low > INFO: Found 0 Core Units in the JTAG device Chain. > > > I think the problem is that it recognise an xcv50e, while .bit file is > configured for xc2s50e. > > How can I make it recognise correctly my spartan2e? > > thanks > > -- > Mastupristi?Article: 76549
It is a good way when you have tristates and I have used it many times. However not many people used this technique and Xilinx have reduced and totally phased out internal tristates in their later families for this reason and others. For Spartan-II though it is a very good way to save CLB resources but don't expect the same results for Spartan-3 etc. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "Jason Berringer" <jberringer.at@sympatico.dot.ca> wrote in message news:O4Psd.15588$dC3.197817@news20.bellglobal.com... > Hello all, > > I'm curious to hear some comments on the following idea. I had a bus > interface (total of 9, 16 bit wide registers) that I had originally designed > a large bus multiplexer for. The select lines were coded into a 9 bit vector > "000000001" when the first register was addressed, "000000010" when the > second register was addressed, and so on, all controlled via address lines, > chip selects, and read strobes. This seemed to produce a fair amount of > logic, and slower speeds so I thought of using the 9 bit select vector to > control internal tristates i.e. : > > data <= register1 when sel(0) = '1' else (others 'Z'). > data <= register2 when sel(1) = '1' else (others 'Z'). > data <= register3 when sel(2) = '1' else (others 'Z'). > > Since I haven't seen this done before in my searches I was curious to see > some comments on it. Pros, cons, is it an acceptable means to accomplish > this or should I stick to the bus multiplexer. All comments are appreciated. > > I'm using a Spartan II just in case anyone is interested. > > Thanks > > Jason > >
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