Custom Search
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z
It seems that the program can't connect to X. I had the same problem. I had to enable TCP connection to my X server. For this you should search trough the doc of you ditrib. In my case I'm using Ubuntu (debian) and gdm as login manager, so I had to edit the file /etc/gdm/gdm.conf and change: DisallowTCP=true into DisallowTCP=false Then I restarted gdm and the problem was over. If it still doesn't work maybe you should also try to enable connection to X by typing "xhost localhost" or "xhost +" in a terminal (careful, the second one enable EVERYONE to connect to your server, what could lead to a security hazard). Hope this help. John Williams wrote: > Hi Geoffrey, > > Geoffrey Wall wrote: > >> i know Fedora is not officially supported but, has anyone had the >> following problem when trying to install ISE 6.3i : >> >> [root@moose cdrom]# ./setup >> Wind/U Error (294): Unable to install Wind/U ini file >> (/media/cdrom/data/WindU). >> See the Wind/U manual for more details on the ".WindU" file and the >> "WINDU" >> environment variable. >> Wind/U X-toolkit Error: wuDisplay: Can't open display >> >> >> ************ setup done! *************** >> >> [root@moose cdrom]# echo $DISPLAY >> :0.0 >> >> >> as you can see, i start the setup and it cant seem to find the correct >> display >> i can run other X apps fine though... >> any one have any ideas? > > > > Try "export LD_ASSUME_KERNEL=2.4.7" before you run the setup util. > > Regards, > > JohnArticle: 78176
> But in order to boot the Mac a 5380 would have to be emulated, as well > as the IWM, at least for the status register on the IWM, right? Or am > I missing something? I've got the data sheets and info on the IWM, so > it can be done... I thought it had the OS in ROM. Perhaps you could make a gadget that looks like a 5380 Ooh look what I found in my chip collection. a DP5380 from national semiconductor. Must be pretty early one too, it has "ENGR SAMPLE" printed on it. Date code 8735! I'd certainly swap it for a 68HC000 PLCC68 16 MHz for instance :-) > I found another 512k board that has an MFM hard drive interface on it > (after market), supposedly it boots. Maybe that will give me some > insight. MFM is just as dead as SCSI, or even more so.Article: 78177
Tobias, let me assume you are serious: I wrote that some reliability qualification test have not been completed. But I also said that the parts are completely tested. Anybody familiar with IC testing understands that. The production testing is done 100% (functionality plus ac and dc parameters) The reliability qualification test are something completely different. The word "test" has several meanings. Now, if you are a lawyer... Peter ===================== Tobias Weingartner wrote: > Peter Alfke wrote: > > We call them ES because some long-term reliability qualification tests > > have not yet been completed. > > And a little later... > > > But any idea that ES parts are flakey, not completely tested, or > > unreliable is dead WRONG. > > Hmm... > > First you say that "some" ... tests have not yet been completed, and > then you say "not completely tested ... is dead WRONG". I hate to > quibble, but you ain't having it both ways... :-) > > -- > [100~Plax]sb16i0A2172656B63616820636420726568746F6E61207473754A[dZ1!=b]salaxArticle: 78178
Neiko wrote:
> I am trying to install ISE 6.3i on a Gentoo distribution. I tried
> Fedora and couldn't get it to work either, so I'm sticking with Gentoo
> since I know its workings better. Anyways, when I try to install I get:
>
> isengard cdrom # ./setup
> -bash: ./setup: /bin/sh: bad interpreter: Permission denied
I once fixed that error by converting the
script dos2unix before executing it.
Good luck.
-- Mike Treseler
Article: 78179
Martin wrote:
> Can two PPC's share the same SDRAM and Flash resources?
It is possible, The arbiter logic is not
complicated but but most of the memory
pins would require its own fpga io pin.
-- Mike Treseler
Article: 78180Peter Alfke wrote: > Low-pass filter followed by Schmitt trigger is the only safe bet. > Here is the simplest Schmitt tigger: > Inside the chip, route the incoming signal non-inverted to an other > pin, as output. > Run a 10 kilohm resistor from that output to the input. (Yes, I know, > that forms a latch) Now drive the input from your low-impedance 60 Hz > source through a 1 kilohm resistor. > This gives you 10% of Vcc as hysteresis. For different values, play > with the two resistor valus. I get how the hysteresis and noise filtering works, but don't digital inputs have a minimum rise time spec that would be violated by this approach? Even with the hysteresis network the input would see a very slowly rising signal. Could I make a low/no-precision Khz range oscillator by doing something like this involving a R-C feedback? -JeffArticle: 78181
My plan was to see how they interfaced the MFM drive to the mac. The only thing they did right with MFM drives was make them loud. I love those noises. I will have a bottle of acid in my hands in an hour. :DArticle: 78182
Jeff, Is Peter paying you to post or something? ;-) http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=pa_six_easy Syms. "Jeff Cunningham" <jcc@sover.net> wrote in message news:3aDJd.61$xi.20003@newshog.newsread.com... > > I get how the hysteresis and noise filtering works, but don't digital > inputs have a minimum rise time spec that would be violated by this > approach? Even with the hysteresis network the input would see a very > slowly rising signal. > > Could I make a low/no-precision Khz range oscillator by doing something > like this involving a R-C feedback? > > -Jeff >Article: 78183
I am innocent, but thanks for the URL... Peter AlfkeArticle: 78184
Hello, I designed a module that issues writes and reads to the PLB bus using IPIF interface from the "Create Peripheral" wizard in EDK's XPS. I have issued requests per the guidelines in the PLB documentation (http://www.xilinx.com/bvdocs/ipcenter/data_sheet/plb_ipif.pdf ) and the README.txt that comes with the "Create Peripheral" wizard. Specifically, I have been using the waveforms on pages 116 and 117 as guidelines. The main difference is that my implementation issues single beat writes and reads. Nonetheless, I'm using the write/read requests in a similar manner as the waveforms in the PDF: I'm hold the request signals high until the MstLastAck, MstTimeOut or MstBusError goes high. All the data, BE's, address signals, etc. have been set-up before the request signal is asserted. The problem I'm encountering is that the plb_ipif module in my_plb_master pcore doesn't respond accordingly. For instance, the signals M_request, M_RNW, M_BE do not change appropriately. The slave attachment signals also do not toggle as demonstrated on the diagrams. Is anyone aware of any more documentation about the specifics of the timing for all these signals. With only two pages of waveforms (as compared to the 14+ pages of diagrams for the slave interface), it is difficult to know what I'm doing wrong (assuming the plb_ipif module is bug-free). Even better, does anyone designed plb masters modules? Anything useful gleaned from that experience? Thanks in advance, NNArticle: 78185
"logjam" <grant@cmosxray.com> wrote in message news:1106707306.520985.207230@z14g2000cwz.googlegroups.com... > My plan was to see how they interfaced the MFM drive to the Mac. Well it is your time... > only thing they did right with MFM drives was make them loud. > I love those noises. Noise is wasted power. > I will have a bottle of acid in my hands in an hour. Ouch. I've been playing with Xilinx ISE and manage to compile VHDL versions of the interrupt controller and it seems okay. I didn't know whether to model things on the real Mac PALs or a single all-in-one CPLD. Each has its own pros and cons. The former allows you to 'fill in the blanks' more. The latter avoids confusing interactions. Seeing as you are trying to create replacements for the PALS, it would be more helpful to you to start with the former. I can send you some equations/diagrams if you tell me your email address. Cheers, K. BTW is the CPU running at 16 or 8 MHz?Article: 78186
Jeff Cunningham wrote: > Peter Alfke wrote: > >> Low-pass filter followed by Schmitt trigger is the only safe bet. >> Here is the simplest Schmitt tigger: >> Inside the chip, route the incoming signal non-inverted to an other >> pin, as output. >> Run a 10 kilohm resistor from that output to the input. (Yes, I know, >> that forms a latch) Now drive the input from your low-impedance 60 Hz >> source through a 1 kilohm resistor. >> This gives you 10% of Vcc as hysteresis. For different values, play >> with the two resistor valus. > > > I get how the hysteresis and noise filtering works, but don't digital > inputs have a minimum rise time spec that would be violated by this > approach? Yes. Where I have trialed this, it never gets parts bench testing. Poor noise rejection, and prone to cross talk effects etc - just poor design generally, and if it fails in the field, you are on your own.... > Even with the hysteresis network the input would see a very > slowly rising signal. Correct, it does, until the instant of switching, and then you have a race condition, where the IP stage is thinking about oscillating at some very high frequency, while you wait for what you hope is a clean regenerative edge to arrive at the feedback pin. > > Could I make a low/no-precision Khz range oscillator by doing something > like this involving a R-C feedback? Only if the PLD has hysteresis, and even then, you also need to watch the Icc adder caused by the quasi-linear-input range. I have made VCOs a la 4046 topology, using PLDS, but you need to keep the slew rate above a minimum that dictated ~10MHz a generation ago. The CoolrunnerII and MAX II CPLDs have schmitt pin options. -jgArticle: 78187
This seems to have solved my install problem, and I got both CDs installed, but when I try to run ise, it seem EXTREMEMLY SLOW, in fact I gave up waiting for UI to finish drawing itself...i did get some warnings: szmyd@isengard ~ $ Xilinx/bin/lin/ise Cannot register service: RPC: Unable to receive; errno = Connection refused Cannot register service: RPC: Unable to receive; errno = Connection refused unable to register (registryProg, registryVers, tcp) Wind/U Error (248): Failed to connect to the registry on server isengard OLE API Function OleInitialize is not currently implemented. Further warnings will be suppressed Bertrand Rousseau wrote: > > I had the same problem when I tried to run the installers from the cd. > Then I copied the content of the CDs on my hard disk and the problem > disappeared. > > I succesfully installed ISE 6.3i on a ubuntu distrib and on a gentoo > distrib. >Article: 78188
Steve wrote: > Rudolf Usselmann wrote: > >> >> I've got several boards from Memec-Insight with the Virtex 4 LX-25. >> Unfortunately they are marked "Engineering Samples", which worries >> me. >> >> Can some one from Xilinx explain the difference between Engineering >> Samples and Production devices ? Are there any function/electrical/ >> timing differences ? >> >> Thanks, >> rudi >> ============================================================= >> Rudolf Usselmann, ASICS World Services, http://www.asics.ws >> Your Partner for IP Cores, Design, Verification and Synthesis > > Rudi, > > You must download the XC4VLX25CES errata datasheet, find out what the > short comings are, and decide if they matter for your application and > evaluation. Unfortunately, the Xilinx web site uses session specific > dynamic links, so this is as close as I can get an exact url to point you > to the pdf for the ES. Go to the errata section at the bottom of this > page: > http://www.xilinx.com/xlnx/xweb/xil_publications_display.jsp?category=Publications/FPGA+Device+Families/Virtex-4&iLanguageID=1 > > This datasheet describes some JTAG specific issues that may be the root > cause of your other post. More power requirements during init -- check > your power supplies! > > Thanks, Steve What is the likelihood that the "errors" in the errata will be fixed for the production devices for the V4LX25 ? rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 78189
Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote: > The 4VLX25 has an issue with the timing of the last bit shifted out on > TDO in that TDO tristates too early. This results in the final bit > being misread, typically as a 1. Sadly, the last bit in the device > status register is the CRC bit and this results in the the warning > message you see. This issue is detailed in the device errata > > http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?BV_SessionID=@@@@1670514069.1106675756@@@@&BV_EngineID=cccfadddjhehjdfcflgcefldfhndfmo.0&category=-1210882&ipoid=24318118&iLanguageID=1 > > along with some possible work-arounds Thanks Niel, got the doc. Does this explain the 52 mismatches I get during compare as well ? Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 78190
Peter Alfke wrote: > Let me give a more generic answer about ES. > "Engineering Samples" is really an inappropriate name, I would call it > "Early Silicon" :-) > The devices are thoroughly tested and perform according to the data > sheet, as amended by an errate sheet. By definition, ES parts have an > errate sheet (at best it says:"NO ERRATA") > We call them ES because some long-term reliability qualification tests > have not yet been completed. We might also have to change some masks to > fix the errata problem(s). > We therefore suggest that ES parts not be used in your final > manufacturing. > But any idea that ES parts are flakey, not completely tested, or > unreliable is dead WRONG. > Hope that helps. > Peter Alfke, Xilinx Applications Peter, According to the errata there seem to be some serious problems with some of the ES parts. I would assume Xilinx would strive to fix those ? Or am I wrong ? Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 78191
> Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> > wrote: > >> The 4VLX25 has an issue with the timing of the last bit shifted out on >> TDO in that TDO tristates too early. This results in the final bit >> being misread, typically as a 1. Sadly, the last bit in the device >> status register is the CRC bit and this results in the the warning >> message you see. This issue is detailed in the device errata >> >> > http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?BV_SessionID=@@@@1670514069.1106675756@@@@&BV_EngineID=cccfadddjhehjdfcflgcefldfhndfmo.0&category=-1210882&ipoid=24318118&iLanguageID=1 >> >> along with some possible work-arounds > > > Thanks Niel, got the doc. > > Does this explain the 52 mismatches I get during compare as well ? > > Thanks, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and Synthesis Niel, unfortunately the work around does not work on Linux. Bit Gen Core dumps (Segmentation fault) when specifying the option for serial configuration. Are there any other solutions ? Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 78192
The CPU runs at 8MHz. My e-mail address is g1c2c@sto4ck5ly.com There are no numbers in my e-mail address. Take those out. I did not do very well with the acid tonight. It was fun while it lasted. The acid was way too diluted to work at a decent rate, but strong enough to catch fire (nevermind). So finally I took one of them over to a beuhler metallurgy sanding disc and gave it a polish down to the silicon. Most of the data was "wiped" off, but I was able to see a dozen microns by 3/16 or so. Doesn't seem as fun as it once did...well, at least I had fun! :) I will start prooving the logic once I get that analyzer. I've needed an excuse to get one for a long time. I would have killed (well, not really) to get one back when I interfaced a hard drive to the AVR. What would you suggest as a beginning kit on CPLDs? Something from Altera or Atmel? I'd also like to get a decent EEPROM/GAL/PAL device too. Any suggestions on that? I have a buddy in the digital x-ray world who uses an altera between analog to digital convers and a microcontroller, so if I went with an altera enviornment I might be able to get free phone support. ;) I've got the 6 PALs desoldered, and they're not going to get acid treated, so I'll put them on the breadboard and proove the logic with them. Did you ever see the equations posted at AVR-Freaks? I have the Eagle schematic program and CircuitMaker 2000 at work. But I don't like Circuit maker at all. I can't find any way to import schematics into Eagle either. I'm working on a version of the macintosh schematic in Eagle, and will probably do most of my stuff in Eagle just because its free and available for many platforms. Is a "5380 SCSI chip" emulator too much for an inexpensive CPLD? The goal being an IDE controller that looks like a 5380. Last week on tuesday I didn't even know what PAL stood for. Steep learning curve, but with time I'll understand all this. I can bit-bang it with a microcontroller, but this might be an opportunity to learn about those CPLDsArticle: 78193
> I would suggest starting out with someone else's board first, unless you > have a whole lot of free time on your hands. I used the Avnet 2VP20 board, > and it seems to work reasonably well, and is also reasonably priced. It > comes with a complete Linux development environment. For what it is worth, > it is using a 16MB Flash, a 32MB SDRAM, and a 2MB SRAM (Linux doesn't use > the SRAM), all 32 bits wide. And it comes with both ethernet and serial > interfaces, both of which work under Linux. Free time I do not have. This is for future PPC implementation on a new design that won't use them initially. I think I'll just place a high-speed I/O expansion connector on the board with enough (and the proper) resources to support a nice amount of DDR2 and Flash. The final configuration can then be addressed when that mezzanine board is designed. I just got done looking at that eval board's documentation as I read your post. It is a good starting point. -MartinArticle: 78194
It looks like google took my e-mail address out. :( send stuff to gcc-at-stockly-dot-comArticle: 78195
Trying to port my latest design from a SpartanIIe-300 to a SpartanIII-200 I get the following warning: "WARNING: Place 119 - Unable to find location. SLICEM component <net name> not placed". This leads to : "ERROR: Place 120 - There were not enough sites to place all selected components." Looking at the device utilization summary, it reports that 678 of 960 SLICEMs are used. What can I do to make this problem go away? I'm using an FPGA development board, so it is a little hard to assign pins differently. Most of the SLICEM warnings are in regard to an internal FIFO. I have regenerated this core without things getting any better. Greetings, Børge StrandArticle: 78196
logjam wrote: <snip> > What would you suggest as a beginning kit on CPLDs? Something from > Altera or Atmel? Atmel still support SPLD and 5V ATF16V8C / ATF22V10CQ devices, Altera and Xilinx do not. Atmel's tools also allow test vector creation, so you can verify BOTH the removed PLDs, and your new candidate ones, BEFORE you try plugging into the museum motherboard, which you probably do not want to fry.... So I'd start with Atmel, and keep pin-compatible PLDs, to first prove you have the logic right. The modern ones should be lower power, and faster than the old ones. -jgArticle: 78197
Neiko wrote: > This seems to have solved my install problem, and I got both CDs > installed, but when I try to run ise, it seem EXTREMEMLY SLOW, in fact I > gave up waiting for UI to finish drawing itself...i did get some warnings: My box runs usually Seti on a nice level of 19. But Xilinx' GUI tools are affected by this. That means ISE, Floorplanner and FPGAEditor are very slow if Seti runs, look for tasks consuming performance. > > szmyd@isengard ~ $ Xilinx/bin/lin/ise > Cannot register service: RPC: Unable to receive; errno = Connection > refused Cannot register service: RPC: Unable to receive; errno = > Connection refused unable to register (registryProg, registryVers, tcp) > > Wind/U Error (248): Failed to connect to the registry on server isengard > OLE API Function OleInitialize is not currently implemented. Further > warnings will be suppressed OLE is Object Linking and Embbeding, IMHO only available under Windows or Wine. Bye TomArticle: 78198
Nju, I've been designing master PLB master modules using the PLB IPIF for quite a while now and, like in your case, the only think I could rely on were the two diagrams you referreded to in your message and the simulation results. I have to say that I did not follow the design flow suggested by Xilinx because I just instatiated the PLB IPIF inside my code and I did not use the Peripheral wizard. I think that the timing reported in those two diagrams is not correct becasue the signls Bus2IP_Cs and Bus2IP_CE are always asserted at the same point in time but the signals Bus2IP_RdCe, Bus2IP_WrCe, Bus2IP_RdReq and Bus2IP_WrReq, althought are always asserted at the same time, are alwas at least one clock cycles delayed respect to the previous two. To be honest, I do not think that that module is bug-free but so far it seem to behave correctly in our application. If you can be more specific about your problem maybe I can help you a little more. Regarding the documentation, I do not know if something more detaild exist. Regards, Andrea SabatiniArticle: 78199
I did not had this problem. But maybe you should look at /etc/hosts to
see if you have a line like
127.0.0.1 localhost.localdomain localhost isengard
cause it seems that the GUI can't connect to the server (it can't
resolve 'isengard'). Note that I'm completely unsure about this, I'm
just giving you some hints. Furthermore I suppose you are running on
your PC ('localhost') and not on a distant server.
Oh, and when I start XPS it takes always a long time (about 2 or 3 min)
before the GUI show up, but once started, the interface is quite
reactive, so it doesn't cause that much trouble. During this time my
computer shows a 100% CPU state also. And sometimes during the use of
other EDK tools the GUI seems to freeze, but after waiting a little it
comes back.
Neiko wrote:
> This seems to have solved my install problem, and I got both CDs
> installed, but when I try to run ise, it seem EXTREMEMLY SLOW, in fact I
> gave up waiting for UI to finish drawing itself...i did get some warnings:
>
> szmyd@isengard ~ $ Xilinx/bin/lin/ise
> Cannot register service: RPC: Unable to receive; errno = Connection refused
> Cannot register service: RPC: Unable to receive; errno = Connection refused
> unable to register (registryProg, registryVers, tcp)
>
> Wind/U Error (248): Failed to connect to the registry on server isengard
> OLE API Function OleInitialize is not currently implemented. Further
> warnings will be suppressed
>
>
> Bertrand Rousseau wrote:
>
>>
>> I had the same problem when I tried to run the installers from the cd.
>> Then I copied the content of the CDs on my hard disk and the problem
>> disappeared.
>>
>> I succesfully installed ISE 6.3i on a ubuntu distrib and on a gentoo
>> distrib.
>>
Site Home Archive Home FAQ Home How to search the Archive How to Navigate the Archive
Compare FPGA features and resources
Threads starting:
Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z