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Allan Herriman wrote: > Are you aware of the effects of clock jitter on ADC performance? You > should check with your system designers about this effect, otherwise > you may get "sub-optimal" results, i.e. it won't work. [snip] > It's possible that the divide by 13 counter would be better, as it > generates no jitter. Can you tolerate the frequency error? > > Regards, > Allan If you can't live with either 41 ns jitter or the frequency error you could cascade two DCM's using 8/25 and 6/25 respectively for CLKFX_MULTIPLY/CLKFX_DIVIDE. The intermediate frequency would be 7.68 MHz. which is well below the output frequency specification for CLKFX even in low frequency mode, so you'll need to really set the first CLKFX_DIVIDE to 1 and then externally divide by 5 to generate the input to the second DCM. I don't have enough experience with Spartan 3 to tell you how much jitter you will get this way, but if the second DCM actually locks, I can't believe it's anywhere near 41 ns.Article: 78101
In that case, if the output of the 16 bit multiply is result(15 downto 0), your output should be result(15 downto 8) incremented if result(7) is a '1'. Truncation is usually bad; rounding is much nicer! Cheers, Syms. "SD" <sourabh.dhir@gmail.com> wrote in message news:1106605358.458339.77730@c13g2000cwb.googlegroups.com... > I plan to have it "unsigned". >Article: 78102
Dan, Yep, this is what I do for clipped sine-wave TCXOs on my Xilinx FPGAs. I use the input delay in spare unbonded IOBs for the delay. Works a treat, and no Schmitts required! Cheers, Syms. "Dan K" <danielgkNOSPAM@voomtech.com> wrote in message news:41f57d5c$0$2164$a1866201@visi.com... > > What else do you have in the pld? A "normal" clk? some extra ff's? I > would set ff Q1 when 60 hz = '1' and QUAL = '0' and clear ff Q1 when 60 hz > = '0' and QUAL = '1' where QUAL is ff Q1 delayed by a ms or so using the > "normal" clk and some ff's. Use ff Q1 as your 60 hz global clk and you > should be good to go. If you do this you can probably lose the rf choke > too. >Article: 78103
Is the schematic of the unitron close enough to the mac 512k that we can use Apple's schematic? At least most of it is typed Portuguese, I can fumble my way through google on that. ;) The part where you talk about turbo, does that section have anything to do with the 23% speed improvement mentioned on the unitron page?Article: 78104
i know Fedora is not officially supported but, has anyone had the following problem when trying to install ISE 6.3i : [root@moose cdrom]# ./setup Wind/U Error (294): Unable to install Wind/U ini file (/media/cdrom/data/WindU). See the Wind/U manual for more details on the ".WindU" file and the "WINDU" environment variable. Wind/U X-toolkit Error: wuDisplay: Can't open display ************ setup done! *************** [root@moose cdrom]# echo $DISPLAY :0.0 as you can see, i start the setup and it cant seem to find the correct display i can run other X apps fine though... any one have any ideas? -- Geoffrey Wall Masters Student in Electrical/Computer Engineering Florida State University, FAMU/FSU College of Engineering wallge@eng.fsu.edu Cell Phone: 850.339.4157 ECE Machine Intelligence Lab http://www.eng.fsu.edu/mil MIL Office Phone: 850.410.6145 Center for Applied Vision and Imaging Science http://cavis.fsu.edu/ CAVIS Office Phone: 850.645.2257Article: 78105
EPCS1 is equivalent to M25P10 from ST, and EPCS4 is equivalent for M25P40. Cost is about $1.20 and $1.80 respectively. "Jedi" <me@aol.com> wrote in message news:X4uHd.276$vl1.143@read3.inet.fi... > Someone knows roughly the prices for EPCS1 and EPCS4 at 100 pieces? > > I know I can lookup at www.ebv.com but I see nothing mentioned about > at which quantities those prices are... > > > rick >Article: 78106
Hi Geoffrey, Geoffrey Wall wrote: > i know Fedora is not officially supported but, has anyone had the following > problem when trying to install ISE 6.3i : > > [root@moose cdrom]# ./setup > Wind/U Error (294): Unable to install Wind/U ini file > (/media/cdrom/data/WindU). > See the Wind/U manual for more details on the ".WindU" file and the "WINDU" > environment variable. > Wind/U X-toolkit Error: wuDisplay: Can't open display > > > ************ setup done! *************** > > [root@moose cdrom]# echo $DISPLAY > :0.0 > > > as you can see, i start the setup and it cant seem to find the correct > display > i can run other X apps fine though... > any one have any ideas? Try "export LD_ASSUME_KERNEL=2.4.7" before you run the setup util. Regards, JohnArticle: 78107
> Is the schematic of the unitron close enough to the mac 512k that we > can use Apple's schematic? Except for different pin names, it should be exactly the same. For example: Apple names my names 16M SYSCLK 8M PCLK M/VID S1 /RAM /RAMEN /ROM /ROMEN /AS /AS /UDS /UDS /LDS /LDS /CAS0 /CASL /CAS1 /CASH /RAS /RAS TC VCLK 1M Q2 4M Q1 2M S0 /DTACK /DTACK > At least most of it is typed Portuguese, I can fumble my way through > google on that. ;) Here is a quick translation, probably better than what Google or Babelfish could do: http://www.merlintec.com/download/unitronreport2and3.txt > The part where you talk about turbo, does that section have anything to > do with the 23% speed improvement mentioned on the unitron page? Exactly, though I only compare with the original and not SE/Classic timing.Article: 78108
For a while- I was throwing it at the junior engineers in the office whenever they walked by. With it unfolder- it is much harder to harass the June grads.Article: 78109
Look up the Docs for XFLOW. Xilinxs' command line utilities. Cheers "Rick Thompson" <nospam@nospam.com> wrote in message news:tshav0hht1185ajvg9pfja9kottbdct7p5@4ax.com... > Hi all - > > I'm just doing my first device (a Spartan 3S200 or 400) after a break > of 5 years, and I'd like to do a scripted flow (I've done this > previously with 4K&Virtex/Leonardo/Foundation, running > par/map/ngdbuild/etc from a makefile). Can anyone tell me if this is > possible with the free Webpack tools, or will I have to buy something? > Is the free XST scriptable? Is XST any good? > > Finally, any ideas on whether the flow has changed radically since > 2000, or should I just be able to take up where I left off? > > Cheers - > > Rick >Article: 78110
Low-pass filter followed by Schmitt trigger is the only safe bet. Here is the simplest Schmitt tigger: Inside the chip, route the incoming signal non-inverted to an other pin, as output. Run a 10 kilohm resistor from that output to the input. (Yes, I know, that forms a latch) Now drive the input from your low-impedance 60 Hz source through a 1 kilohm resistor. This gives you 10% of Vcc as hysteresis. For different values, play with the two resistor valus. Costs one extra pin and two resistors, saves lots of headaches. Peter Alfke, Xilinx ApplicationsArticle: 78111
> As I mentioned in that page, after the job was done I gave Unitron all > the material I had created without keeping a copy for myself (that was > one of the terms of our contract). Ah, I see. I've just finished a first draft of re-drawing the Mac circuit in Orcad. It is just to get an idea of how it works. The ROM/RAM/CPU sections are not hard to fathom. There are a load of multiplexers for CPU/VDU/audio access, not so simple but you can see what it is up to. Most complexity lies in the PALs/IWM, but you can tell which PAL pins are definitely not outputs (those on the left of the chips. Incidentally, even if we do manage to recreate the PAL equations, how will we recreate the IWM? If it is only relevant to disk access, we can live without it because floppies are no longer an essential medium. People backup to CD/DVD, and use memory cards instead of floppies. > This morning I scanned it converting each page into a (very large) PDF I've managed to get an idea of what things are going on. Perhaps I could make a web page of my own scribblings? I don't know if I can be bothered to recreate the Mac, because the Atari ST is better (colour output, TV display, games). But maybe someone else is and would find my notes helpful. > For it to be of any use to people I would have to translate the > comments and report from Portuguese to English That would be nice, but another poster seems to have translated some of it already. I will try to collect a few notes for the web site. Thanks for doing the scans. History and I thank you!Article: 78112
I'd like to see those schematics, if you wouldn't mind. Something that Eagle can open? If you would like, you can post your work on a web board I'm working on. I have a ton of information and a few interested people. I also see the need to move away from the fpga list once the on topic pal discussion ends. ;) I bought an 18 channel logic analyzer that is capable of over 128k-1.5M samples depending on the activity. By this weekend I will have a few dozen captures of the PAL input/output in a form that can be downloaded. The software that comes with the logic analyzer is free, so you can view/manipulate the data pretty good. I also bought a few Mac 512k motherboards off ebay for $9 to get extra PAL chips from. On Tuesday I will be decapsulating/delidding/decapping the chips and photographing them with my digital camera. I hope that the PALs look the same on the silicon layer as they do on the datasheet. ;) I expect to have pictures of at least one PAL this weekend. 32x64 at the right magnification should only take up a few pictures. For me, every part of this project is an adventure. I will be attempting to decap the ICs by covering their bellies with heat sink compound, heating them on a hot plate to 130*C, and then dripping nitric acid on to them. :) I've also made a few processor replacement PCBs that allow a new 68HC000 PLCC68 to replace the 68000 DIP64. They had to be custom carriers, because of the pinout change and count. So I put 64 pins on the carrier and a signal name next to each pin. I also threw in a mac logo in the traces on the top layer. ;) I have an extra carrier if anyone is interested... Another benefit of the new 68HC is its a 16MHz model. ;) Sounds like a fun project. Better to halfway through something and stuff it in the corner than watch prime time TV. ;) GrantArticle: 78113
Am Mon, 24 Jan 2005 19:26:03 -0500 schrieb Geoffrey Wall: > Wind/U X-toolkit Error: wuDisplay: Can't open display > > > ************ setup done! *************** > > [root@moose cdrom]# echo $DISPLAY > :0.0 > Try: export DISPLAY=:0 or export DISPLAY=hostname:0.0 It seems, Wind/U has problems parsing ":0.0" correctly. Greetings, JanArticle: 78114
Hi again, I'm thinking about buying one of Xilinx' Platform USB cables. However, it says in answer record 20429: "Windows XP SP2 is not an officially supported environment." I guess that means Xilinx just hasn't tested it in this environment (or at least they hadn't last time the answer record was updated), hence they won't guarantee it will work. Has anyone successfully used it or encountered any problems? -- cu, SeanArticle: 78115
The issue with the IWM is confusing. I'm not sure how the Plus roms would handle not having the IWM or 5380 SCSI chip. I can not find any 5380 chips on the market. Zilog has a Z53C80 that is in Life-Time production, but they have no stock and neither do any of their distributors. The 5380 could probably be duplicated with 2 or 3 75MHz PICs. Sorry, but I have no idea what a FPGA is except what the letters stand for. Maybe we could make a 5380 in an FPGA, but then it wouldn't be through hole .1" spaced... Can we get a DIP / PLCC fpga with enough hourse power to do the 3MHz SCSI link? With the SCSI chip it would be pretty easy to fake a SCSI drive with a microcontroller and attach some flash. Another solution would be emulating the IWM and using the HD20 method of putting 20MB on the disk drive port. The only problem with that is the 400-500kbit transfer rate on those ports. :( There was the suggestion of putting the whole plus into a single FPGA. That sounds neat, but the theory is out of my grasp at the moment. After I get a better understanding of the computer and possibly some experience with FPGAs from the project...Article: 78116
Just select the WYSIWYG synthesis style in the ASSIGNMENT, LOGIC OPTIONS menu.Article: 78117
Peter Alfke wrote: > Low-pass filter followed by Schmitt trigger is the only safe bet. > Here is the simplest Schmitt tigger: > Inside the chip, route the incoming signal non-inverted to an other > pin, as output. > Run a 10 kilohm resistor from that output to the input. (Yes, I know, > that forms a latch) Now drive the input from your low-impedance 60 Hz > source through a 1 kilohm resistor. > This gives you 10% of Vcc as hysteresis. For different values, play > with the two resistor valus. > > Costs one extra pin and two resistors, saves lots of headaches. > Peter Alfke, Xilinx Applications or use a PLD with Hysteresis inbuilt ? or, for the low impedance buffer you mention, choose a single gate device like 1G14/1G17 ? If power consumption mattered, the above R-R schmitt is sub optimal, but I guess with a 9572 who cares... -jgArticle: 78118
On 24 Jan 2005 09:57:37 GMT, ptkwt@aracnet.com (Phil Tomson) wrote:
>I'm working on a program which will generate some VHDL or Verilog code
>to do some arithmetic operations. The code generated should be able to be
>synthesized into various FPGA families (an option to the code generating
>program). The function is something along the lines of:
>
> threshold= -15.0 #typically between -20.0 and -10.0 depending on problem
> X = vector of numbers in the range of -infinity to 0.0
> Y = vector of numbers in the range of -n to +n
> accumulator = 0
> foreach x in X, each y in Y
> if x > threshold #typically -20.0 to -10.0 depending on the problem
> accumulator += y*exp(x)
> end
> end
> answer = accumulator + bias
The lower limit of X sounds a little difficult to synthesise :-)
>Currently I've got a lookup table for the exp(x) function which works fine
>for this application since the values of x will always be negative and we
>canb disregard values of x which are less than some threshold (since for
>our purposes the result is essentially 0). I'm simulating the lookup
>table using a case statement in a programming language called Ruby. I can
>then replace the exp() function with the lookup table version in the code
>and compare results. So far the lookup table seems very manageable - 64
>entries seems to work just fine. I need to do a bit more research, but it
>seems like 256 entries or less should work for the majority of problems.
OK, but of course you need to be very careful that you understand all
the issues about precision - too few entries in your lookup table
will give significant errors in some cases. For well-behaved
functions such as exp() it's sometimes appropriate to use a fairly
coarse lookup table and then do linear interpolation between the
entries. Make each LUT entry hold two values: the value at the
chosen point, and the gradient from there to the next point.
(Hey, for exp() they're the same!!!) Then split the binary x
value into two fields: the most significant bits address the LUT,
and the less significant bits are multiplied by the gradient
and added to the LUT first-order result.
>Now I need to start migrating more towards a hardware implementation. So
>I need some way to represent the values from the exp() function in binary.
>I'm looking for advice on how to scale these numbers. I'm currently
>thinking that given 8 bits (though the number of bits will probably be
>variable depending on the application and the size of the FPGA) I have a
>range of 0 to 255, so exp(0) (which is 1.0, of course) could be
>represented by 255 and exp(threshold) could be represented by 0. Then
>multiply this integer (between 0 and 255) by the y value which is itself
>scaled, and add (or subtract, depending on the sign) the result to/from
>the accumulator. At this point, I suspect that I would need to disregard
>some number of LSBs in the accumulator (because the x values were
>essentially scaled up to be greater than 0).
Be somewhat wary of simply dropping unwanted LSBs. Whenever you
do that, you are introducing a bias into the result of (on average)
a 1 in the most significant lost bit. This is usually harmless on
a single value, but if you're accumulating many values then the
truncation errors can stack up. Consider rounding instead: add
a 1 in the most significant lost position, and then drop the LSBs
(or, if you prefer, increment the truncated result if the most
significant dropped bit is 1).
>Am I on the right track?
Yes indeed. You are, however, mixing together two slightly different
(but closely related) ideas and it might be a good idea to separate
them.
First, you are considering scaling all the numbers in the problem
(scaling your exponent by 255). This is of course entirely
reasonable if (1) you can get the table into that form easily,
and (2) you can "un-scale" the final result before making use of it.
Second, you are quite properly thinking about how to represent
non-integral values as bit patterns in hardware. Such bit
patterns of course end up looking rather like integers.
You then need to worry about dealing with rounding and overflow
conditions, because your hardware has a limit on the number of
bits at its most significant and at its least significant end.
Once again you are obviously aware of this. The usual
jargon is "fixed point arithmetic". I'm sure you can find
information on this in all kinds of places, but I wrote something
about it a year or two back when I built my own fixed-point
VHDL library - you can read my notes by downloading the stuff at
http://www.doulos.co.uk/knowhow/vhdl_models/fp_arith/
It's a reasonable "beginners' guide" to fixed-point binary
arithmetic. However, please DON'T use the fixed-point package
you'll find there, for two reasons:
(1) it's not very well tested, and I found a horrible bug in
it a couple of months ago
(2) there's a proposed standardised fixed-point package,
written by David Bishop, now available at
http://www.eda.org/vhdl-200x/vhdl-200x-ft/packages/files.html
(look for the item "IEEE.Fixed_Pkg).
Finally, it sounds as though you've done all the prototyping in
Ruby so this probably doesn't help, but... if you use something
like Matlab then you would be able to simulate all the effects
of limited bit precision without too much trouble.
Hope this helps a bit.
--
Jonathan Bromley, Consultant
DOULOS - Developing Design Know-how
VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services
Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com
The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
Article: 78119www.fpga4fun.com wrote: > EPCS1 is equivalent to M25P10 from ST, and EPCS4 is equivalent for M25P40. > Cost is about $1.20 and $1.80 respectively. > I already use M25PXX for Cyclone..that's old news (o; And this wasn't the original question anyway (o; rick > > "Jedi" <me@aol.com> wrote in message news:X4uHd.276$vl1.143@read3.inet.fi... > >>Someone knows roughly the prices for EPCS1 and EPCS4 at 100 pieces? >> >>I know I can lookup at www.ebv.com but I see nothing mentioned about >>at which quantities those prices are... >> >> >>rick >> > > >Article: 78120
is there a possibility to create bidimensional array, and do things such as : signal foo : STD_LOGIC_???(1 downto 0, 7 downto 0); signal foo1 : STD_LOGIC_VECTOR(7 downto 0); [...] foo(0) <= foo1; -- Ceci est une signature automatique de MesNews. Site : http://www.mesnews.netArticle: 78121
There is an example for a bidim array declaration : type bidim_array is array (width-1 downto 1, width-1 downto 0) of std_logic; signal MEM : bidim_array; Moti.Article: 78122
I've got several boards from Memec-Insight with the Virtex 4 LX-25. Unfortunately they are marked "Engineering Samples", which worries me. Can some one from Xilinx explain the difference between Engineering Samples and Production devices ? Are there any function/electrical/ timing differences ? Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 78123
Hi all. I am working on a project which is targetted on a Xilinx Virtex2Pro xc2vp30. To debug the logic that I am developing I sometimes need to modify the code that is executed by one of the two PPC available inside the fpga. The code is completely stored in internal BRAM so if I change it I need to update the bitstrem of the device and to me this seems quite easy: just press the button "Update Bitstream" in Project Studio (version 6.3). But, since the file used to configure the fpga is an hex file created by Project Navigator (version 6.3.03i) every time a software change is required I am forced to re-generate the hardware which takes at least 40 minutes. I thought that after having updated the bitstream in Project Studio it would have been enought to select the icon "Generate PROM, ACE or JTAG File" in Project Navigator and choose "Open without Updating" but this solution generated a completely not working version of the hw (verified with ChipScope), no matter of the software changes that were made. I already looked into the documentation provided with the tools, I searched on Xilinx website and on the net but I did not find any answer to my problem. Have someone already faced this issued? Did he/she solved it? Any suggestion is really appreciated. Thanks in advance, Andrea SabatiniArticle: 78124
Hi ! Impact is reporting some strange errors when attempting to program a xc4vlx25. First I get "Error in status register CRC bit is NOT 0", and than during verify I get 45-52 mismatches, seems to be different from trial to trial. Tried several boards, seems to be persistent ... Any ideas what might be causing that ? Oh, yes I am using Par. Cable 4, and ISI 6.3.03i. Thanks, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and Synthesis
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