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I need some schematics (pcb) with some fpga on pci board...everything...
Some links would be enough.
Thanks,
Article: 78201On Tue, 25 Jan 2005 18:11:08 -0500, Ray Andraka <ray@andraka.com> wrote: >A possibility is to do it with a recursive call to a component, one call >for each level of the >pyramid. Your code needs an end condition in it to terminate the >recersive calls. A long >while back, I did some adder trees this way, and it broke some of the >tools (notably >Synplify). I am pretty sure the bug that caused it to break is now >fixed, although I have >not checked it in some time. Quartus is still broken for recursive component instantiation AFAIK, and I am pretty sure that some other tools have similar problems. Recursive instantiation badly confuses the automatic hierarchy traversal machinery in Xilinx ISE, so that you have to choose the top-level design by hand, but I seem to remember that the synthesis tool itself is OK with it. -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL, Verilog, SystemC, Perl, Tcl/Tk, Verification, Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, BH24 1AW, UK Tel: +44 (0)1425 471223 mail:jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.Article: 78202
Ray, I managed to do the recursive call but my problem was in the declaration part I didnt knew how to the declare the signals as I mentioned in the begining of the thread. eventually I took Nicolas Matringe advise and declared a complete bidim array (width-1,width-1) - that is actually twice the size I needed and the synthesizer optimized half of array for me. the code relevant section is attached.. and it's working too ;-) BTW - I did it in order to create a delay network for an 32 bit NCO design at 300MHz. Regards, Moti. signal c : std_logic_vector (width-2 downto 0); signal accumulator_reg : std_logic_vector (width-1 downto 0); signal b_delayed : std_logic_vector (width-1 downto 1); type bidim_array is array (width-1 downto 1, width-1 downto 0) of std_logic; signal reg : bidim_array; begin process (clk,resetn) begin if resetn = '0' then reg <= (others => (others => '0')); if rising_edge(clk) then--elsif rising_edge(clk) then for n in 1 to width-1 loop reg (n,0) <= b(n); end loop; for i in 2 to width-1 loop for j in 1 to i-1 loop reg(i,j) <= reg(i,j-1); end loop; end loop; end if; end process; process(reg) begin for i in 1 to width-1 loop b_delayed(i) <= reg(i,i-1); end loop ; end process;Article: 78203
One major difference between Spartan-IIE and Spartan-3 is that Spartan-3 only supports 1 out of the 2 LUTs within a Slice as a memory element. Your problem is probably due to either using a macro element that has a fixed relational structure or constraints that relatively lock memory elements. I would suggest rebuilding the macro for Spartan-3, or if using constraints for this structure, remove the Slice location constraints. -- John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "B?rge Strand" <borge.strand@gmail.com> wrote in message news:187469a2.0501260029.1a4cc729@posting.google.com... > Trying to port my latest design from a SpartanIIe-300 to a > SpartanIII-200 I get the following warning: > > "WARNING: Place 119 - Unable to find location. SLICEM component <net > name> not placed". > > This leads to : > "ERROR: Place 120 - There were not enough sites to place all selected > components." > > Looking at the device utilization summary, it reports that 678 of 960 > SLICEMs are used. > > What can I do to make this problem go away? I'm using an FPGA > development board, so it is a little hard to assign pins differently. > Most of the SLICEM warnings are in regard to an internal FIFO. I have > regenerated this core without things getting any better. > > > Greetings, > > > Børge StrandArticle: 78204
Hi I had a similar problem when using a black box (ROM) during synthesis and an edif netlist for the black box during P&R. The ROM was build for a different target device (virtex II instead of Spartan III) When I parsed the edif netlist I could see placement directives which could not be solved for the spartan III So my suggestion is to either recreate this black box for the required device or remove all placement directives from the edif. HTH Ansgar -- Attention please, reply address is invalid, please remove "_xxx_" ro reply "B?rge Strand" <borge.strand@gmail.com> schrieb im Newsbeitrag news:187469a2.0501260029.1a4cc729@posting.google.com... > Trying to port my latest design from a SpartanIIe-300 to a > SpartanIII-200 I get the following warning: > > "WARNING: Place 119 - Unable to find location. SLICEM component <net > name> not placed". > > This leads to : > "ERROR: Place 120 - There were not enough sites to place all selected > components." > > Looking at the device utilization summary, it reports that 678 of 960 > SLICEMs are used. > > What can I do to make this problem go away? I'm using an FPGA > development board, so it is a little hard to assign pins differently. > Most of the SLICEM warnings are in regard to an internal FIFO. I have > regenerated this core without things getting any better. > > > Greetings, > > > Børge StrandArticle: 78205
> The CPU runs at 8 MHz. Okay. The master clock source (16 MHz) seems unclear from the schematic. I can't see an oscillator module or even a quartz crystal. Easily produced though. > acid was way too diluted to work at a decent rate I think you should grind down most of the way, then just etch the final thin bit. Otherwise you will be there all month. > I will start proving the logic once I get that analyzer. I've needed > an excuse to get one for a long time. I would have killed (well, not > really) to get one back when I interfaced a hard drive to the AVR. > What would you suggest as a beginning kit on CPLDs? Something from > Altera or Atmel? I have the Xilinx ISE for my FPGA work, and it also compiles for their CPLD chips (the 9500 series). I just bought a few in PLCC44 packages, you can put sockets on whatever 0.1" protoboard you have. You'll need a programming dongle for your printer port. I use the one that came with my BurchEd FPGA dev kit. I'm sure they'll sell you the dongle alone if you want. > I'd also like to get a decent EEPROM/GAL/PAL device too. A programmer? I managed to get away without one. I got my project to run BASIC from ROM inside the FPGA, then run a bit of code to program the Flash. > I've got the 6 PALs desoldered, and they're not going to get acid > treated, so I'll put them on the breadboard and prove the logic with > them. The 16L8 should be a doddle, the registered ones less so but it helps to have a clue what is going on. > > Did you ever see the equations posted at AVR-Freaks? What where those for? > Macintosh schematic in Eagle Fair enough. Can Eagle print to virtual (pdf) printers? Most Eagle schematics I see are image files. > Is a "5380 SCSI chip" emulator too much for an inexpensive CPLD? A mate of mine implemented drives for it and he said it was a really badly implemented chip. If it wasn't happy with the sequence of programming events it would lock up so he had to modify the design to have an address that would trigger a hardware reset, the only thing that would unlock it. It is a 40 pin chip but it didn't seem to have much in it. CPU interface pins, buffered SCSI pins, and a few state machines (that locked up when confused). It was an industry standard SCSI chip though. > goal being an IDE controller that looks like a 5380. Sounds a very bad idea. You are going to need a micro to read data in one low level format, convert it into a completely different low level format, then the 68K has to turn that back into data. It is far more sensible to get the 68K to use IDE directly. And before you think "Aw no, that sounds like loads of software work", bear in mind that it will be so writing software for a micro to do it for you. Though I note you have done AVR to IDE before. The 68K bus width matches IDE.Article: 78206
Is there any software I can download for use in MATLAB/Simulink that I can download for free for testing / simulating FPGA from Xilinx ? I am doing my masters degreee thesis. -- John David BirchArticle: 78207
Hello, I want to connect a SDRAM (single data rate) to a spartan 2e FPGA. Are there some special recommendations about the attribution of the pins? Thank you in advance smuArticle: 78208
Peter Alfke wrote: > Now, if you are a lawyer... Then I would not care at all and just make something up ;-) Kolja SulimmaArticle: 78209
smu wrote: > Hello, > > I want to connect a SDRAM (single data rate) to a spartan 2e FPGA. > Are there some special recommendations about the attribution of the pins? > > Thank you in advance > > smu I do this all the time in Spartan 2e with the lowest speed grade and have no problem running 100 MHz with pinout selected before the code was designed (i.e. the board was designed before the FPGA code). Really you have to look at the speed you want to run and make sure you can support the setup and hold requirements of the SDRAM parts after the board is routed. I usually pick the pinout to simplify board routing, because in the end shorter traces lead to easier timing constraints. If you want to run the SDRAM at its rated frequency (usually at least 143 MHz) you need to be even more careful with layout. Also my designs were generally streaming video, so I didn't care about latency through the memory, only throughput. You will have trouble in any design that doesn't use IOB flip-flops in both directions for data and output IOB flip-flops on the control signals. Remember to use fast slew on the outputs to reduce clock to out timing. This also presents a challenge for quad flat packs which exhibit significant ground bounce with multiple fast outputs switching. I would recommend BGA packaging, especially if you have a wide data bus. If you need to use a PQ package for some reason, try to distribute the data bus over multiple banks to reduce ground bounce. This will present a routing challenge and may reduce the usable frequency of the final design.Article: 78210
Hi all, I need to find the xilinx EDK reference design named opb_core_ssp0_ref the "user core templates reference guides" document is refering to it but I can't find it in my EDK root or anywhere else. If someone can help me here I will be glad.. Thanks in adnance, Moti.Article: 78211
Rudolf Usselmann wrote: > Steve wrote: > >> Rudolf Usselmann wrote: >> >>> >>> I've got several boards from Memec-Insight with the Virtex 4 LX-25. >>> Unfortunately they are marked "Engineering Samples", which worries >>> me. >>> <SNIP> > This datasheet describes some JTAG specific issues that may be the root > cause of your other post. More power requirements during init -- check > your power supplies! > <SNIP> > What is the likelihood that the "errors" in the errata will be > fixed for the production devices for the V4LX25 ? > > rudi Rudi, I have no association with Xilinx, so I suggest you develop a contact with Xilinx to get a real answer. Getting the inside "what and when" story on fixes is unlikely to be revealed in this forum, due to what should be obvious competitive reasons. In all fairness, Engineering Samples are early version product that many manufacturers ship to get something in the hands of their customers so that they can hopefully get a major portion of a design debugged before the final product is available. I've been glad to get ES parts, given the alternative of waiting. Typically the errata is corrected in the final product, but there is no guarantee. My experience with ES parts has been that the issues can be worked around or put off, so that I can complete >90% of my design with the ES parts. However, if one of the errata issues is critical to your application, you are screwed. Maybe I've been lucky. YMMV, buyer beware, do your home work. The errata datasheet seems to suggest a higher initialization current draw with this ES part, though I may be jumping to conclusions, since I've _not_ even looked at this part's full datasheet. (I've personally seen higher current draw for ES parts during init with a competing FPGA manufacturer who's name begins with "A," so it is my knee jerk reaction.) It is certainly an easy check for you to confirm that you are not experiencing some sort of power supply glitch during init. Instability would not be unheard of if LDO regulators are being used, for example. Good Luck, SteveArticle: 78212
Does anyone have any gigabit ethernet (copper or fiber) personality module designs for the ML310? Thanks. -- Nicholas C. Weaver. to reply email to "nweaver" at the domain icsi.berkeley.eduArticle: 78213
Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote: > The 4VLX25 has an issue with the timing of the last bit shifted out on > TDO in that TDO tristates too early. This results in the final bit > being misread, typically as a 1. Sadly, the last bit in the device > status register is the CRC bit and this results in the the warning > message you see. This issue is detailed in the device errata > > http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?BV_SessionID=@@@@1670514069.1106675756@@@@&BV_EngineID=cccfadddjhehjdfcflgcefldfhndfmo.0&category=-1210882&ipoid=24318118&iLanguageID=1 Neil, I would like to develop a real solution for the above problem. I am stuck with 3 Memec-Insight boards, which Memec refuses to replace for boards with Production Parts. Right now those boards are pretty much useless (no programming, no chipscope), as they provide directly a connector to a parallel cable 4. I need to build a gizmo, that will allow me to fix/work around this problem. There is also a (xilinx) CPLD that can be included in to the scan chain, but by default it would be before the FPGA. Now, If I can mode the CPLD after the FPGA in the chain, and add a delay to CPLDs TCLK input, would that solve the problem ? How big of a delay would I have to add ? Can you, or some other Xilinx soul give us a bit more technical data about the late TDO, so we can engineer a reliable solution ? Or any other practical solutions would be highly appreciated. Thank you ! Kind Regards, rudi ============================================================= Rudolf Usselmann, ASICS World Services, http://www.asics.ws Your Partner for IP Cores, Design, Verification and SynthesisArticle: 78214
glen herrmannsfeldt wrote: > nathan_wilson@hotmail.com wrote: > > I've been trying to divide a 60Hz signal down to 1Hz and slower using > > an XC9572 (5V). I connect a 60Hz signal to the gck input, count to 60, > > and output a 4 bit count of 1Hz. I've put an RF choke on the 60Hz input > > which seemed to remove some problems. It still has random delays in the > > output. Is 60Hz too slow for this device? > > An RF choke sounds good, but you should have more than that. > > A Schmidt trigger so it doesn't count noise that still comes > through. Otherwise 60Hz counting isn't too slow, but the > edge must be faster than that. If you put it through a few > inverters (and make sure they don't get optimized away) that > would speed up the transition. > > -- glen The 60Hz is a square wave output from an opto-isolator. It rises from 0.6V to 4.7V in 110 microseconds. Is that fast enought?Article: 78215
Rudi, I know we have a simple workaround that we use in the fpga lab. But, I am not in San Jose right now, so let me look into when I return on Friday. Austin Rudolf Usselmann wrote: > Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote: > > >>The 4VLX25 has an issue with the timing of the last bit shifted out on >>TDO in that TDO tristates too early. This results in the final bit >>being misread, typically as a 1. Sadly, the last bit in the device >>status register is the CRC bit and this results in the the warning >>message you see. This issue is detailed in the device errata >> >> > > http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?BV_SessionID=@@@@1670514069.1106675756@@@@&BV_EngineID=cccfadddjhehjdfcflgcefldfhndfmo.0&category=-1210882&ipoid=24318118&iLanguageID=1 > > Neil, > > I would like to develop a real solution for the above problem. > I am stuck with 3 Memec-Insight boards, which Memec refuses to > replace for boards with Production Parts. Right now those boards > are pretty much useless (no programming, no chipscope), as they > provide directly a connector to a parallel cable 4. I need to > build a gizmo, that will allow me to fix/work around this problem. > > There is also a (xilinx) CPLD that can be included in to the scan > chain, but by default it would be before the FPGA. > > Now, If I can mode the CPLD after the FPGA in the chain, and add a > delay to CPLDs TCLK input, would that solve the problem ? > > How big of a delay would I have to add ? Can you, or some other > Xilinx soul give us a bit more technical data about the late TDO, > so we can engineer a reliable solution ? > > Or any other practical solutions would be highly appreciated. > > Thank you ! > > Kind Regards, > rudi > ============================================================= > Rudolf Usselmann, ASICS World Services, http://www.asics.ws > Your Partner for IP Cores, Design, Verification and Synthesis > >Article: 78216
All, Yes, these ES errata issues have been addressed on the LX25. There is a 'zeroization' current (~400mA) on Vccaux as the part cleans out the config memory that just sticks, and doesn't go away on the very first LX25's, until they are configured. All other parts have fixes for this, so the LX25 will get its fixes, too. In a fixed part, there is still a 1-4 ms period of increased Iccaux, but I would hardly call it a surge, as it is on the order of a few hundred milliamperes, which the part will need anyway if DCM's are used (as well as the other circuits that use Vccaux). If the minimum Iccaux (per the data sheet) is provided, everything works just fine. The TDO issue is also fixed. For more details, you mail email me or Peter directly. I am presently not in San Jose until Friday. Austin Steve wrote: > Rudolf Usselmann wrote: > > >>Steve wrote: >> >> >>>Rudolf Usselmann wrote: >>> >>> >>>>I've got several boards from Memec-Insight with the Virtex 4 LX-25. >>>>Unfortunately they are marked "Engineering Samples", which worries >>>>me. >>>> > > <SNIP> > >>This datasheet describes some JTAG specific issues that may be the root >>cause of your other post. More power requirements during init -- check >>your power supplies! >> > > <SNIP> > >>What is the likelihood that the "errors" in the errata will be >>fixed for the production devices for the V4LX25 ? >> >>rudi > > > Rudi, > I have no association with Xilinx, so I suggest you > develop a contact with Xilinx to get a real answer. Getting the > inside "what and when" story on fixes is unlikely to be revealed > in this forum, due to what should be obvious competitive reasons. > > In all fairness, Engineering Samples are early version > product that many manufacturers ship to get something in the hands > of their customers so that they can hopefully get a major portion of > a design debugged before the final product is available. I've been glad > to get ES parts, given the alternative of waiting. Typically the errata > is corrected in the final product, but there is no guarantee. My > experience with ES parts has been that the issues can be worked around > or put off, so that I can complete >90% of my design with the ES parts. > However, if one of the errata issues is critical to your application, > you are screwed. Maybe I've been lucky. YMMV, buyer beware, do your > home work. > > The errata datasheet seems to suggest a higher initialization > current draw with this ES part, though I may be jumping to conclusions, > since I've _not_ even looked at this part's full datasheet. (I've personally > seen higher current draw for ES parts during init with a competing FPGA > manufacturer who's name begins with "A," so it is my knee jerk reaction.) > It is certainly an easy check for you to confirm that you are not > experiencing some sort of power supply glitch during init. Instability > would not be unheard of if LDO regulators are being used, for example. > > Good Luck, Steve > > >Article: 78217
Falk Brunner wrote: > "Kevin Neilson" <kevin_neilson@removethiscomcast.net> schrieb im Newsbeitrag > news:ct66gl$bgl1@xco-news.xilinx.com... > > >>>The Freq of the Altera is 20Mhz >>>The max freq of the encoder is 25Khz >>>The max Freq of output is 30Khz >>> >>>Please Help. >>> >>>Pliers >>> >> >>With such a massive ratio between system freq and encoder freq there is >>no need for a PLL. Just sample the encoder input using the system clock >>and add in pulses as desired. > > > ;-)) > then it would be still a ADPLL. But the goal ist to have the pulses spaced > as equal as possible. This reqires a ADPLL. > But after all, even a ADPLL is "just" a clever FSM. > > Regards > Falk > You're right. For some reason I was thinking he wanted to use a PLL or DLL, but he does clearly say he wants an ADPLL. So the correct answer is: no, I don't have any code for that, but if the input pulse edges are clean, making an ADPLL should be very straightforward: just make an NCO and then add a value to the NCO's phase increment that is proportional to the phase difference between the NCO and the input clock.Article: 78218
Thomas Reinemann wrote: > Neiko wrote: > > >>This seems to have solved my install problem, and I got both CDs >>installed, but when I try to run ise, it seem EXTREMEMLY SLOW, in fact I >>gave up waiting for UI to finish drawing itself...i did get some warnings: > > My box runs usually Seti on a nice level of 19. But Xilinx' GUI tools are > affected by this. That means ISE, Floorplanner and FPGAEditor are very slow > if Seti runs, look for tasks consuming performance. > Ayup ;) Same here. When I am going to run the tools, I first execute an alias which does environment confuration: alias xi 'seti stop;source /opt/Xilinx/settings.csh;source /opt/EDK/setup.csh;source /opt/eldk/v2p_bsp_envs.csh' -- My real email is akamail.com@dclark (or something like that).Article: 78219
The mismatches during readback are under investigation and appear to be
related to an issue in bitgen. A patch is currently under development
and should be available shortly
Rudolf Usselmann wrote:
> Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote:
>
>
>>The 4VLX25 has an issue with the timing of the last bit shifted out on
>>TDO in that TDO tristates too early. This results in the final bit
>>being misread, typically as a 1. Sadly, the last bit in the device
>>status register is the CRC bit and this results in the the warning
>>message you see. This issue is detailed in the device errata
>>
>>
>
> http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?BV_SessionID=@@@@1670514069.1106675756@@@@&BV_EngineID=cccfadddjhehjdfcflgcefldfhndfmo.0&category=-1210882&ipoid=24318118&iLanguageID=1
>
>>along with some possible work-arounds
>
>
>
> Thanks Niel, got the doc.
>
> Does this explain the 52 mismatches I get during compare as well ?
>
> Thanks,
> rudi
> =============================================================
> Rudolf Usselmann, ASICS World Services, http://www.asics.ws
> Your Partner for IP Cores, Design, Verification and Synthesis
--
*CAUTION:* Shameless self-promotion follows...
Article: 78220Moti wrote: > Hi all, > > I need to find the xilinx EDK reference design named opb_core_ssp0_ref > > the "user core templates reference guides" document is refering to it > but I can't find it in my EDK root or anywhere else. > If someone can help me here I will be glad.. It should be in EDK/hw/XilinxReferenceDesigns/pcores -- My real email is akamail.com@dclark (or something like that).Article: 78221
Rudolph,
Making the CPLD the last device in the chain should make the issue go
away since the CPLD seems to be able to sample the TDO before is tristates.
It is also known that the new Platform Cable USB makes this problem go
away because it samples the TDO earlier.
I believe that Autin indicated that they have another solution that they
have hadd success with in the lab. I think this involved judicious
capacitor selection. He indicated he would supply the details
Rudolf Usselmann wrote:
> Neil Glenn Jacobson <n.e.i.l.j.a.c.o.b.s.o.n.a.t.x.i.l.i.n.x.c.o.m.> wrote:
>
>
>>The 4VLX25 has an issue with the timing of the last bit shifted out on
>>TDO in that TDO tristates too early. This results in the final bit
>>being misread, typically as a 1. Sadly, the last bit in the device
>>status register is the CRC bit and this results in the the warning
>>message you see. This issue is detailed in the device errata
>>
>>
>
> http://www.xilinx.com/xlnx/xweb/xil_publications_file.jsp?BV_SessionID=@@@@1670514069.1106675756@@@@&BV_EngineID=cccfadddjhehjdfcflgcefldfhndfmo.0&category=-1210882&ipoid=24318118&iLanguageID=1
>
> Neil,
>
> I would like to develop a real solution for the above problem.
> I am stuck with 3 Memec-Insight boards, which Memec refuses to
> replace for boards with Production Parts. Right now those boards
> are pretty much useless (no programming, no chipscope), as they
> provide directly a connector to a parallel cable 4. I need to
> build a gizmo, that will allow me to fix/work around this problem.
>
> There is also a (xilinx) CPLD that can be included in to the scan
> chain, but by default it would be before the FPGA.
>
> Now, If I can mode the CPLD after the FPGA in the chain, and add a
> delay to CPLDs TCLK input, would that solve the problem ?
>
> How big of a delay would I have to add ? Can you, or some other
> Xilinx soul give us a bit more technical data about the late TDO,
> so we can engineer a reliable solution ?
>
> Or any other practical solutions would be highly appreciated.
>
> Thank you !
>
> Kind Regards,
> rudi
> =============================================================
> Rudolf Usselmann, ASICS World Services, http://www.asics.ws
> Your Partner for IP Cores, Design, Verification and Synthesis
>
>
--
*CAUTION:* Shameless self-promotion follows...
Article: 78222I know it should be there, the problem is that it is not there (even after installing the service pack) ... I will appreciate it if you will be able to send me the package or at least the pdf document contained there by email. To - moti@terasync.net I tried to get it via my Xilinx FAE and he also does not have it. Thanks in advance, Moti.Article: 78223
Hi, can someone tell me how to tell the fitter in ispLEVER 4.2 to place registers in the IOs as input registers ? Thank you for your help. Rgds AndréArticle: 78224
John David Birch wrote: > Is there any software I can download for use in MATLAB/Simulink that I can > download for free for testing / simulating FPGA from Xilinx ? > > I am doing my masters degreee thesis. > Have you looked at Simulink's "Link for ModelSim"? I am not sure about cost (they may have educational versions). -Lance
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