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Hi all, I use a small memory block in my design. It's a hand-coded (VHDL) dual-port ram, that's recognized by Quartus as memory. However, when synthesizing, Quartus rightfully complains that no initialization was set to the memory. I looked in the help, but found no way to initialize MY memory with a .mif file - only a Quartus generated mega-function memory, which I don't want to use. I have a strong feeling that it's just a simple attribute in the code, but I just can't find it anywhere in Quartus' docs. Any ideas ? TIA EliArticle: 75026
"Antti Lukats" <antti@case2000.com> wrote in message news:clb407$fuf$02$1@news.t-online.com... > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message > news:fX5ed.30157$z77.27796@news.chello.at... > > <is about Anttis NIOS clone> > > >> So, either it's available, or it's not. What's it to be? > > >> > > >> John > > > http://ipcores.openchip.org > > > > > > > Hi Antti, > > > > isn't 'Please ask for pricing' on a website with 'openchip' in the domain > name a little bit > > controversial ;-) > > I know, providing the source code of a processor for free download to be > 'open-source' > > AND trying to sell the design is an unusual and problematic (or better no) > business model. > > > > Martin > > Hi Martin, > > "open" doesnt have to mean that everything is free. "Open" doesn't mean it has to be zero cost. However, "open source" generally means "free as in speech" (I know there are differences between "open source software" and "free software"). That means you can happily charge me for the core - but I can then modifiy it if I want, and pass it on to others at whatever cost (if any) I want. If you have trademarked the name, you can stop me using that name - I'd have to find a new one for "my" version. "Open" designs are ones where all information is freely available, and anyone is free to implement them. The Sparc architecture is open - anyone can make a new Sparc core (with a different name, of course), while particular implementations are closed. The x86 architecture is propritery, or "closed" - you need a license to be able to make an implementation. > > For all designs and ip cores copyrighted to openchip - the sources are > available, but not necessarily for free. That's fair enough, and a perfectly valid arrangement, and may well be the best for both you and your customers. But it's not "open". > > Also in my opinion several "open source licenses" are in many ways more > restrictive then commercial licenses. > That's certainly true - the GPL has very specific restrictions. That's why people often use BSD-style licenses or modified GPL for such things as FPGA cores or embedded software components. > So as example if I would make NIOX GPL it would prevent you using it in > commercial products without re-releasing the modified source and possible > your own ip as well. If you OTOH "buy" NIOX source code you are not bound to > such restrictions and can make profit anyway you like. > > One of most problem with www.opencores.com is that the regulations there > make it real hard for the developers to benefit. > That's why many of the cores have BSD-style licenses. It is also quite possible to contact the authors and arrange another license if you want. In fact, the GPL can give you the best of both worlds here - people can download your core and use it, but are mostly restricted to non-commercial work (i.e., their own work must also be GPL'ed). Great for hobby use, accademica, and prototyping and experimenting. Companies looking to use it commercially can try it out, then buy a licence before shipping. And you get to call it "open" without people complaining. > So openchip licensing is more flexible - make money and what more important > allow others to make money too. So the others will have more time to play > with their children (or have fun the way the like it). > > Yes I have put "ask for pricing" - but did you ask? Maybe the price is $1 > for you? Notice I might sell it for $1 to Martin - but under specially > taylored license. All you have to do is ask :) > > Buying (if that option is available) is in many cases better and cheaper > than "getting for free". If you pay for something you are entitled to some > supprot (or money back) - getting for free means usually no support (and > nobody pays for your time you wasted because of lack of support). > That is, of course, incorrect as a generalisation - as anyone who has tried to get support for commercial products will realise. The quality of the product, the quality of support, and the price you paid are seldom related. I've had lots of experiance of getting good, fast and helpful feedback from open source developers who have received nothing from me (except perhaps some praise, or helpful feedback), and I've contacted commercial support lines to find I know more about their products than they do. Of course, the opposite occurs too - there is no rule. Selling on the basis of "support" relies on reputation, not the price you charge. Many people charge seperately for support and the product itself - perhaps even giving the product away as fully open source (such as many linux distributers). Whatever model works for you is fine - but it is unreasonable to claim that since you charge money your support will automatically be better. > Also selling something "enforce" more feedback then giving away for free. > And without feedback its really hard to find bugs and improve a product. As > example my MicroBlaze/uCLinux free version has been available for downloads > for several weeks, and there is ZERO feedback yet. Nothing. Perhaps everyone thinks it works so well there is no need :-) ? For something like that, however, there will not be many people trying it (do many people know about it?), and people are likely to blame themselves for problems rather than passing information back to you. Getting an active community around a product can be difficult - I know how frustrating it can be to release something as open source and get no reaction. I wish you luck with your processor. As I said, I don't think anyone has problems with your choice of licensing and pricing (although I suspect a GPL version, perhaps less powerful or less optomised, and a commercial version would help you get customers and feedback faster). It's just that "open" means far more than "you get the source with the product" (even the Windows source is available). David > > Antti > >Article: 75027
Hello, I am developing a FPGAs (BGA case) board. Is it possible to check the connections between two pins on two different FPGAs with the Boundary scan? If so, exists there a tool that is able to make this kind of test using the board schematic? Thank you in advance. smuArticle: 75028
Have a look at the new Spartan-3 variant when fuller details are released. News item here http://www.xilinx.com/prs_rls/silicon_spart/0478s3lp.htm . Depending on usage and the final figures for current consumption this may do what you want. It you can squeeze you requirements into a Coolrunner2 then it probably remains a better choice. John Adair Enterpoint Ltd. - Home of Broaddown2. The Ultimate Spartan3 Development Board. http://www.enterpoint.co.uk "John" <localhost@localhost.com.com> wrote in message news:YO1fd.27349$Kl3.14348@twister.socal.rr.com... > I am working on an instrument that currently uses a 300 MHz TI dual- > issue DSP + A/Ds + a micro. Under "normal" use, I can get a week out of > the D-cell batteries the device uses. > > At the moment, I am considering replacing the DSP and other glue with an > FPGA, but I don't see many low-power options. > > Any suggestions? Any low-power FPGA experiences to share? > > I asked an Altera FAE and he very rudely answered "Low-power Altera > FPGAs aren't on the road map"...yeah and I bet low-power CPLDs (ala > MaxII) weren't on the road map until CoolRunner started hurting sales... > > I'd like to stick with brand A or X since they offer soft core > processors. > > John.Article: 75029
FPGA's by their very nature are low power.. provided you don't clock them fast. The idea would be to build something like Intel's Speed step into it.. so it slows down or even freezes when not needed. you will want a DPLL version that can have the clock multiplied by more than 2 for this. The DPLL can't be changed without stoppage.. but there are clock muxes too .. so you can clean switch while you change a DPLL. Ray or Austin might know better about doing this.. I've never tried it. Maybe even look at a device that uses quadrant clocks instead of global clocks.. but that would limit area to 1/4 of the device per clock. but a fast clock isn't spread over the entire device then (am not sure how much affect this would have on power). Maybe look at a small coolrunner to handle clock management / power control. Then start using slow clocks where you don't need speed.. and only fast where critical. You should find the power reduction impressive compared to a DSP. But as with anything.. the higher the clock... the higher the power.. so that's your biggest enemy. If you can't reduce the clock.. then IMO low power will never exist with current silicon. Next pick you interfaces wisely. Don't use high power interfaces unless absolutely nessassary. And even then revaluate first. Then pick you IO / CORE / AUX voltages If they are low then you can reduce power... I'm not sure if you can get them to all run of a single battery's voltage.. not using a regulator will save you big time on a power conscious design. failing that... use an ultra high efficient PSU to get your supply voltages from the battery. It will probably be one of the biggest looses power wise. The last thing is don't choose a device bigger than you need. Silicon area is equates to power. There is an entire science devoted to low power. And I'm sure I don't know much about it too :-) Simon "John" <localhost@localhost.com.com> wrote in message news:YO1fd.27349$Kl3.14348@twister.socal.rr.com... > I am working on an instrument that currently uses a 300 MHz TI dual- > issue DSP + A/Ds + a micro. Under "normal" use, I can get a week out of > the D-cell batteries the device uses. > > At the moment, I am considering replacing the DSP and other glue with an > FPGA, but I don't see many low-power options. > > Any suggestions? Any low-power FPGA experiences to share? > > I asked an Altera FAE and he very rudely answered "Low-power Altera > FPGAs aren't on the road map"...yeah and I bet low-power CPLDs (ala > MaxII) weren't on the road map until CoolRunner started hurting sales... > > I'd like to stick with brand A or X since they offer soft core > processors. > > John.Article: 75030
Thomas Rudloff <thomasREMOVE_rudloffREMOVE@gmx.net> wrote in message news:<417BA070.3030805@gmx.net>... > Moti Cohen wrote: > > >>> > >>> > >>> > >>> > >>Do not know if this was addressed before. Do you use a four layer PCB > >>carefully decoupled with capacitors? > >>Is your ground bounce ok? Do you have contentions on your board? Did you > >>try to put the outputs into slow > >>smooth switching mode? > >> > >> > > > > > >- I'm using a 10 layers PCB and I believe that I decoupled the voltage > >supply inputs as needed ( three levels of capcitors values). > > > >- I dont have any contentions on the board (I tested it on several > >boards) - and the current consumption is o.k. + the chip does not warm > >up + the same pin assignment file is used in cases when the chip does > >works. > > > >- I guess that by "smooth switching mode" you mean "Slow slew rate" so > >at the begining I did tried to set the outputs to slow slew rate but > >without any success. > > > >I didnt checked for ground bounces - but my design does not contains > >many outputs that change on the same time and along with using slow > >slew rate outputs I hope that I should not worry about ground/VCC > >bouncing problems. > > > > > > > > > Looks like a very proper design. Another idea: Do you have floating inputs? > > >>It looks to me like you switch off a bank by switching and the result > >>depends on what is fitted into this bank. > >> > >> > > > >I'm not sure what you meant by "switching off a bank" I will be glad > >if you explain it.. > > > > > > > Chips have multiple VCC/GND inputs to parts of the chip. If you overload > a section it is likely > that because of the supply break down caused by this in the section flip > flops might flip. > Texas Instruments has a very good app note: scba004c.pdf > > Another thing is tiying the design. I am not familia with the latest > software and just figuring > out some things either. But on Foundation there was a tie option to tie > unused inputs to > defined logic levels. I know from the past that you can test designs > without tie to save time > but they were not that reliable like tied design. in the Xilinx's spartan IIE its possible to associate an internal pull-up/pull-down resistor to each of the logic inputs, hence tying them to either vcc or gnd in case that they are floating. But still I would like to thank you for the reference to the TI article, I downloaded it and I attend to read it soon. Thanks again.. Ragards, Moti.Article: 75031
Hi everyone, I had a question in regards to the Xilinx ISE. I have a design in which i use synopsys for synthesis. Then, I import the edif file into XILINX ISE. Next, I go to "Create Timing Constraints." What i find here is a list of values that the Xilinx ISE assumes to be clocks. The problem is, these values do not contain some of the clock signals. Why is this? Is there a way i can force it to put some of my signals in this clock constraint section? It has a lot of signals in this section that aren't even clock signals, is there a way to define this section better? Thanks, XavierArticle: 75032
Can a Cyclone PLL accept a clipped sine wave with an amplitude of 0.8V - i.e. what is the maximum rise time on the edge of the PLL clock input?Article: 75033
Hi Eliben, The current version of Quartus 4.1 requires the use of a mega-function generated memory for RAM initialization. We are working on the ability to initialize a memory from within the HDL in one of our 2005 releases. - Subroto <eliben@gmail.com> wrote in message news:1098690343.844854.109020@f14g2000cwb.googlegroups.com... > Hi all, > > I use a small memory block in my design. It's a hand-coded (VHDL) > dual-port ram, that's recognized by Quartus as memory. > However, when synthesizing, Quartus rightfully complains that > no initialization was set to the memory. I looked in the help, > but found no way to initialize MY memory with a .mif file - only > a Quartus generated mega-function memory, which I don't want > to use. > > I have a strong feeling that it's just a simple attribute in the > code, but I just can't find it anywhere in Quartus' docs. > Any ideas ? > > TIA > Eli >Article: 75034
Anyone knows of a programmable I/O card for a PC ? I am lookinf for something that can be plugged into PCI slot and software programmed to generate arbitrary digital outputs such as Square-Wave clock or any Serial bit pattern. thnxArticle: 75035
John, There are two issues here: while operating, what is the allowed power budget, and while idling what is the allowed power budget? Some devices just sit there more that 90% of the time doing nothing (like a software defined handheld radio). Other designs are running 100% of the time. FPGAs have more leakage current (static current) than a ASSP (like a DSP uC), and thus are not optimal for designs where you want long battery life. FPGAs are very efficient for doing the work (dynamic power), but high clock speeds means lots of power. Better to make the algorithm highly parallel, and lower the clock rate as much as possible. Typical ratios for DSP vs FPGA are 80:1 speed up possible if you use a FPGA instead of a DSP. You can use this in reverse, in other words, slow down the 300 MHz DSP clock by a factor of 80 when you implement the algorithm in a FPGA (3.75 MHz for the same 'work'). The LX25 Virtex 4 is ~ 40 mA static leakage at room temp at 1.2 volts. The DSP48 blocks (one 18X18 multiply-accumulate) are 3 to 9 mW/MHz (depending on how much interconnect you use to make your filters). Reconfiguration can be used to reprogram the device to do different jobs at different times, so a smaller part can do the job of a larger part, saving static power. Austin John wrote: > I am working on an instrument that currently uses a 300 MHz TI dual- > issue DSP + A/Ds + a micro. Under "normal" use, I can get a week out of > the D-cell batteries the device uses. > > At the moment, I am considering replacing the DSP and other glue with an > FPGA, but I don't see many low-power options. > > Any suggestions? Any low-power FPGA experiences to share? > > I asked an Altera FAE and he very rudely answered "Low-power Altera > FPGAs aren't on the road map"...yeah and I bet low-power CPLDs (ala > MaxII) weren't on the road map until CoolRunner started hurting sales... > > I'd like to stick with brand A or X since they offer soft core > processors. > > John.Article: 75036
"Yaseen Zaidi" <yaseenzaidi@NETZERO.com> wrote in message news:a31921fc.0410242057.2fbe3c42@posting.google.com... > Hello there, > > I've got a hard-wired asyncrhonous reset coming into GCK on a Spartan > XC2S200 device. The reset is used within three different processes in I you must instantiate a IBUFG on the reset signal in your hdl code in order to use GCK as non clock signal. Xilinx Spartan3 Starterkit (designed by Digilent) has this kind of problem that reset is connected to global clock. Instantiating IBUFG fixes the mapper problem for it. AnttiArticle: 75037
John Williams wrote: > Hi Mike, > > Mike Peattie wrote: > >> I have written an assembler for PicoBlaze (KCPSM3) in Perl. It's working > I could be interested in this - but mostly from the perspective of using > it as a base to port the assembler into C. I have a beginning here: <ftp://ftp.icarus.com/pub/eda/pbasm/> The assembler structure is there, it only needs some missing pseudo-ops implemented and a few missing instructions filled into a table. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 75038
>FPGAs are very efficient for doing the work (dynamic power), but high >clock speeds means lots of power. Better to make the algorithm highly >parallel, and lower the clock rate as much as possible. What's going on here? Classic reasoning says that 2 FFs at half speed will take the same power as 1 FF at full speed. (assuming same cap load...) Why not run faster so you can use a smaller part and get lower static power? -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 75039
Simon, I guess it's been a while since you checked out the quiescent supply currents for the latest parts? For example, worst case Iccintq for the smallest V2PRO (XC2VP2) is 300mA. That's about 20 hours on a NiMH D cell. Typical is 20mA, but no-one would design with typical figures, would they? BTW, anyone know why there's such a big difference from 'typical' to 'max' figures? Does it depend on the configuration used in the part? Cheers, Syms. "Simon Peacock" <nowhere@to.be.found> wrote in message news:417cd164@news.actrix.gen.nz... > FPGA's by their very nature are low power.. provided you don't clock them > fast. >Article: 75040
Hi Austin, Question. Why does a large slow machine use more power than a small fast one? Cheers, Syms. p.s. I think the algorithm uses more or less the same power whichever way you go, so I always go small and fast to use a smaller part. Product of size and speed and all. I guess that's not good for Xilinx's sales though? Just kidding! ;-) "Austin Lesea" <austin@xilinx.com> wrote in message news:clj446$qq3@cliff.xsj.xilinx.com... > FPGAs are very efficient for doing the work (dynamic power), but high > clock speeds means lots of power. Better to make the algorithm highly > parallel, and lower the clock rate as much as possible. >Article: 75041
Symon, The leakage current is not pattern dependent. Make sure you check the latest datasheet, as we used to state all leakages at 100C worst case (theoretical) silicon. We now state what we see from the process control sampling over all actual process corners. Austin Symon wrote: > Simon, > I guess it's been a while since you checked out the quiescent supply > currents for the latest parts? For example, worst case Iccintq for the > smallest V2PRO (XC2VP2) is 300mA. That's about 20 hours on a NiMH D cell. > Typical is 20mA, but no-one would design with typical figures, would they? > BTW, anyone know why there's such a big difference from 'typical' to 'max' > figures? Does it depend on the configuration used in the part? > Cheers, Syms. > > "Simon Peacock" <nowhere@to.be.found> wrote in message > news:417cd164@news.actrix.gen.nz... > >>FPGA's by their very nature are low power.. provided you don't clock them >>fast. >> > > > >Article: 75042
Hal, Let's see....P= CV^2F, and so for each node switching, the power scales with frequency. One node at F is equal to two nodes at 1/2F? Yes, it sure looks that way. I suppose the reason to run slower is to run cooler. But, you are right, run the smallest part as fast as needed to do the work. No reason to run it any faster than needed, however. One reason for the very low power for the DSP48 is that the capacitive loads are very small. Good catch. Thanks, Austin Hal Murray wrote: >>FPGAs are very efficient for doing the work (dynamic power), but high >>clock speeds means lots of power. Better to make the algorithm highly >>parallel, and lower the clock rate as much as possible. > > > What's going on here? Classic reasoning says that 2 FFs at half > speed will take the same power as 1 FF at full speed. (assuming > same cap load...) > > Why not run faster so you can use a smaller part and get lower > static power? >Article: 75043
Hi Austin, http://direct.xilinx.com/bvdocs/publications/ds083.pdf Page 73 of 425. I'm curious at the order of magnitude spread of values from Typical to Max., especially as it's not configuration dependent. Anyway, if you have some new leakage figures, could you let me know where to find them? Thanks, Symon. "Austin Lesea" <austin@xilinx.com> wrote in message news:cljagp$pkn1@cliff.xsj.xilinx.com... > Symon, > > The leakage current is not pattern dependent. > > Make sure you check the latest datasheet, as we used to state all > leakages at 100C worst case (theoretical) silicon. We now state what we > see from the process control sampling over all actual process corners. > > Austin >Article: 75044
Thomas Rudloff <thomasREMOVE_rudloffREMOVE@gmx.net> wrote in message news:<41796BF6.6040901@gmx.net>... > I am targetting an S3 and need a VCXO. This can be done by permanently > rotating the delay in the DLL. > Unfortunately the DLLs in S3 do not wrap (IIRC). > > Is there another option than interleaving two DLLs and spool the second > towards the oposite end and switch on the > overflow on the first. > > Example: > The first one goes towards the max delay end. The second one is spooled > to minimum. On overflow the clock > will be swittched to the second one. (uh, it's frighting me!). Hi Thomas, I dont know what is your application that reqiuers the vcxo so maybe my suggestion will be useless but here it is anyway.. to my knowledge, a vcxo is an oscillator that is being controlled by analog tuning voltage determining its output frequency (usually used in pll sync applications) - so I'm not sure how to implement it in a fpga . but if what you need is a module with a controlled output frequency to be used either inside the fpga or outside it I suggest you to use a NCO - Nomerically Controled Oscillator which is very easy to implement in a fpga (using just an rotating accumulator). I hope that its helpfull in some way.. Regards, Moti.Article: 75045
>I'm curious at the order of magnitude spread of values from Typical to Max., >especially as it's not configuration dependent. Temperature? Isn't leakage exponential with (absolute) temperature. For things like battery life, many times you have to consider real operating temperatures rather than worst case if you want sensible answers. More fun for the people making and reading data sheets. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 75046
Symon, That is the latest data. The reason for the leakage is source drain leakage across the smallest geometry transistors. Since we do have a lot of transistors, we have to be very careful to use the leakiest versions only where needed for speed, and use the higher Vt transistors for non-speed paths and circuits (like the memory cells). One can select for the lowest current devices (which will also be the slowest speed devices), but that is a bad business model, as getting slow parts regularly is not something you necessarily want! As geometries shrink, leakage increases (per sq-micron). As well, process variations also increase, so there may be a larger variation in the latest generations than in earlier generations for both typical and maximum numbers. So the typ of 20 mA for a 2VP2 at room temperature is just that, typical process. The max at 300 mA at 100C is the fastest corner part/process number at the hottest temperature. The current at 85C would be about 2.5X the current at 25C (both from simulations and data). So, the same part would be typically 20 mA at room, and 50 mA at 85C. There is a small variation with pattern. Not large enough to matter (when compared to process variations). V4 has a low static (leakage) current (much much lower than other 90nm ICs) because of the triple oxide process we used. So the memory cells are all 0.13 micron, and the same as the V2P generation (in terms of leakage). If you are interested in a specific part, I could go see where the process is currently running, and provide you with data. Austin Symon wrote: > Hi Austin, > http://direct.xilinx.com/bvdocs/publications/ds083.pdf > Page 73 of 425. > I'm curious at the order of magnitude spread of values from Typical to Max., > especially as it's not configuration dependent. > Anyway, if you have some new leakage figures, could you let me know where to > find them? > Thanks, Symon. > "Austin Lesea" <austin@xilinx.com> wrote in message > news:cljagp$pkn1@cliff.xsj.xilinx.com... > >>Symon, >> >>The leakage current is not pattern dependent. >> >>Make sure you check the latest datasheet, as we used to state all >>leakages at 100C worst case (theoretical) silicon. We now state what we >>see from the process control sampling over all actual process corners. >> >>Austin >> > > >Article: 75047
John Williams <jwilliams@itee.uq.edu.au> writes: > Hi Mike, > > Mike Peattie wrote: > > I have written an assembler for PicoBlaze (KCPSM3) in Perl. It's > > working > > [snip] > > > I'd like to make a call for test cases, or potential users. Please > > email me if you're at all interested. It's possible that this > > script may be included in future distributions of PicoBlaze. > > I could be interested in this - but mostly from the perspective of > using it as a base to port the assembler into C. Isn't there a GNU assembler for PicoBlaze? Petter -- A: Because it messes up the order in which people normally read text. Q: Why is top-posting such a bad thing? A: Top-posting. Q: What is the most annoying thing on usenet and in e-mail?Article: 75048
"smu" <pas@d.adresse> wrote in message news:clih72$b8f$1@s5.feed.news.oleane.net... > Hello, > > I am developing a FPGAs (BGA case) board. > > Is it possible to check the connections between two pins on two > different FPGAs with the Boundary scan? > > If so, exists there a tool that is able to make this kind of test using > the board schematic? > > Thank you in advance. > > smu yes, checking connections is defenetly possible. Also many other things, like programming non JTAG memories and other non JTAG devices if those are connected to FPGAs or devices with JTAG boundary scan. check out www.jtag,com I guess pretty much expensive tools. if you dont mind some programming yourself I have an windows application that uses 2 PLDs in JTAG chain to program an FPGA (not on boundary scan!) and then via that FPGA an parallel Flash memory. This application could be modified to test your custom board. The schematics extraction would be manual, or if you can import netlist from sch a netlist reader could be added to provide the link to your schematics. AnttiArticle: 75049
Austin, Thanks for that, it's much clearer now. Of course, as Hal also says, the temperature makes a big difference. I seem to recall you've posted along these lines before, sorry to make you repeat yourself. I'm looking forward to when the V4 datasheet gets filled in. Until then, I'll now use the leakiest parts I buy in either the fastest circuits I design or the ones used in fridges! ;-) Best, Syms. "Austin Lesea" <austin@xilinx.com> wrote in message news:cljf2b$52g1@cliff.xsj.xilinx.com... > Symon, > > That is the latest data. > > The reason for the leakage is source drain leakage across the smallest > geometry transistors. Since we do have a lot of transistors, we have to > be very careful to use the leakiest versions only where needed for > speed, and use the higher Vt transistors for non-speed paths and > circuits (like the memory cells). > > One can select for the lowest current devices (which will also be the > slowest speed devices), but that is a bad business model, as getting > slow parts regularly is not something you necessarily want! > > As geometries shrink, leakage increases (per sq-micron). As well, > process variations also increase, so there may be a larger variation in > the latest generations than in earlier generations for both typical and > maximum numbers. > > So the typ of 20 mA for a 2VP2 at room temperature is just that, typical > process. The max at 300 mA at 100C is the fastest corner part/process > number at the hottest temperature. > > The current at 85C would be about 2.5X the current at 25C (both from > simulations and data). So, the same part would be typically 20 mA at > room, and 50 mA at 85C. > > There is a small variation with pattern. Not large enough to matter > (when compared to process variations). > > V4 has a low static (leakage) current (much much lower than other 90nm > ICs) because of the triple oxide process we used. So the memory cells > are all 0.13 micron, and the same as the V2P generation (in terms of > leakage). > > If you are interested in a specific part, I could go see where the > process is currently running, and provide you with data. > > Austin
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