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See XAPP719 for one possible use of the STARTUP_VIRTEX4 primitive (in this case in combination with the USR_ACCESS_VIRTEX4 primitive). - Peter GaLaKtIkUs™ wrote: > Hi all! > Can some one be kind and explain me the startup cycle of an Virtex-4? > Is the logic activated AFTER the GSR is asserted of should I add some > logic to wai for the end of the startup? > For what is the SARTUP_VIRTEX4 primitive? > > Cheers > Mehdi >Article: 93301
Thanks for the help, Ray. I added the register after the block ram and that fixed that timing error. I was then having more timing errors in a CoreGen FFT core. The design was running significantly slower than the data sheet specified. After a lot of playing around with tool settings, I finally found the problem. CoreGen showed the correct device on the bottom of the main gui page, however the device setting in the options was set to spartan 3. I corrected the setting, and now my design is making timing with default settings for all implementation tools. I think there is probably room for improvement as well. Thanks again. ScottArticle: 93302
Hi John, Could you please let me know how many comparators you need to do one pixel for 1 clock design? In the second picture, there are 13 comparators. WengArticle: 93303
Hi John, I am confused if your are the real author of the paper in Xilinx website paper: JOHN L. SMITH. I am not familiar with American people's names. I thought your were Just John before. If you are, please accept my respect for you. That is a really excellent paper and design. WengArticle: 93304
Hi, I've just finished tweaking all the Verilog code for my Atari DVG reimplementation. Problem is, I've hit the macrocell limit for the XC95216 chip I was using, and I can't really justify using two 95216es when the second one is only going to have 50 used macrocells on it. I've got some 72MC chips, but they're XC9500XL series (i.e. XC9572XL-10 in PC44 package). Does anyone know if an XC9500XL at 3.3V and an XC9500 at 5V will happily communicate with each other without level converter ICs between them, or would I be better off just adding another 95216 and some extra logic to fill the chip up? Another question - does anyone know of a (preferably UK or European) components distributor that carries XC95288 or XC95288XL chips in small quantities? Any leaded package is fine - QFP, LQFP, PQFP, whatever, as long as it has metal leads along the edges (i.e. not CSP or BGA). I'm also looking for Coolrunner chips, same rules - leaded packages only, small (i.e. testing samples) quantities. I've found loads of companies that'll sell me 20 or 30 of the things, but I only want two or three. I could get them from Digikey, but then I get to deal with UPS's "Customs brokerage fees" and such... Thanks. -- Phil. | Acorn RiscPC600 SA220 64MB+6GB 100baseT philpem@philpem.me.uk | Athlon64 3200+ A8VDeluxe R2 512MB+100GB http://www.philpem.me.uk/ | Panasonic CF-25 Mk.2 Toughbook No software patents! <http://www.eff.org/> / <http://www.ffii.org/> ... Neither Borrower Or Lender Be; routinely ignored by Congress.Article: 93305
Weng writes: >I am confused if your are the real author of the paper in Xilinx >website paper: JOHN L. SMITH. >I am not familiar with American people's names. I thought your were >Just John before. Yes, I am the John L. Smith who wrote that paper. I use JustJohn here because there are many John Smiths, and there are several notable other Johns who regularly contribute to comp.arch.fpga, e.g. the estimable John_H(andwork), JJ (JohnJakson), John Larkin, and a host of others. I also use JustJohn to remind me to keep my ego in check. >That is a really excellent paper and design. Thank you again. Flattery will get you lots of places. It won't get your homework done, or a patentable circuit... You see Weng, I'm confused. The questions you ask demonstrate complete unfamiliarity with the field, indicating you are either a student just starting out, or perhaps dabbling in something new for fun. But past posts (I just checked) indicate you want to patent something. If that is the case, you will have to work to get some knowledge in the field you want the patent in. >In the second picture, there are 13 comparators. Yes, and I will be truly impressed if you have something better (or better than Khaled's circuit), and would love to see it. I don't know if it would be worth patenting though, probably more trouble than it's worth, and very difficult to enforce. Still, it amazes me what does get patented. Weng, you've been very polite throughout this interchange, and if English is not your first language, you write it very well. But your questions are too simple, and you need to start answering them (researching) for yourself. Regards, JohnArticle: 93306
> Does anyone know if an XC9500XL at 3.3V and an XC9500 at 5V will happily > communicate with each other without level converter ICs between them, or > would I be better off just adding another 95216 and some extra logic to fill > the chip up? Mixing up 95 and 95xl ? That should work fine, but you have to consider the following: - No interconnect level problems due to the 5V-tolerance of the 95xl. - However the xl outputs drive to 3,3V only, 5V can be obtained by pullups only if outputs are tristated. Ignore that for 95/95xl interconnections or if TTL or HCT logic is driven. - 95 CPLDs have higher I/O sink current at 5V I/O's (24mA), 95XL have 8mA only. Source current of 4mA is the same in both families (95 at 5V). - 95XL is faster and cheaper, but (same as 95) has no input registers, so you must live with high setup times tsu. Consider connecting two 95216-20 together, the maximum clock frequency of synchronious interconnections can be 50MHz only. (Tsu+Tco=10+10ns). A 95216-20 and a 9572xl-10 can work up to 60,6MHz (Tco+Tsu=10+6.5ns), a little bit faster. - Coolrunner and CoolRunner-II have input registers, but less logic ressources. - 95/95xl JTAG chain can be 3,3V or 5V, see Xilinx Answer record #7270 http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=7270 At the German distri www.schukat.com, 95288XL in TQ144 and PQ208 can be ordered in small quantities: http://www1.schukat.com/schukat/schukat_cms_de.nsf/index/CMSFFEDE67DB7032C11C1256DF1003EF651?OpenDocument&wg=B1820&refDoc=CMS0187E8048C5198A9C1256D730042864D&kb=XC95288XL10TQG14 MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho !Article: 93307
In message <40oovlF1bnhaaU1@individual.net>
"M.Randelzhofer" <techseller@gmx.de> wrote:
> Mixing up 95 and 95xl ?
> That should work fine, but you have to consider the following:
[snip]
> - Coolrunner and CoolRunner-II have input registers, but less logic
> ressources.
Hmm, I might try fitting the logic into a Coolrunner in a few minutes. I've
just eliminated three registers that should not have existed and got the
logic down to 218 macrocells. Only two more MCs to optimize out, then I can
(hopefully) get it to fit in a single XC95216. Failing that, I'll put the
state machine logic in the 216 and move the vector output circuitry into a
XC95144XL.
I just need to figure out if a 95*XL can communicate with 5V CMOS logic - I
need to add some more glue logic to interface the vector generator to the
system bus of a CMOS 6502 CPU. It seems bus buffers may be necessary..
thankfully the 6502 has a R/!W output, which makes buffering the data bus
nice and easy (only need a 244 bus transceiver).
I'm also toying with the idea of building a Gameboy-based DSO or logic
analyser - another device with a 5V CMOS CPU (a Z80 this time)...
> - 95/95xl JTAG chain can be 3,3V or 5V, see Xilinx Answer record #7270
> http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=7270
That's a point - I completely forgot about the JTAG chain. Thanks for the
link...
> At the German distri www.schukat.com, 95288XL in TQ144 and PQ208 can be
> ordered in small quantities:
> http://www1.schukat.com/schukat/schukat_cms_de.nsf/index/CMSFFEDE67DB7032C11C1256DF1003EF651?OpenDocument&wg=B1820&refDoc=CMS0187E8048C5198A9C1256D730042864D&kb=XC95288XL10TQG14
That would be great, were it not for this:
>> We do not deliver to private end-users
So the search resumes :(
Thanks.
--
Phil. | Acorn RiscPC600 SA220 64MB+6GB 100baseT
philpem@philpem.me.uk | Athlon64 3200+ A8VDeluxe R2 512MB+100GB
http://www.philpem.me.uk/ | Panasonic CF-25 Mk.2 Toughbook
No software patents! <http://www.eff.org/> / <http://www.ffii.org/>
... "Bother", said Pooh, as the vice squad took his GIFS
Article: 93308>I just need to figure out if a 95*XL can communicate with 5V CMOS logic - I Which 5V CMOS logic? If it is HCT then 3.3 volts from 95XL is a high level. >system bus of a CMOS 6502 CPU. It seems bus buffers may be necessary.. 65(S)C02 should work at TTL levels. Only the clock input "needs" voltage swing up to full 5 volts. This is also true for NMOS 6502.Article: 93309
> I just need to figure out if a 95*XL can communicate with 5V CMOS logic - I > need to add some more glue logic to interface the vector generator to the > system bus of a CMOS 6502 CPU. It seems bus buffers may be necessary.. > thankfully the 6502 has a R/!W output, which makes buffering the data bus > nice and easy (only need a 244 bus transceiver). > > I'm also toying with the idea of building a Gameboy-based DSO or logic > analyser - another device with a 5V CMOS CPU (a Z80 this time)... > The 95*/95*xl mixture makes especially sense where 95* communicates with 5V CMOS or sinks higher currents, and 95xl cares for logic density and speed at noticeable lower prices. Using 95*xl only with levelshifters for 5V CMOS and a 3,3V LDO is probably the cheapest solution. CoolRunner XPLA3 devices have the same limits in driving 5V CMOS as 95*xl. MIKE -- www.oho-elektronik.de OHO-Elektronik Michael Randelzhofer FPGA und CPLD Mini Module Klein aber oho !Article: 93310
After I found out that I couldn't syntesize a lot of the verilog code (
http://awlnk.com/?aRts ), I had to redesign how I was going to
implement this design. I'm going for something significantly easier,
though I'm breaking it up into more modular parts. I'm getting all
sorts of errors from all over the place (using both silos synthesizer
and the xilinx webpack). The code is very simple - I want to be able
to set one of 32 pins as high, low, or high impedence using a minimal
number of input pins. The design I came up with so far incorporates a
counter latch/demux. I'm not sure how to implement the highimpedence
functionalty of the output, so I've ignored it for now (though I would
love some input). Here's the code so far -- any help would be greatly
appreciated!! :
module counter32(in,reset,out);
input [0:0] in;
input reset;
output [4:0] out;
always @(posedge in) begin /* i've seen sample code include reset
here, dont know why though */
if (!reset)
out = out + 1;
end
always @(posedge reset)
out = 5'b00000;
endmodule
module latch32(in,out,enable,signal);
input [5:0] in;
output [31:0] out;
input enable;
input signal;
integer N;
always @(posedge enable)
out[in] = signal;
endmodule
module counterLatch32(in,reset,enable,signal,out);
input [0:0] in;
input [0:0] reset;
input [0:0] enable;
input [0:0] signal;
output [31:0] out;
wire [4:0] select;
reg [31:0] out;
module counter32(in, reset, select);
module latch32(select, out, enable, signal);
endmodule
Article: 93311
In message <do7hpq$1bud$1@news.cc.tut.fi>
"Mika Leinonen" <mika.leinonen@tut.fi> wrote:
> >I just need to figure out if a 95*XL can communicate with 5V CMOS logic - I
>
> Which 5V CMOS logic? If it is HCT then 3.3 volts from 95XL is a high level.
No idea at all - that's half the fun of designing hardware for a Gameboy, no
voltage specs on the CPU, just a rather vague "it's a CMOS Z80 clone with an
onboard LCD controller and a few instruction set tweaks"...
> >system bus of a CMOS 6502 CPU. It seems bus buffers may be necessary..
>
> 65(S)C02 should work at TTL levels. Only the clock input "needs"
> voltage swing up to full 5 volts. This is also true for NMOS 6502.
That's good to know.. I'll check the datasheet in a sec - the chip I'm using
is a WDC W65C02SP.
Later.
--
Phil. | Acorn RiscPC600 SA220 64MB+6GB 100baseT
philpem@philpem.me.uk | Athlon64 3200+ A8VDeluxe R2 512MB+100GB
http://www.philpem.me.uk/ | Panasonic CF-25 Mk.2 Toughbook
No software patents! <http://www.eff.org/> / <http://www.ffii.org/>
... BNFL : Buy No Fish Locally
Article: 93312
Hi Mehdi,
GSR will reset all of the internal flipflops to a known state
(usually 0 - unless otherwise specified by the bitstream). There are
however other chip events that happen after GSR.
The best marker for the end of the FPGA startup is the EOS signal which
is an output available from the STARTUP_VIRTEX4 primitive. EOS stands
for "end of startup".
- Vic
GaLaKtIkUs™ wrote:
> Hi all!
> Can some one be kind and explain me the startup cycle of an Virtex-4?
> Is the logic activated AFTER the GSR is asserted of should I add some
> logic to wai for the end of the startup?
> For what is the SARTUP_VIRTEX4 primitive?
>
> Cheers
> Mehdi
>
Article: 93313Ah, this is interesting. Weng and I have been having this extended chat on median filters (hope it did not bore anyone), and because it seems that Weng is looking to develop something patentable, I had a look-see over at USPTO. I find there is a recently (04, July) granted patent, US 6760737, which seems after wading through all the pat-speak gobbledy-gook (which is mostly in the order of a proof (that can be done a bit simpler)), to list my median circuit exactly. One paragraph (col 4, lines 47-50) even describes the pipelining, not verbatim from the XCell note, but close enough. So has anyone else here had this happen? What was your reaction? On the one hand, I'm pleased to see that I can generate patentable stuff (5 years earlier than filing date on this one), but on the other hand mildly annoyed to see someone else's name there, and wishing I'd made the filing myself. How would you react? I would think the patent is useless, because I'd already shown the method, but am wondering if the state of law is such that Lucent could come after me for using my own circuit. Corrolary question...Do most patents just make money for lawyers and add to the writer's resumes? Or do a majority have actual worth beyond that? Regards All, JohnArticle: 93314
Scott Bekker wrote: > Thanks for the help, Ray. I added the register after the block ram and > that fixed that timing error. I was then having more timing errors in > a CoreGen FFT core. The design was running significantly slower than > the data sheet specified. .... I think there is probably room for improvement as well. > > Thanks again. > > Scott > Glad to have been a help. As I indicated, with some diligence, you can get the slow speed grade V4SX (-10) to run at 400 MHz, which is the max clock rate of the BRAMs and DSP48's when fully pipelined. The fabric, with the exception of the carry chains, can run considerably faster. The carry chains are limited to about 10 bits at 400 Mhz, which is a shame.Article: 93315
I'd pick up any book on Verilog and read the first 2-3 chapters. This will solve a majority of your problems. You're making fundamental mistakes with the shown code. "Reza Naima" <google@reza.net> wrote in message news:1135039228.101043.151430@o13g2000cwo.googlegroups.com... > After I found out that I couldn't syntesize a lot of the verilog code ( > http://awlnk.com/?aRts ), I had to redesign how I was going to > implement this design. I'm going for something significantly easier, > though I'm breaking it up into more modular parts. I'm getting all > sorts of errors from all over the place (using both silos synthesizer > and the xilinx webpack). The code is very simple - I want to be able > to set one of 32 pins as high, low, or high impedence using a minimal > number of input pins. The design I came up with so far incorporates a > counter latch/demux. I'm not sure how to implement the highimpedence > functionalty of the output, so I've ignored it for now (though I would > love some input). Here's the code so far -- any help would be greatly > appreciated!! : > > module counter32(in,reset,out); > input [0:0] in; > input reset; > output [4:0] out; > > always @(posedge in) begin /* i've seen sample code include reset > here, dont know why though */ > if (!reset) > out = out + 1; > end > > always @(posedge reset) > out = 5'b00000; > > endmodule > > module latch32(in,out,enable,signal); > input [5:0] in; > output [31:0] out; > input enable; > input signal; > integer N; > > always @(posedge enable) > out[in] = signal; > > endmodule > > > module counterLatch32(in,reset,enable,signal,out); > input [0:0] in; > input [0:0] reset; > input [0:0] enable; > input [0:0] signal; > output [31:0] out; > > wire [4:0] select; > reg [31:0] out; > > module counter32(in, reset, select); > module latch32(select, out, enable, signal); > > endmodule >Article: 93316
Hello, What cable are you using for programming? If it is a cable IV, Is it powered (LED is green not yellow)? Is this the only device in the chain? The cable IV needs power on pin 2 of the cable to match the IO supply of the device to be programmed. Check your mode control bits. I have programmed the V2P40 using both JTAG and serial with the mode bits set for serial slave. I would try a larger resistor and see if your symptoms change. (The Virtex Pro spec states >200 ohms.) Try a 1K or 2K? I am not familiar with the CRO acronym. Did you look at the timing and levels with a scope? We had trouble with the TDO->TDI on one part in the chain and the signals were not passing at 5MHz. Dropping the cable speed helped but fixing the path (missing a pullup) got us running reliably. Regards, Bart On Mon, 19 Dec 2005 10:52:37 -0600, rmanand wrote: > > >Hi friends > >The Virtex II pro (XC2VP100) device is not Configuring through Impact7.1e > > >When i try to check with CRO what is happeing at the BOUNDARY SCAN SIGNALS >TDO ,TDI,TCK ,TMS > >I found TDI,TMS,TDI signals are okay .THE TDO is always stuck at >one(pulled up by 220 ohm resisitor preferred by xilinix). > >The prog Pin is pulled up to 3.3V through 4.7k.The Init pin is pulled up >to 3.3v through 4.7k.These all are xilinx reccomendation. > >I could not understand what will be reason for the TDO is always high at >one and how to solve the problem. > > >The impact is always throughing Impact -583 error. >Expeting your valuabe replies > >Thanks in advance > >Article: 93317
Hi All, I have Linux up running for PPC on the virtex-ii pro board (XUPV2P). I'm new to embedded system design. Anyhow, I'm hoping to run software applications on the board. I'm familiar with adding software to the standalone system using EDK. But with an OS on it, what modifications do I need to make before the executables (.elf) can be run? Is there any reference? Thanks plenty. -EricArticle: 93318
i want to get an demo design reference of ICAP. if anyone want to give me a hand, many thanks here. ^_^ my e-mail is lioupayphone@gmail.comArticle: 93319
I will agree with Rob, you need a book. Clearly this is a homework
problem . . but you did a good job to start. So here are some pointers
that should help.
Generally :
1. Name your ports and your I/O's, something that means something.
"in", "out", "signal" are not very helpful. All these devices should
have an input called "clk".
2. Whenever assigning a sequential element ( flop / latch ) using a
reg, use the '<=' non-blocking assignment operator in verilog. This
will save you many headaches in the future.
3. [0:0] is unecessary, as an unsized input, output, reg or wire is
always 1 bit or [0:0].
Specifically:
1. (counter32) Don't assign a value (out) from two different
always-blocks. This is a synchronous version of the same flop, with an
enable ( en ) , and a clear ( in place of reset ) .
always @(posedge clk)
if ( !clr)
out <= (en) ? out + 1 : out ;
else
out <= 'b0 ;
2. Latches are troublesome and usually not preferred in FPGA design, if
you can use a flop. But if ( god forbid ) you need one. Here is how to
code it :
always (clk or d)
if ( clk ) q <= d ;
This is a single bit flop. Who's value is set on the output whenever
any value changes and the clock is high ( the definition of a latch ) .
3. (counterLatch32) You are confusing module declaration with module
instantiation. A declaration using the word "module" followed by the
name of a module, followed by all the stuff in a module, followed by
the word "endmodule". What you need to do is make an instance of a
block so it might look like this :
counter32 count_a ( .clk(clk), .en(en), .reset(reset), .out(out) ) ;
This will instance a counter32 module and connect its inputs and
outputs to wires to wires of the same name in the parents module scope.
The instance name will be count_a.
I hope this all makes sense. I am sure you can find some good online
FAQ's about verilog. Please look up those for further info. Best way to
learn is by just copying someone else.
-Art
Article: 93320JustJohn wrote ... > I would think the patent is useless, because I'd already shown the > method, but am wondering if the state of law is such that Lucent could > come after me for using my own circuit. Could Lucent come after you for using your own circuit? Of course the answer is "yes." The more significant question is whether or not Lucent would have a significant chance of winning a patent infringement suit. If you can demonstrate that your circuit was published or sold more than 1 year before the priority date of Lucent's patent application, then it would be difficult for Lucent to prevail in court. > Corrolary question...Do most patents just make money for lawyers and > add to the writer's resumes? Or do a majority have actual worth beyond > that? Generally it is difficult to estimate the value of a patent. In some cases patent rights are sold, so for those patents there is an established value. In other situations an infringement case is won by the patent owner, or a settlement is agreed to; again some dollar value is determined. But in many situations a company has a portfolio of patents that keep competitors at bay. Consider the situation where your company develops and patents technology "A", and improvements A1, A2, etc. If these patent allow you to achieve a monopoly they can be quite valuable. But perhaps I am you competitor and to avoid your patents and to stay in the marketI develop and patent B, B1, B2, etc. Within a few years we are developing parallel, but distinct technologies. There may be some advantages to the A series, and there may be different advantages to the B series, but it is hard to put a dollar value on each of our technologies. Our patents are important to our businesses, the help us maintain a douopoly, and they may prevent the other party from implementing certain improvements. But how much are they worth? Richard TanzerArticle: 93321
Hi again! When instantiating the STARTUP_VIRTEX4 shoul I connect all the inputs? Is it possible to leave them all (inputs) unconnected? from where should the input GSR come from ? Thnaks a lot for interest and help MehdiArticle: 93322
Hi! If you recieve it follow it to me if you can and if the author of the reference agrees. MehdiArticle: 93323
I bought a book a book recommended by one of the application engineers at a reseller of Xilinx (Verilog HDL), and it described verilog very well. But it didn't distinguish between what was used for simulation and what is synthesizeable. So my first bit of code (if you look at the link) worked fine on the simulator, but it relied heavily on constructs that could not be synthesized. I then asked for recommendations on books, and was told that there were no good ones. Hence I'm hoping I can get some pointers to reference code, or some help debugging the code I wrote. Thnx, RezaArticle: 93324
You can try with universalscan software >"smu" <pas@d.adresse> wrote in message >news:clih72$b8f$1@s5.feed.news.oleane.net... >> Hello, >> >> I am developing a FPGAs (BGA case) board. >> >> Is it possible to check the connections between two pins on two >> different FPGAs with the Boundary scan? >> >> If so, exists there a tool that is able to make this kind of test using >> the board schematic? >> >> Thank you in advance. >> >> smu > >yes, checking connections is defenetly possible. Also many other things, >like programming non JTAG memories and other non JTAG devices if those are >connected to FPGAs or devices with JTAG boundary scan. > >check out >www.jtag,com > >I guess pretty much expensive tools. > >if you dont mind some programming yourself I have an windows application >that uses 2 PLDs in JTAG chain to program an FPGA (not on boundary scan!) >and then via that FPGA an parallel Flash memory. This application could be >modified to test your custom board. The schematics extraction would be >manual, or if you can import netlist from sch a netlist reader could be >added to provide the link to your schematics. > >Antti > > >
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