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Messages from 89050

Article: 89050
Subject: Re: Long Multiplication
From: "Gary Pace" <xxx@yyy.com>
Date: Sun, 04 Sep 2005 04:03:08 GMT
Links: << >>  << T >>  << A >>
Thanks.

"Symon" <symon_brewer@hotmail.com> wrote in message 
news:431a3a00$0$18645$14726298@news.sunsite.dk...
> Hi Gary,
> Google for "distributed arithmetic". I'm sure plenty of people are ready 
> and willing to sell you some VHDL!
> Cheers, Syms.
> 



Article: 89051
Subject: IC design contract
From: cell_rx@msn.com
Date: 3 Sep 2005 22:53:26 -0700
Links: << >>  << T >>  << A >>
if you or your friend have PCI-Express and 10G ethernet MAC design
experience successful,plz email me.


there is a PCI-Express and 10G ethernet MAC  interface design contract.


Article: 89052
Subject: Logic??
From: "Kumar" <kumarssss@gmail.com>
Date: 3 Sep 2005 23:00:45 -0700
Links: << >>  << T >>  << A >>
What logic is needed for the

4 bit add pipe

to write the VHDL program????


Article: 89053
Subject: Re: Modelling latches in Verilog
From: Philip Pemberton <philpem@despammed.com>
Date: Sun, 04 Sep 2005 09:39:13 +0100
Links: << >>  << T >>  << A >>
mk wrote:
> actually 574 is not a latch but a posedge DFF with tri-state outputs

Oh, so it is. The difference being that the latch's Qout follows Din while EN 
is high, and the flipflop only latches data in when EN performs a L/H transition.

The things you only notice when you read the truth tables. I'm working from 
the TI "Digital Logic Pocket Data Book" here :)

I've been trying to model the whole lot in one file - never thought of 
modelling the DFFs and buffers separately... I've added the t74574 model to my 
code library - thanks for that.

Thanks,
-- 
Phil.                                | Acorn RiscPC600 SA220 64MB+6GB 100baseT
philpem@despammed.com (valid address)| Athlon64 3200+ A8VDeluxe R2 512MB+100GB
http://www.philpem.me.uk/            | Panasonic CF-25 Mk.2 Toughbook
No software patents!          <http://www.eff.org/> /  <http://www.ffii.org/>

Article: 89054
Subject: Re: Logic??
From: vizziee@gmail.com
Date: 4 Sep 2005 01:40:57 -0700
Links: << >>  << T >>  << A >>
Can you please eleaborate what exactly are the specifications of your
problem.


Article: 89055
Subject: Partial Reconfiguration : New Forum
From: Michael <michael@genesis-os.com>
Date: Sun, 4 Sep 2005 01:50:22 -0700
Links: << >>  << T >>  << A >>
My name is Michael and I am entering this technique of partial re-configuration.

I am starting new Group of PR users. And you are most welcome to join it.

Group name: Partial_reconfiguration Group home page: <http://groups.google.com/group/Partial_reconfiguration> Group email address: Partial_reconfiguration@googlegroups.com

Regards,

Michael Zilbershlag - CEO Genesis-OS

Article: 89056
Subject: Re: The best way to sum 8 datas?
From: "Marco" <marcotoschi@nospam.it>
Date: Sun, 4 Sep 2005 16:25:55 +0200
Links: << >>  << T >>  << A >>
>
> Accumulator.  Adder with output register connected back to one adder 
> input, block RA< connected to other input.
>
> 1. Clear register
>
> 2. Step through block RAM addresses and clock accumulator register at end 
> of each address cycle.
>
> 3. After n cycles (8?) result is in output of accumulator.
>
> Slurp
>

Many Thanks
Marco 



Article: 89057
Subject: Re: Partial Reconfiguration : New Forum
From: Paul Hartke <phartke@Stanford.EDU>
Date: Sun, 04 Sep 2005 08:13:19 -0700
Links: << >>  << T >>  << A >>
Do you think another group is really required for this relatively small
community?

John Williams already has a good email list and archive at
http://www.itee.uq.edu.au/~listarch/partial-reconfig/ that has been
pretty active for almost two years now.  

Paul

Michael wrote:
> 
> My name is Michael and I am entering this technique of partial re-configuration.
> 
> I am starting new Group of PR users. And you are most welcome to join it.
> 
> Group name: Partial_reconfiguration Group home page: <http://groups.google.com/group/Partial_reconfiguration> Group email address: Partial_reconfiguration@googlegroups.com
> 
> Regards,
> 
> Michael Zilbershlag - CEO Genesis-OS

Article: 89058
Subject: Re: Logic??
From: "Kumar" <kumarssss@gmail.com>
Date: 4 Sep 2005 10:05:20 -0700
Links: << >>  << T >>  << A >>
Write a VHDL program

 4 bit add pipe
              (a) behavioural arch
              (b) structural arch
Can u tell?


Article: 89059
Subject: Re: Logic??
From: "Slurp" <slip@slop.slap>
Date: Sun, 4 Sep 2005 18:25:50 +0100
Links: << >>  << T >>  << A >>

"Kumar" <kumarssss@gmail.com> wrote in message 
news:1125853520.326154.279290@z14g2000cwz.googlegroups.com...
> Write a VHDL program
>
> 4 bit add pipe
>              (a) behavioural arch
>              (b) structural arch
> Can u tell?
>

Carry in?
Carry out?
How long is the pipe?
Input registers?
Output Registers?
Binary/Gray/signed/unsigned?
Homework/assignment?




Article: 89060
Subject: Re: Logic??
From: John_H <johnhandwork@mail.com>
Date: Sun, 04 Sep 2005 17:44:04 GMT
Links: << >>  << T >>  << A >>
If you could share with us the texts and other instructional materials 
from your class, perhaps THEN we could adequately do your homework for you.

As you gather the material to post on the newsgroup, perhaps you'll 
realize the information is already at your fingertips.


Kumar wrote:

> What logic is needed for the
> 
> 4 bit add pipe
> 
> to write the VHDL program????

Article: 89061
Subject: Re: Spartan 3 Ram Instantiation
From: amir.intisar@gmail.com
Date: 4 Sep 2005 14:05:36 -0700
Links: << >>  << T >>  << A >>
Hi John,
            basically, every 1ms (very slow) a 16 bit value is coming
in from an ADC. I need to take this value and put it in memory. The
Spartan 3 has 262,144(18 bit)  16 bit wide memory slots (two of). I
just want to insert the ADC data in memory location one, increment the
address, wait for the next ADC value and put it in memory address
two...so on. I have written code for this in verilog but i was looking
at maybe instantiating it using one of the xilinx templates, because my
code is messy. Is there any better strategy for what i am doing?.
....Thanks !!!!!!!!!


Article: 89062
Subject: Re: Spartan 3 Ram Instantiation
From: Philip Freidin <philip@fliptronics.com>
Date: Sun, 04 Sep 2005 21:43:55 GMT
Links: << >>  << T >>  << A >>
On 2 Sep 2005 13:35:51 -0700, amir.intisar@gmail.com wrote:
>           i have a question about the RAM instantiations for the
>Spartan 3(XC3S200) in the Xilinx verilog templates. You can instantiate
>different types of SRAM sizes and bit widths, like 16K x 1, 2K x 8,
>512K x 32, but what if a user wants use the SRAM in a 256K x 16 format,
>or something else not displayed in the templates?. Can this be done ??

The Xilinx XC3S200 FPGAs do not have that much memory on chip. The memory
is in blocks of 16K (or 18K with parity) bits. You can select different
configurations for each block, but the total size of each block is fixed
at 16K/18K bits. This is 2K bytes.

The XC3S200 has 12 blocks, for a total of 24K bytes. If you have data that
is 16 bit, then at most, you can store 12K values.

There is detailed comparison information on all Xilinx FPGAs at this URL:

   http://www.fpga-faq.org/compare/build_form.cgi

On 4 Sep 2005 14:05:36 -0700, amir.intisar@gmail.com wrote:
>Hi John,
>            basically, every 1ms (very slow) a 16 bit value is coming
>in from an ADC. I need to take this value and put it in memory. The
>Spartan 3 has 262,144(18 bit)  16 bit wide memory slots (two of).

No it doesn't. It has a total of 221184 bits.

>I just want to insert the ADC data in memory location one, increment the
>address, wait for the next ADC value and put it in memory address
>two...so on. I have written code for this in verilog but i was looking
>at maybe instantiating it using one of the xilinx templates, because my
>code is messy. Is there any better strategy for what i am doing?.
>....Thanks !!!!!!!!!

If you really need 256K x 16 storage, it will need more memory, off
chip. How this is implemented is up to you. The Xilinx templates only
cover what fits on chip.




===================
Philip Freidin
philip.freidin@fpga-faq.org
Host for WWW.FPGA-FAQ.ORG

Article: 89063
Subject: Re: High baud rate chips for RS232 protocol
From: langwadt@ieee.org
Date: 4 Sep 2005 15:15:00 -0700
Links: << >>  << T >>  << A >>

Jim Granville skrev:

> Mak wrote:
> > Hello all,
> >
> > I am interested in designing a custom board with serial interface and I
> > am searching for RS232 port driver ICs which can support baud rates
> > higher than 230kbps.
> >
> > There are many PCI or USB to serial interface options available which
> > support bauds of upto 920kbps. I have designed a UART interface in FPGA
> > but need higher baud rate driver ics to actaully get the performance I
> > require.
> >
> > Any recommendations?
>
> I think you are asking about the level translators ?
> You have tried the usual suspects at Maxim and Linear ?
> You might also want a 3.3V supply interface device.
>
> http://www.maxim-ic.com/Interface.cfm
> shows 150 devices under "RS-232 Line Driver/Receivers"
>
> -jg

If you follow the rs-232 spec you can't go above ~115.2Kbit, to go
above that you need a level translator that supports higher speeds,
usually 
with an extra pin that enables a higher slew rate    

-Lasse


Article: 89064
Subject: Re: Spartan 3 Ram Instantiation
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Sun, 4 Sep 2005 16:39:49 -0700
Links: << >>  << T >>  << A >>
Use a RAMB16_S18 .  Don't use the two extra parity bits.

You will get 1K of storage for each BRAM or 12K max, I think, for that chip 
there.

Why would you think you need to double the frequency?

Brad Smallridge
aivision.com


<amir.intisar@gmail.com> wrote in message 
news:1125693351.090847.157570@g14g2000cwa.googlegroups.com...
> Hey Folks,
>           i have a question about the RAM instantiations for the
> Spartan 3(XC3S200) in the Xilinx verilog templates. You can instantiate
> different types of SRAM sizes and bit widths, like 16K x 1, 2K x 8,
> 512K x 32, but what if a user wants use the SRAM in a 256K x 16 format,
> or something else not displayed in the templates?. Can this be done ??
>
> Also, the clock parameter (clk) in the instantiations, does this neeed
> to be 100 Mhz, same as the SRAM clock frequency?. Do i need to use the
> DCM to double the FPGA clock frequency?.
>
> Thanks !!!
> 



Article: 89065
Subject: Re: I2C "SCL" line problem
From: "Brad Smallridge" <bradsmallridge@dslextreme.com>
Date: Sun, 4 Sep 2005 16:52:00 -0700
Links: << >>  << T >>  << A >>
Well, the I2C interface has those funny START and STOP conditions
relating to data changing while on the clock is high state.  Are you
aware of that and could that influence your circuit?

Brad Smallridge
b r a d @ a i v i s i o n . c o m


<praveen.kantharajapura@gmail.com> wrote in message 
news:1125635260.092860.131020@f14g2000cwb.googlegroups.com...
> Hi all,
>
> I faced the following problem with my I2C slave code(VHDL).
>
> I was incrementing a counter on the negative edge of  SCL(this clock is
> coming from the processor's I2C port , 100 KHz frequency).
> But what i observed on the CRO was that my bit counter which was
> running on the "negative edge" of SCL , was incrementing on "positive
> edge" also and this was not happening always.
>
> The solution to this problem was i inverted the incomimg clock "SCL"
> and used the rising edge to increment my counter now it was fine.
>
> Can any I2C experts clarify what is the problem with working on
> "negative edge of "SCL" clock.
>
>
> Regards,
> Prav
> 



Article: 89066
Subject: Quartus web edition simulation with off-chip logic?
From: VAX9000@gmail.com
Date: 4 Sep 2005 20:03:36 -0700
Links: << >>  << T >>  << A >>
Hi, list,
  I am using Quartus II 4.2 and 5.0 (on two different machines)
web-editions for MAX II design. The chip is done and I know how to
simulate the design by forcing the input pins. But now I want to
simulate the chip with some simple off-chip logic. For example, I want
the output pin 'B' to feed the input pin 'A', then simulate the chip
again. How do I do that? I remember I have done that with XILINX
software by generating a simulation "shell" vhdl file, then editing the
vhdl file to fit in the logic. But how about Altera? Thank you!

vax, 9000


Article: 89067
Subject: Problem with interfacingT-VPACK with ALTERA QUIP5.0
From: "Narayan" <narayan.subramanian@gmail.com>
Date: 4 Sep 2005 20:52:26 -0700
Links: << >>  << T >>  << A >>
Hi All,

  I am having problem when interfacing T-VPACK
(http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html) with QUIP5.0.

  I have a 'test4.vhd' file:
  ---------------------------------------------------------
  library IEEE;
  use IEEE.STD_LOGIC_1164.ALL;

  entity test4 is
  port (	a	: in std_logic_vector(4 downto 0);
		b	: in std_logic_vector(4 downto 0);
		c	: out std_logic_vector(4 downto 0));
  end test4;

  architecture test4_arch of test4 is
  begin

	c <= a and b;

  end test4_arch;
  ----------------------------------------------------------

  I generated test4.blif for the above vhdl file. I then used the
following
  command in t-vpack: $: t-vpack test4.blif test4.net

  I got the following error:
  Error:  Net #10 (c[0]) has no driver and will cause
  memory corruption.

  Does anyone have suggestions to solve above problem?

Thanks,
Narayan


Article: 89068
Subject: coe file of Xilinx MAC FIR core??
From: "AdamS" <sutongqi@gmail.com>
Date: 4 Sep 2005 21:01:54 -0700
Links: << >>  << T >>  << A >>
I know that "coewrite" in matlab could give out the coe file for Xilinx
DA FIR core. but it seems that the same method does not suit for MAC
FIR core.

then...how could I get the coe file for a MAC FIR?


Article: 89069
Subject: Reading internal signals through a testbench.
From: "CODE_IS_BAD" <Puneetsingh81@gmail.com>
Date: 4 Sep 2005 23:11:51 -0700
Links: << >>  << T >>  << A >>
Hi all,
   Through a testbench (Verilog or VHDL), how do I read the values of
signals of a sub module through a top module? This is required to match
and assert if the program is working correctly. Please help. Thank you.

Best Regards,


Article: 89070
Subject: Re: I2C "SCL" line problem
From: praveen.kantharajapura@gmail.com
Date: 4 Sep 2005 23:26:47 -0700
Links: << >>  << T >>  << A >>
Hi Falk,

We cannot go for the Scmitt trigger option , because the PCB's are
already out.Could any thing be done to avoid flase triggering in FPGA's
only.

Regards,
Prav

Falk Brunner wrote:
> <alan@nishioka.com> schrieb im Newsbeitrag
> news:1125649231.259165.250930@g43g2000cwa.googlegroups.com...
>
> > I2C is an open-collector bus with a resistor pullup.
> > So the falling edge is sharp and the rising edge is exponential.
> >
> > I would guess that the rising edge is too slow and is causing problems
> > for your input buffer at the input threshold.
>
> Yes, you should use the schmitt trigger option for the input (if it is a
> coolrunner-II)
> I2C is terribly slow for nowadays CPLDs, so a rising edge can (and WILL)
> have enough noise on it to make the CPLD see double edges.
> I also suggest to NOT use SCL directly as a clock (for the given reason).
> Use a "high speed" (lets say 10 MHz) clock to sample SDA/SCL and make your
> state machine rung on this 10 MHz clock using the samples SDA/SCL.
> 
> Regards
> Falk


Article: 89071
Subject: Re: coe file of Xilinx MAC FIR core??
From: =?ISO-8859-1?Q?Johan_Bernsp=E5ng?= <xjohbex@xfoix.se>
Date: Mon, 05 Sep 2005 08:41:40 +0200
Links: << >>  << T >>  << A >>
AdamS wrote:
> I know that "coewrite" in matlab could give out the coe file for Xilinx
> DA FIR core. but it seems that the same method does not suit for MAC
> FIR core.
> 
> then...how could I get the coe file for a MAC FIR?
> 

Hi AdamS,

You can, for instance, export the coefficients from the FDA tool in 
MatLab to the workspace. Find out how much you should multiply the 
coefficients with to acheive the bit width you use. (That is, if you 
have 16-bit coefficients the largest coefficient should have the value 
32767 in order to optimize the filter). Multiply the coeff. vector by 
the number.
Next you can copy the coefficients from the variable viewer in MatLab 
and paste them in a file that looks something like this:

radix=10;
coefdata=352, 256, 332, 410, 484, 547, 595, ... ;

and save it as a .coe file. (You do have to do a replacement of all tab 
characters to ", " before saving, but that shouldn't be any problem i 
any decent editor.

For more info, see the filter documentation in coregen.

/Johan


-- 
-----------------------------------------------
Johan Bernspång, xjohbex@xfoix.se
Research engineer

Swedish Defence Research Agency - FOI
Division of Command & Control Systems
Department of Electronic Warfare Systems

www.foi.se

Please remove the x's in the email address if
replying to me personally.
-----------------------------------------------

Article: 89072
Subject: Re: bare die (non packaged) FPGA, CPLD, controllers ?
From: "Dix" <mystery@gmail.com>
Date: 5 Sep 2005 00:01:27 -0700
Links: << >>  << T >>  << A >>
Thanks Daniel,

You perhaps might have hints for Arm processors as dice ?

Dix.

www.testhaus.com


Article: 89073
Subject: Re: Problem with interfacingT-VPACK with ALTERA QUIP5.0
From: "raj" <r.p.bharadwaj@gmail.com>
Date: 5 Sep 2005 00:04:50 -0700
Links: << >>  << T >>  << A >>
Probably Dr Vaughn Betz will be the best person to answer this.
I too had the same prob.
Narayan wrote:
> Hi All,
>
>   I am having problem when interfacing T-VPACK
> (http://www.eecg.toronto.edu/~vaughn/vpr/vpr.html) with QUIP5.0.
>
>   I have a 'test4.vhd' file:
>   ---------------------------------------------------------
>   library IEEE;
>   use IEEE.STD_LOGIC_1164.ALL;
>
>   entity test4 is
>   port (	a	: in std_logic_vector(4 downto 0);
> 		b	: in std_logic_vector(4 downto 0);
> 		c	: out std_logic_vector(4 downto 0));
>   end test4;
>
>   architecture test4_arch of test4 is
>   begin
>
> 	c <= a and b;
>
>   end test4_arch;
>   ----------------------------------------------------------
>
>   I generated test4.blif for the above vhdl file. I then used the
> following
>   command in t-vpack: $: t-vpack test4.blif test4.net
>
>   I got the following error:
>   Error:  Net #10 (c[0]) has no driver and will cause
>   memory corruption.
>
>   Does anyone have suggestions to solve above problem?
> 
> Thanks,
> Narayan


Article: 89074
Subject: Re: Mentor FPGA Advantage, a simple question
From: ciappalastringa <fake@fake.it>
Date: Mon, 05 Sep 2005 10:17:21 +0200
Links: << >>  << T >>  << A >>

> Consider learning Modelsim all by itself first.
> You can't run synthesis until you have good
> code, and the only way to get good code
> is to edit/sim/edit/sim.


Thanks for your answer but I already have a
working code and my answer remain the same...



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