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> -----Original Message----- > From: John Williams [mailto:j2.williams@qut.edu.au] > Jonathan Bromley wrote: > > How say we invent > > a new type UFIX in which the lower (right) subscript bound > > determines the position of the binary point? Here's a bit > > of a package to get this idea started. Right at the end there's > > also a procedure AddAndTrunc() which gives some ideas about how > > the return value from the "+" operator could be processed. > > I suspect a suitably creative RESIZE() function could be written > > to do any re-scaling you might need. > > That's precisely what I was thinking - I was just being lazy to see if > anyone's done it before and released it! Not that I know of, but I confess I haven't looked very hard. > Can you assign attributes to existing types in VHDL? > Basically create a > subtype of std_logic_vector, and use attributes to carry around the > position of the binary point? Yes, but it would be a surprise if synthesis could recognise them. That's why I chose to encode the point position in the subscript range, which synthesis tools do understand. > I only had time to just glance at your code, but I'm > wondering, would it > support varying types within a single design? What I'm > thinking is that > you could declare a signal with say 3 integer and 5 frac. bits, and > another signal with 2 int. and 6 frac., then add them together, > multiply, whatever, and the results of those operations would be > automatically created to be the appropriate type. Yes, the overloaded "+" operator I wrote will do precisely that. > Maybe I'm asking too > much of VHDL (it's the C++ programmer in me coming out again!) Certainly not; anything C++ can do, VHDL can do better (OK, I made that bit up, it's not true :) ). There are a few issues with the approach I suggested. Effectively I'm imposing two new convention on std_logic_vectors: (1) the subscript range must always be DOWNTO; (2) the subscript value is tied to the bit's binary weight. Neither of these things is required for the existing integer arithmetic packages like NUMERIC_STD. Unfortunately, there's no way I know of to get VHDL to enforce either of these conventions (although the DOWNTO thing could be checked with an assertion). There's also the slightly unpleasant artificial notion of the fixed-point offset, to avoid using negative subscripts for the fractional part. VHDL supports negative subscripts (eat your heart out C++!) but using them in this context would introduce a bunch of unpleasant issues related to synthesis, and the inevitable business of casting the new fixed-point values to and from ordinary std_logic_vectors. Hence my "hack" with the fixed design-wide subscript offset. There are plenty of other ways to do fixed-point in VHDL - using record types springs to mind as the most obvious alternative - but I think the approach I suggested gets the best leverage out of VHDL's facilities. It has the disadvantage that we are giving a new meaning to the subscripts that is not familiar to most VHDL users and is not enforceable by the language. There is an important issue related to the result values from arithmetic operations. In VHDL, a function can return an unconstrained vector type, and constrain the return value when it executes - I used this in my example. However, I suspect you don't always want this behaviour in fixed point. I think I have a reasonably elegant solution to this problem, but I'm not going to shoot my mouth off about it until I've worked it out properly and found out how wrong it is!Article: 44951
Hi all! I'm a german student and want to buy an develpment-board for home. In the uni, we use Actel FPGAs and Synopsis on SUN-Stations. So I want to do some exercises at home and make some own developments e.g. EPP-Printerport-Interface for A/D-Converter. Now I don't know whats easier/cheaper/newer (for future-support) because I don't want to buy a newer one next year. Can you help me? StevenArticle: 44952
Hi folks, I have designed a modular prototyping platform for system and circuit designs (www.RAPTOR2000.de) that implements a Configuration Manager for (partial) (Re-)Configuration of Xilinx Virtex FPGAs at 50MByte/s via the SelectMAP port. It consists of a PCI-Bus motherboard and up to six (FPGA-)modules. All the FPGA boards I know do the reconfiguration via PCI-Bus by access to a register which drives the SelectMAP signals (CCLK toggles by set/reset the appropriate bit of the register). As I know by this way the maximus SelectMAP rate can not be reached. My Configuration Managers works in a different way. Anyone programs the manager by the location of the bitstream and the fpga-module that should be reconfigured and afterwards the manager reads the configuration data on its own (even when located in the main mem of the host computer) and reconfigures the FPGA at 50MByte/s. I want to compare my implementiation with other boards, but I do not know amy board that reconfigures at 50MByte/s. Can you tell me some? Heiko -- --------------------------------------------------------------- Dipl. Ing. H. Kalte | HEINZ NIXDORF INSTITUTE | Office: F1.213 System and Circuit Technology | Fon: +49 (0)5251 60-6459 Fürstenallee 11 | Fax: +49 (0)5251 60-6351 33102 Paderborn, Germany | --------------------------------------------------------------- mailto:kalte@hni.uni-paderborn.de http://wwwhni.uni-paderborn.de/sct/ --------------------------------------------------------------- Home of the RAPTOR Rapid Prototyping Systems http://www.RAPTOR2000.de/ ---------------------------------------------------------------Article: 44953
On Tue, 2 Jul 2002 16:47:13 +0200, "Falk Brunner" <Falk.Brunner@gmx.de> wrote: >"Thomas" <ThoLei@gmx.net> schrieb im Newsbeitrag >news:ee77a68.-1@WebX.sUN8CHnE... >> Dear Community! >> >> In my application I need to let the FPGA communicate with the PC. (I want >to write a small C++ program where you can enter some values) >> The demo board I use offers an serial RS-232 port but only with TXin and >RXout pins. So I suppose I must use some software handshake? >> And i have to implement a serial/parallel converter within the FPGA (vhdl >code?). > >A complete RS232 UART inluding 16 byte FIFO in both directions is ready to >use available for Spartan-II devices. Have a look at the xapps from Xilinx >(AFAIK 223 or so). For other families, you may try the UART from > >www.opencores.org > >If you need a intelligent salve inside the FPGA, I recommend having a look >at xapp213, which delivers a 8 bit RISC processor, ready to use. > >-- >MfG >Falk Hi, Implementing a simple SPI or JTAG type synchronous interface should take a lot less space in the FPGA, and you could simply bit-bang on the PC side via either the parallel port or serial port. Regards Anton ErasmusArticle: 44954
Hi all, I have to connect Camera Link connecteur (26 pin) to a Virtex-II FPGA (LVDS pins). What will be the easier schematic to do this connection. Thank for you advice LaurentArticle: 44955
Can anybody help me in generating clk2x,clk1x and 180 degree phase
shifted clk1x using DLL for spartan2 devices.
It gives the fallowing error in PAR
ERROR:Place:1726 - Could not find an automatic placement for the
following
components:
CLKIN of type GCLK IOB is unplaced.
dll of type DLL is unplaced.
clkg of type GCLK BUFFER is unplaced.
clk180g of type GCLK BUFFER is unplaced.
clk2xg of type GCLK BUFFER is unplaced.
ERROR:Place:1727 - Xilinx requires using locate constraints to
preplace such
connected GCLK/GCLKIO/DLL components.
Total REAL time to Placer completion: 2 secs
Total CPU time to Placer completion: 1 secs
Source file is given below .
library ieee;
use ieee.std_logic_1164.all;
library unisim;
use unisim.vcomponents.all;
entity dll_standard is
port (
CLKIN : in std_logic ;
RESET : in std_logic ;
CLK0 : out std_logic ;
CLK2X : out std_logic ;
CLK180 : out std_logic ;
LOCKED : out std_logic
);
end dll_standard;
architecture structural of dll_standard is
signal CLKIN_w, RESET_w, CLK0_dll, CLK0_g, CLK2X_dll,
LOCKED_dll,CLK180_DLL : std_logic;
begin
clkpad : IBUFG port map (I=>CLKIN, O=>CLKIN_w);
rstpad : IBUF port map (I=>RESET, O=>RESET_w);
dll : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLK0_g, RST=>RESET_w,
CLK0=>CLK0_dll, CLK90=>open, CLK180=>CLK180_DLL, CLK270=>open,
CLK2X=>CLK2X_dll, CLKDV=>open, LOCKED=>LOCKED_dll);
clkg : BUFG port map (I=>CLK0_dll, O=>CLK0_g);
clk2xg : BUFG port map (I=>CLK2X_dll, O=>CLK2X);
lckpad : OBUF port map (I=>LOCKED_dll, O=>LOCKED);
clk180g : BUFG port map (I=>CLK180_DLL, O=>CLK180);
CLK0 <= CLK0_g;
end structural;
Article: 44956Anton Erasmus wrote: > On Tue, 2 Jul 2002 16:47:13 +0200, "Falk Brunner" > <Falk.Brunner@gmx.de> wrote: > > >"Thomas" <ThoLei@gmx.net> schrieb im Newsbeitrag > >news:ee77a68.-1@WebX.sUN8CHnE... > >> Dear Community! > >> > >> In my application I need to let the FPGA communicate with the PC. (I want > >to write a small C++ program where you can enter some values) > >> The demo board I use offers an serial RS-232 port but only with TXin and > >RXout pins. So I suppose I must use some software handshake? > >> And i have to implement a serial/parallel converter within the FPGA (vhdl > >code?). > > > >A complete RS232 UART inluding 16 byte FIFO in both directions is ready to > >use available for Spartan-II devices. Have a look at the xapps from Xilinx > >(AFAIK 223 or so). For other families, you may try the UART from > > > >www.opencores.org > > > >If you need a intelligent salve inside the FPGA, I recommend having a look > >at xapp213, which delivers a 8 bit RISC processor, ready to use. > > > >-- > >MfG > >Falk > > Hi, > > Implementing a simple SPI or JTAG type synchronous interface should > take a lot less space in the FPGA, and you could simply bit-bang on > the PC side via either the parallel port or serial port. > > Regards > Anton Erasmus I'd say the MicroWire protocol (4 pin, used by the serial EEPROMs that hold config info for e.g. Ethernet controllers. 93LC46 is an example) is probably simpler than both. None of that tedious ACK/NACK stuff needed by SPI nor the fairly complicated SM needed by JTAG.Article: 44957
And on those pins that support 3.3V, they are are not PCI compliant.
You have to add clamping diodes or the chip can be damaged.
In article <3D2714E1.682C6BC7@attbi.com>, philtoms@attbi.com says...
> Correct. Only certain banks support 3.3v I/O.
>
> Guerre wrote:
>
> > Am I reading the data sheet correctly? Is it true that most of the pins are
> > not 3.3 volt tolerant on the Pro parts??!? Arrrgh!
--
gad
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
= Greg Deuerling, Fermi National Accelerator Laboratory =
= P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629, FAX (630)840-5406 =
= Electronic Systems Engineering Group =
= Work: egads@fnal.gov Personal: gad@elnet.com =
=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=
Article: 44958You can add diodes to prevent damage, but that is NOT PCI compliant. To meet the PCI 3.3 volt spec you MUST have the clamping diodes inside the chip. This keeps the load capacitance down and prevents SI issues from stubbing. Greg Deuerling wrote: > > And on those pins that support 3.3V, they are are not PCI compliant. > You have to add clamping diodes or the chip can be damaged. > > In article <3D2714E1.682C6BC7@attbi.com>, philtoms@attbi.com says... > > Correct. Only certain banks support 3.3v I/O. > > > > Guerre wrote: > > > > > Am I reading the data sheet correctly? Is it true that most of the pins are > > > not 3.3 volt tolerant on the Pro parts??!? Arrrgh! > -- > gad > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= > = Greg Deuerling, Fermi National Accelerator Laboratory = > = P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629, FAX (630)840-5406 = > = Electronic Systems Engineering Group = > = Work: egads@fnal.gov Personal: gad@elnet.com = > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44959
this is an easy one to fix, you have to tell the PAR tools which DLL and
buffers you want to use for the dll signals and the dll itself.
the best way for me to show you this is by example...
here's a dll code that I use
signal CLKIN, CLK, CLK0, CLK2X, CLKDV: std_logic;
signal RST, LOCKED_ONE : std_logic;
--association of architectures
component CLKDLL
port (CLKIN, CLKFB, RST : in STD_LOGIC;
CLK0, CLK90, CLK180, CLK270, CLK2X, CLKDV, LOCKED : out std_logic);
end component;
component IBUFG
port (I : in STD_LOGIC; O : out std_logic);
end component;
component BUFG
port (I : in STD_LOGIC; O : out std_logic);
end component;
begin -- architecture of Clock Dll
Clock_Shadowed <= CLK;
LOCKED <= LOCKED_ONE;
U1: IBUFG port map (I=>Source_Clock, O=>CLKIN);
U2: CLKDLL
-- synopsys synthesis_off
generic map( CLKDV_DIVIDE_VALUE, DUTY_CYCLE_CORRECTION_VALUE,
STARTUP_WAIT_VALUE)
-- synopsys synthesis_on
port map ( CLKIN=>CLKIN,
CLKFB=>CLK,
RST=>Reset,
CLK0=>CLK0,
CLK2X => CLK2X,
CLKDV => CLKDV,
LOCKED=>LOCKED_ONE);
U3: BUFG port map (I=>CLK0, O=>CLK);
U4: BUFG port map (I=>CLK2X, O=>Clock_Multiplied);
U5: BUFG port map (I=>CLKDV, O=>Clock_Divided);
and in my ucf i have the following lines:
INST tx_dll_u2 clkdv_divide = 2.5;
INST tx_dll_u2 startup_wait = TRUE;
INST tx_dll_u2 LOC = DLL0;
INST tx_dll_u3 LOC = GCLKBUF0;
INST tx_dll_u4 LOC = GCLKBUF1;
INST tx_dll_u5 LOC = GCLKBUF3;
tx_dll is the label given to the dll instatiation in the next layer of
heirarchy
there are some xapps on this subject too!
HTH
Benjamin Todd
European Organisation for Nuclear Research
SL SPS/LHC -- Control -- Timing Division
CERN, Geneva, Switzerland, CH-1211
Building 864 Room 1 - A24
"Kumar" <yatiks@yahoo.com> wrote in message
news:b479edf8.0207080404.22a2e525@posting.google.com...
> Can anybody help me in generating clk2x,clk1x and 180 degree phase
> shifted clk1x using DLL for spartan2 devices.
> It gives the fallowing error in PAR
> ERROR:Place:1726 - Could not find an automatic placement for the
> following
> components:
> CLKIN of type GCLK IOB is unplaced.
> dll of type DLL is unplaced.
> clkg of type GCLK BUFFER is unplaced.
> clk180g of type GCLK BUFFER is unplaced.
> clk2xg of type GCLK BUFFER is unplaced.
> ERROR:Place:1727 - Xilinx requires using locate constraints to
> preplace such
> connected GCLK/GCLKIO/DLL components.
> Total REAL time to Placer completion: 2 secs
> Total CPU time to Placer completion: 1 secs
>
> Source file is given below .
>
> library ieee;
> use ieee.std_logic_1164.all;
> library unisim;
> use unisim.vcomponents.all;
>
> entity dll_standard is
> port (
> CLKIN : in std_logic ;
> RESET : in std_logic ;
> CLK0 : out std_logic ;
> CLK2X : out std_logic ;
> CLK180 : out std_logic ;
> LOCKED : out std_logic
> );
> end dll_standard;
>
> architecture structural of dll_standard is
>
> signal CLKIN_w, RESET_w, CLK0_dll, CLK0_g, CLK2X_dll,
> LOCKED_dll,CLK180_DLL : std_logic;
>
> begin
>
> clkpad : IBUFG port map (I=>CLKIN, O=>CLKIN_w);
> rstpad : IBUF port map (I=>RESET, O=>RESET_w);
>
> dll : CLKDLL port map (CLKIN=>CLKIN_w, CLKFB=>CLK0_g, RST=>RESET_w,
> CLK0=>CLK0_dll, CLK90=>open, CLK180=>CLK180_DLL, CLK270=>open,
> CLK2X=>CLK2X_dll, CLKDV=>open, LOCKED=>LOCKED_dll);
>
> clkg : BUFG port map (I=>CLK0_dll, O=>CLK0_g);
> clk2xg : BUFG port map (I=>CLK2X_dll, O=>CLK2X);
> lckpad : OBUF port map (I=>LOCKED_dll, O=>LOCKED);
>
> clk180g : BUFG port map (I=>CLK180_DLL, O=>CLK180);
>
> CLK0 <= CLK0_g;
>
> end structural;
Article: 44960go to the licensing wizard and post what is says for your licence... in win 2k (on my computer) Start -> Programs -> ModelSim XE II 5.5e -> Licensing Wizard -- Benjamin Todd European Organisation for Nuclear Research SL SPS/LHC -- Control -- Timing Division CERN, Geneva, Switzerland, CH-1211 Building 864 Room 1 - A24 "Derrick Cheng" <cdcheng@uiuc.edu> wrote in message news:Ke2W8.2708$m7.26250@vixen.cso.uiuc.edu... > Everytime I run the simulation, the ModelSim(Free version) says that my > license file is > invalid, such that I could not perform the simulation. > I got the license file from the Xilinx, and I installed the license > successfully with the License program. > > I am just wondering anybody has the similar situation like mine, and how can > I solve the problem. > Thanks. > > >Article: 44961
Hello, I am encountering differences between the Behavioral- and Post Place&Route-Simulation. I am targeting a Virtex2 device. When assigning the reset signal for one clock (the first clock in simulation), it seems this signal is internaly active for two or three clocks. Could this be possible or is this a completely different effect? Is this the simulation of the Startup-Sequence of the FPGA? Greetings, HolgerArticle: 44962
Hi John, did you check the Cesys FPGA development boards XC2S_EVAL and X2S_USB ? They use XC2S200 SPARTAN-II FPGAs and come with examples and Download/Debug/Monitoring Software. You can download all tools and documentation as well as the complete SCHEMATICS OF THE BOARDS from our website. To compile, place & route your sources, the free Xilinx WebPack is all you need. here is the link: http://www.cesys.com/english/indexenglish.htm best regards Manfred Kraus -------------------------------- CESYS GmbH Zeppelinstrasse 6a D-91074 Herzogenaurach Tel. +49 9132 733 400 Fax. +49 9132 733 401 Email mkraus@I_HATE_SPAWN_cesys.com URL http://www.cesys.com --------------------------------Article: 44963
"Derrick Cheng" schrieb: > invalid, such that I could not perform the simulation. > I got the license file from the Xilinx, and I installed the license > successfully with the License program. The License is bound to the MAC-Address of your Network card. Did you registered, downloaded and work with the same computer? Greetings, HolgerArticle: 44964
This is a multi-part message in MIME format. --------------D17FE15063D530CA0ABA088D Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi, You can check out a PCI with Virtex-II Pro reference at http://www.xilinx.com/xapp/xapp653.pdf --Stephan rickman wrote: > You can add diodes to prevent damage, but that is NOT PCI compliant. To > meet the PCI 3.3 volt spec you MUST have the clamping diodes inside the > chip. This keeps the load capacitance down and prevents SI issues from > stubbing. > > Greg Deuerling wrote: > > > > And on those pins that support 3.3V, they are are not PCI compliant. > > You have to add clamping diodes or the chip can be damaged. > > > > In article <3D2714E1.682C6BC7@attbi.com>, philtoms@attbi.com says... > > > Correct. Only certain banks support 3.3v I/O. > > > > > > Guerre wrote: > > > > > > > Am I reading the data sheet correctly? Is it true that most of the pins are > > > > not 3.3 volt tolerant on the Pro parts??!? Arrrgh! > > -- > > gad > > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= > > = Greg Deuerling, Fermi National Accelerator Laboratory = > > = P.O.Box 500 MS368 Batavia, IL 60510 (630)840-4629, FAX (630)840-5406 = > > = Electronic Systems Engineering Group = > > = Work: egads@fnal.gov Personal: gad@elnet.com = > > =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44965
Hello, I am designing my first PLD using VHDL (for a real product) and am concerned that the design will be clean and free of race conditions and can be safely synthesized using CPLD (initially Xilinx 9500), FPGA, standard cells and ASICS. The design follows the guide lines listed below. I wonder if anybody can comment if these guidelines guaranty a safe design. 1. All flip flops are triggered only by the rising edge of a central clock. 2. There is only one clock in the system and it is used only to directly trigger flip flops (that is, it is not used in any combinatorial logic). 3. Every cyclic data path goes through at least one flip flop. 4. Every path between input and output pins goes through at least one flip flop. 5. The up and down times of the clock are at least an order of magnitude longer than the delay of any data path (the central clock is 4MHZ at most). Any comment will be greatly appreciated. For example, should I worry about clock skew between the flip flops, should I partition the flip flops to two groups, triggered on rising and falling edges of the clock respectively ? Thanks, TalArticle: 44966
The guidelines are safe because they are over-designed. Note that your thought of partitioning into two groups for rising and falling edge triggered flops violates design guideline #1. One clock is the cleanest you can get in a design. Most designers end up with multiple clocks, often dictated by different interfaces that must each be synchronized to each other with appropriate logic. One clock domain means there's no synchronization needed. The race conditions are avoided by having "at least one flip flop" in a feedback or "cyclic data path." A race condition is where an input can change the data to itself which changes the data to itself which changes the data to itself which... While it is inherently safe to have an input feed directly to an output with combinatorial logic, the chip interface is simplified by having all inputs meet a setup/hold and have all outputs defined with a clock-to-out. Sometimes a combinatorial in-to-out is necessary to meet strict timing requirements in system design. The clock period in modern components is easily defined with user timing constraints. The requirement for "an order of magnitude" is superfluous in CPLD and FPGA design. You need to know how to trade off speed and design complexity for high speed designs but designing with a very slow clock almost makes logic delays a non-issue. Too much logic between flops - referred to as "levels of logic" for each time you go through another lookup table or combinatorial CPLD macrocell - can compromise even the long clock periods. Good high speed designs can challenge both the silicon and the designer. You're 100% safe with those guidelines from a functional perspective. Now just don't ever wire up the wrong voltage signals on your parts! TED wrote: > Hello, > > I am designing my first PLD using VHDL (for a real product) and am > concerned that the design will be clean and free of race conditions > and can be safely synthesized using CPLD (initially Xilinx 9500), > FPGA, standard cells and ASICS. > > The design follows the guide lines listed below. I wonder if anybody > can comment if these guidelines guaranty a safe design. > > 1. All flip flops are triggered only by the rising edge of a central > clock. > > 2. There is only one clock in the system and it is used only to > directly trigger flip flops (that is, it is not used in any > combinatorial logic). > > 3. Every cyclic data path goes through at least one flip flop. > > 4. Every path between input and output pins goes through at least one > flip flop. > > 5. The up and down times of the clock are at least an order of > magnitude longer than the delay of any data path (the central clock is > 4MHZ at most). > > Any comment will be greatly appreciated. For example, should I worry > about clock skew between the flip flops, should I partition the flip > flops to two groups, triggered on rising and falling edges of the > clock respectively ? > > Thanks, > > TalArticle: 44967
I ran into the same problem and was told by tech support to edit my edif file. You need to delete all lines containing RLOC or HU_SET. The following commands work well in vi editor. g/RLOC/d g/HU_SET/d "Steven Elzinga" <steven.elzinga@xilinx.com> wrote in message news:3D1CB092.FAE79A6B@xilinx.com... > Charles, > > If possible contact Synplicity support for this problem. Xilinx and > Synplicity will work together to resolve these kinds of issues. These > types of problems that I have seen in the past require the design > files/project to debug exactly what is going wrong. > > regards > > Steve > > > Charles Wagner wrote: > > > I am using Amplify with block regions to optimize a Virtex XCV800 > > implementation with TOP. > > Compiling is OK : no error in Synplify log file. > > (.... Region regrgn5 : TOPS successfull.....) > > > > But when running Xilinx tools i get this messages in map.mrp > > > > Anyone know what's wrong? > > > > CharlesArticle: 44968
Radoslaw Mitura (mitek@ue.eti.pg.gda.pl) wrote: : I have two chips in JTAG scan chain: XC95144xl and XCV50e. : On some nets between those chips i have pullup. : I tried to extest both of the chips. : When I driving net without pullup it is ok, but when i trying : to driving net with pullup something goes wrong: : I can drive from XC95144xl and receive on XCV50e but : I can't do that in reverse direction (drive from XCV50e and receive on : XC95144xl). : Cell when I tried to receive is in third state. : Where is the problem? : Regards : Mitek Did you try removing the pullup to see if it would work? Does the pull up have to low of a value? Is it pulled up to the wrong voltage level? Are the drivers and receivers configured properly? John EatonArticle: 44969
John Hovell wrote:
>
> Hello all --
>
> I am embarking on a new FPGA project, and I was hoping to get some
> recommendations for the FPGA, prototyping board, or programming environment.
>
>
> My new project constraints are:
> - ~300KB ROM
> - 132 Kb (16.5 KB) Block Memory or Distributed memory (I'm a bit fuzzy
> on which one I should be using)
> - ~300 KB of off-chip static RAM
> - 100-200k gates for logic
> - enough room for error in case any of the above are wrong
> - budget for prototype of about $1000 including software (I already
> have a PC)
>
I hate to see people selling FPGA prototyping boards
recommending their own boards. (i.e., Several people before me who
replied to this topic.)
I cannot think of a board that meets your requirement, but you can try
Insight Electronics or Avnet (They are both Xilinx distributors.) which
both sell Xilinx-based prototype boards.
> My questions are:
> 2) How does one make Block RAM or Distributed RAM without using CORE
> Generator? I'll be programming in Verilog, but I'm not sure how to tell
> the compiler I want to make a Block RAM or Distrbuted RAM. I can't
> afford Foundation for $2500, but maybe BaseX is available for $99 on
> some sort of promotion (saw this earlier on the NG)?
>
I know you are aware of it, but use ISE WebPACK which is free.
To use on-chip RAM, instantiate RAM primitives (Virtex or Spartan-II
datasheets should mention how to do it) from your Verilog code.
> 3) What clock speeds are typical for most people using FPGA's? A few
> years ago I was making designs in the 25-50 MHz range on Virtex and
> Spartan FPGA's. I saw some people claiming 380 MHz for designs. A
> typical pipeline stage in my design might have a 16-bit adder. Is the
> -4, -5, or -6 speed rating important for me? (I'm not trying to
> super-optimize here... just get a workable design without spending more
> $ than I have to.)
> Along these lines, I saw people on this NG referring
> to hand-optimization. Does the Xilinx software let you do this? I've
> always just hit "implement" and not much else...
>
You are talking about Floorplanner, which lets you place logic
to certain places to the chip.
When properly placed, I will say that Floorplanner can reduce total
delay (gate delay + routing delay) by 15 to 20%.
The reason you can reduce the delays by using Floorplanner that much is
because automatic P&R isn't that good at placing relevant logic close to
each other.
> I was leaning towards the 250k gate Virtex II since I could use it with
> Xilinx Web Pack (for free :-)) but I couldn't find a protoboard out
> there for this chip -- let alone one that has agreeable features and
> price. If I stuck with what I'm used to, I could get Xess's board based
> on the 300k gate Virtex for $900 with 2MB of static RAM... but something
> tells me I could do better for my money -- if this would even accomodate
> my design (I'm not sure).
>
> So I'm totally open for suggestions, advice, info, etc.... any you could
> give would me much appreciated. Thanks!
>
> Cheers,
> John
I am sure you are aware of it, but ISE WebPACK doesn't support
Virtex 300K system gate part (XCV300), although Virtex-E 300K system
gate part (XCV300E) is supported.
If your application doesn't have to connect to 5V peripherals (i.e.,
TTL), you should use Virtex-E 300K system gate part or Spartan-IIE 300K
system gate part.
Although Spartan-IIE is much cheaper than Virtex-E (Typically, 1/3 of
the price of Virtex-E.), you only get half of the Block RAM of Virtex-E.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44970Hello, we had a problem with the clockbuffer in a Spartan-XCS40XL. The state machines sometimes went crazy. It is a one hot design. By accident, we fixed the problem by changing the clock buffer from the left upper corner to the right lower corner of the chip. We have used only one clocknet with 20Mhz for all flipflops. Now we have transferred the design from XL to Spartan-2E. The state machines again behave sometimes crazy. I guess we have 1000 or more flipflops on that clock net. The power supply voltages are ok. Is there a limit for the number of flipflops one one clocknet? Any idea what is going wrong? Best Regards HelmutArticle: 44971
The first 4 points are reasonable, albeit very conservative. Point 5 is wrong. Clock High and Low times do not matter, as long as they exceed the min value of a few nanoseconds. The number of combinatorial delays accomodated in one clock period ( period is the constraint, not High or Low time) depends on your design. You will inevitably know the number of combinatorial stages between any two flip-flops. Add up their delays, and make sure the sum less than a clock period minus the required set-up time. At 4 MHz you will never have a problem... Peter Alfke, Xilinx Applications. ========================================== TED wrote: > Hello, > > I am designing my first PLD using VHDL (for a real product) and am > concerned that the design will be clean and free of race conditions > and can be safely synthesized using CPLD (initially Xilinx 9500), > FPGA, standard cells and ASICS. > > The design follows the guide lines listed below. I wonder if anybody > can comment if these guidelines guaranty a safe design. > > 1. All flip flops are triggered only by the rising edge of a central > clock. > > 2. There is only one clock in the system and it is used only to > directly trigger flip flops (that is, it is not used in any > combinatorial logic). > > 3. Every cyclic data path goes through at least one flip flop. > > 4. Every path between input and output pins goes through at least one > flip flop. > > 5. The up and down times of the clock are at least an order of > magnitude longer than the delay of any data path (the central clock is > 4MHZ at most). > > Any comment will be greatly appreciated. For example, should I worry > about clock skew between the flip flops, should I partition the flip > flops to two groups, triggered on rising and falling edges of the > clock respectively ? > > Thanks, > > TalArticle: 44972
Hi! Somebody knows how to use the J2 and J3 connectors into the Altera SOPC Board? It has a APEX20K400EBC652-1, and several interfaces, like Ethernet, RS232, IEEE 1394, USB, LCD display, etc, but hasn't general use pins, like the UP1 board has the FLEX_EXPAN barrament. The connectors J2 and J3 has 64-pins and are white. Somebody have worked yet wiht them? I will be thanked with any help. Regards, Bruno Bohrer Cozer Federal University of Rio Grande do Sul Porto Alegre - RS - BRAZILArticle: 44973
For Xilinx you might want to take a look at http://www.digilentinc.com/ The boards are low cost and supported by WebPack software (WebPack is FREE off the web) Stefan Schulte wrote: > Hi all! > > I'm a german student and want to buy an develpment-board for home. > In the uni, we use Actel FPGAs and Synopsis on SUN-Stations. > So I want to do some exercises at home and make some own developments > e.g. EPP-Printerport-Interface for A/D-Converter. > > Now I don't know whats easier/cheaper/newer (for future-support) > because I don't want to buy a newer one next year. > Can you help me? > > Steven -- ***************************** Anna M. Acevedo Manager Xilinx University Program 2100 Logic Drive San Jose, CA 95124 PH: (408) 879-5338 FAX: (408) 371-4836 Email: anna.acevedo@xilinx.com http://university.xilinx.com *****************************Article: 44974
Thanks for the review. BTW, the design is not 'over designed', the FPGA/PLD's are. ;-) Seriously, this is a straight forward design based on the system requirements. The guide lines was defined after the fact as a formal tool to analyze the correctness of the design. From your answer I presume that any synthesized PLD/ASIC will guaranty that if two flip flops gets the same external clock and the output of the first feeds the input of the second, the system will behave properly (that is, clock skew will not cause the second flip flop to sample the new data of the first flip flop). Tal On Mon, 08 Jul 2002 16:20:57 GMT, John_H <johnhandwork@mail.com> wrote: >The guidelines are safe because they are over-designed. Note that your >thought of partitioning into two groups for rising and falling edge >triggered flops violates design guideline #1. > >One clock is the cleanest you can get in a design. Most designers end up >with multiple clocks, often dictated by different interfaces that must >each be synchronized to each other with appropriate logic. One clock >domain means there's no synchronization needed. > >The race conditions are avoided by having "at least one flip flop" in a >feedback or "cyclic data path." A race condition is where an input can >change the data to itself which changes the data to itself which changes >the data to itself which... > >While it is inherently safe to have an input feed directly to an output >with combinatorial logic, the chip interface is simplified by having all >inputs meet a setup/hold and have all outputs defined with a >clock-to-out. Sometimes a combinatorial in-to-out is necessary to meet >strict timing requirements in system design. > >The clock period in modern components is easily defined with user timing >constraints. The requirement for "an order of magnitude" is superfluous >in CPLD and FPGA design. You need to know how to trade off speed and >design complexity for high speed designs but designing with a very slow >clock almost makes logic delays a non-issue. Too much logic between flops >- referred to as "levels of logic" for each time you go through another >lookup table or combinatorial CPLD macrocell - can compromise even the >long clock periods. Good high speed designs can challenge both the >silicon and the designer. > >You're 100% safe with those guidelines from a functional perspective. Now >just don't ever wire up the wrong voltage signals on your parts! > > > >TED wrote: > >> Hello, >> >> I am designing my first PLD using VHDL (for a real product) and am >> concerned that the design will be clean and free of race conditions >> and can be safely synthesized using CPLD (initially Xilinx 9500), >> FPGA, standard cells and ASICS. >> >> The design follows the guide lines listed below. I wonder if anybody >> can comment if these guidelines guaranty a safe design. >> >> 1. All flip flops are triggered only by the rising edge of a central >> clock. >> >> 2. There is only one clock in the system and it is used only to >> directly trigger flip flops (that is, it is not used in any >> combinatorial logic). >> >> 3. Every cyclic data path goes through at least one flip flop. >> >> 4. Every path between input and output pins goes through at least one >> flip flop. >> >> 5. The up and down times of the clock are at least an order of >> magnitude longer than the delay of any data path (the central clock is >> 4MHZ at most). >> >> Any comment will be greatly appreciated. For example, should I worry >> about clock skew between the flip flops, should I partition the flip >> flops to two groups, triggered on rising and falling edges of the >> clock respectively ? >> >> Thanks, >> >> Tal
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