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it looks like you have made a gate level model of your testbench!!! try and do a manual compile for simulation! heres a quick run through of how I do it (may not be the best method mind) 1. Run generate post-timing model of your uut 2. when its done, open model sim (i.e. from Start menu not from project navigator) 3. change your work directory to the right one 4. compile your component (timing) 5. compile the testbench 6. compile any other stuff you need (timing or not) 7. attach the timing model file SDF to the uut 8. load testbench 9. run simulation et voila!! HTH -- Benjamin Todd European Organisation for Particle Physics SL SPS/LHC -- Control -- Timing Division CERN, Geneva, Switzerland, CH-1211 Building 864 Room 1 - A24 "Anthony Ellis" <anthony@ams.co.za> wrote in message news:3d109c82.0@news1.mweb.co.za... > Hi guysm > > Any idea why I get the error at the last line? > Behavioral simulation & XST mapping, routing etc. all execute/complete > correctly but now I am trying to functionally simulate the gate-level. > Note this error also appears when one merely tries to simulate the > "simprim.x_tri_v". > > Thanks Anthony > > # Loading C:/DesignTools/ModelSim/win32pe/../std.standard > # Loading C:/DesignTools/ModelSim/win32pe/../ieee.std_logic_1164(body) > # Loading C:/DesignTools/ModelSim/win32pe/../ieee.numeric_std(body) > # Loading C:/DesignTools/ModelSim/win32pe/../std.textio(body) > # Loading C:/DesignTools/ModelSim/win32pe/../ieee.vital_timing(body) > # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.vcomponents > # Loading C:/DesignTools/ModelSim/win32pe/../ieee.vital_primitives(body) > # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.vpackage(body) > # Loading C:/Projects/DAU30/ARINC_FPGA/Ver_xx/WORK.top_level_tb(struct) > # Loading C:/DesignTools/ModelSim/win32pe/../ieee.std_logic_arith(body) > # Loading C:/DesignTools/ModelSim/win32pe/../ieee.std_logic_unsigned(body) > # Loading C:/Projects/DAU30/ARINC_FPGA/Ver_xx/WORK.top_level(structure) > # Loading > C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_zero(x_zero_v) > # Loading > C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_lut4(x_lut4_v) > # Loading > C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_lut3(x_lut3_v) > # Loading > C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_lut2(x_lut2_v) > # Loading > C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_mux2(x_mux2_v) > # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_ff(x_ff_v) > # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_sff(x_sff_v) > # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_inv(x_inv_v) > # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_one(x_one_v) > # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_buf(x_buf_v) > # Loading C:/DesignTools/Xilinx_Simulation_Libraries/simprim.x_tri(x_tri_v) > # ** Fatal: (vsim-3420) Array sizes do not match. Left is 8. Right is > 4231879. > # Time: 0 ns Iteration: 0 Region: > /top_level_tb/m_top_level/c_trdy_n_obuft > >Article: 44451
Any mailing list or news group interface to the Xilinx forums. It is kind of pain to use the web interface on a daily basis. Thanks, Tal On Wed, 19 Jun 2002 08:57:15 -0800, Patrick <> wrote: >answered in the Xilinx General Forum... > >PatrickArticle: 44452
"Austin Lesea" <austin.lesea@xilinx.com> wrote in message news:3D0F9FCF.2AE2A8B3@xilinx.com... > Also, Virtex is 5V tolerant without any resistor at all (ie 5V PCI interface IO > standard). It is only in Virtex E and later parts where the resistor is going to > be (possibly) required. Hi Austin, I believe he said he wanted to use a Spartan II. Does the same still apply? Regards, Austin P.S. The 3.3V EDO DRAMs seem to work fine with the 5V Spartan part...I have 18 boards that has been used quite heavily, two for a few weeks now, 24 hours a day, and we've seen not a wit of a problem. Thanks again for your support there!Article: 44453
How about Base-X? Does that provide a schematic viewer? Stephan Neuhold wrote: > > Hi Dmitri, > > Unfortunately the current version of XST does not have a schematic > viewer. This will only be available in the next major software release > (sometime later this year). > > Regards, > Stephan > > Dmitri Katchalov wrote: > > > Hi, > > > > I'm starting with FPGA. I've just downloaded Xilinx WebPack > > and I'm going through the tutorials. Everything seems to work > > fine as far as I can tell. > > > > My question is: [how] can I view the results of the synthesis? > > I would expect to see a schematics made up from LUTs and FFs > > or a boolean expression for each FF or something of that sort. > > > > I want to try several different variations of the same design > > and see how it affects the result. Just like I do with assembler > > output produced by a C compiler. > > > > Am I missing something obvious here or is it too much to ask? > > > > Thanks, > > Dmitri -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44454
Sounds to me like you understand what you want to do with the block rams. As long as you understand that they are synchronous rams and need a clock, you should be in good shape. You will need a clock that is faster than your read or write strobes by at least 2x. You will then have to design some logic to detect the write strobe and address and generate a synchronous write enable for the block ram. The read strobe should work to enable the tristate buffers and/or output multiplexer. But you will have to design this interface yourself. The block rams are designed to support logic design, not as a direct interface to your CPU. Think about it. If the block rams had a tristate output, they are inside the chip! Tristate outputs have little use inside the FPGA. Add a mux with the select input from one of the address lines and be done with it! You need to stop thinking that the internal logic of an FPGA is designed with direct interfacing to a CPU in mind. It is not, it is designed to be as flexible as possible so that you can interface the internal logic to whatever you want! So put on your logic engineer's hat and do some designing! Nagaraj wrote: > > No, could you please tell me how to do that in VHDL? > > To be specific, I require the following. I have two dual port > blockRAMs one used for external writing(external to FPGA) and internal > reading. The other is used for External reading and internal writing > (i.e. assume that one BlockRAM is used as a read memory space and the > other as a write memory space). > Now I want data-in of first BlockRAM and data-out of second blockRAM > to connect to system data bus. And address buses of both BlockRAMs to > be connected to system address bus (all through tri-state IO buffers > as you suggested). > Also external control signals of the FPGA(read,write,chip > select,read/write clock) should be interfaced to the corresponding > signals in both the BlockRAMs. > > Thanx in advance, > Nagaraj CS > > rickman <spamgoeshere4@yahoo.com> wrote in message news:<3D109052.9B08CF60@yahoo.com>... > > Block ram is not intended to be the same as a RAM chip. There is no tri > > state buffer on the output. If you want to connect it to a bus, you > > need to add the tri state buffer or use a mux. > > > > Do you know how to do that in an HDL? -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 44455
"Dan Kuechle" <danielgk@voomtech.com> schrieb im Newsbeitrag news:M%7Q8.16$ct2.24969@ruti.visi.com... > So, knowing the net name, and being able to find the CLB in FPGA Editor, how > do I find the bel name? (once I know the bel name I can find the CLB by > searching > for a bel in FPGA Express, but that doesn't help much) If the signal is directly comming from a FlipFlop, it will keep the name from the VHDL code. Have a look at the floorplanner after mapping, there you will find all your FlipFlops and LUTs. -- MfG FalkArticle: 44456
Anthony, Good questions. I have not thought too deeply about Unisim, but my general belief is that they are there to allow instantiation of functionality into your VHDL/ Verilog/ Schematic design, and provide functional simulation capabilities. After synthesis, one uses the Simprim libraries, and I have never questioned that approach. I suspect that this library is required in order to back-annotate timing delays from the Standard Delay Format (SDF) file for timing simulation purposes. Getting the X's out of a synthesized design may frusterate the new user, and sometimes the veteran user as well. One needs to be cognisant of the timing constraints placed on the design by the UCF file. When one does functional simulations, one is almost dealing with an ideally fast part. After place and route, there are real world timing delays, and the design may not work at 200 Mhz any more. Other issues to consider are: Are your memory storage elements getting initialized at the start of your simulation? Is the setup and hold time of your testbench compliant with the UCF file? Is your simulator default resolution set correctly? Are the Xilinx tools optimizing away portions of your design because of coding errors? One thing you could try would be to put in a divide by two test circuit, and see if you can make that simulate after synthesis, and gradually debug the circuits that are giving you problems. Hope this helps, NewmanArticle: 44457
Hello everyone, I have a design which consists of two big parts, one is developed by me, the other by a colleague. For testing I would like to keep this two modules seperate, so that I create a EDIF netlist without IO port from both modules and instanciaze them in a toplevel. So we save time in the compilation. After this I would like to run a normal design flow (Translate-> Map P&R) to get the final design. How can I generate such EDIF files. I tried to use the tools supplied by Xilinx (ngd2 edif) but when translating the final design, I get tons of warnings (like ".... INIT is not allows on x_LUT3...") and errors, complaining about x_BRAM4_S1_s1 . . .is not supported". Any advice will be very appreciated. -- MfG FalkArticle: 44458
SpartanII and Virtex have 5v tolerant 3.3v I/O.
Austin Franklin wrote:
> "Austin Lesea" <austin.lesea@xilinx.com> wrote in message
> news:3D0F9FCF.2AE2A8B3@xilinx.com...
>
> > Also, Virtex is 5V tolerant without any resistor at all (ie 5V PCI
> interface IO
> > standard). It is only in Virtex E and later parts where the resistor is
> going to
> > be (possibly) required.
>
> Hi Austin,
>
> I believe he said he wanted to use a Spartan II. Does the same still apply?
>
> Regards,
>
> Austin
>
> P.S. The 3.3V EDO DRAMs seem to work fine with the 5V Spartan part...I have
> 18 boards that has been used quite heavily, two for a few weeks now, 24
> hours a day, and we've seen not a wit of a problem. Thanks again for your
> support there!
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44459
YOu can get a mapped synthesis output from the synthesizer which is
constructed of unisim library elements. In Synplify you turn on mapped
output and it produces a .vhm (mapped VHDL or .vm mapped verilog output)
which is a unisim primitive only realization of your design. This can be
useful to check the results of synthesis before going into the XIlinx
tools, and it runs a bunch faster than the simprim xilinx output files.
newman wrote:
> Anthony,
> Good questions. I have not thought too deeply about Unisim, but my
> general belief is that they are there to allow instantiation of
> functionality into your VHDL/ Verilog/ Schematic design, and provide
> functional simulation capabilities. After synthesis, one uses the
> Simprim libraries, and I have never questioned that approach. I
> suspect that this library is required in order to back-annotate timing
> delays from the Standard Delay Format (SDF) file for timing simulation
> purposes.
>
> Getting the X's out of a synthesized design may frusterate the new
> user, and sometimes the veteran user as well. One needs to be
> cognisant of the timing constraints placed on the design by the UCF
> file. When one does functional simulations, one is almost dealing
> with an ideally fast part. After place and route, there are real
> world timing delays, and the design may not work at 200 Mhz any more.
> Other issues to consider are:
> Are your memory storage elements getting initialized at the start
> of your simulation?
> Is the setup and hold time of your testbench compliant with the UCF
> file?
> Is your simulator default resolution set correctly?
> Are the Xilinx tools optimizing away portions of your design
> because of coding errors?
>
> One thing you could try would be to put in a divide by two test
> circuit, and see if you can make that simulate after synthesis, and
> gradually debug the circuits that are giving you problems.
>
> Hope this helps,
>
> Newman
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44460Tell us what your synthesizer is. If you were using Synplify, it would be a matter of 1) specifying the output as EDIF, 2) compiling without I/O Insertion for the lower level module(s), and 3) specifying the lower level modules as "black boxes" for use by the higher level module. I think I've got all the points here. Someone else can probably help with your tool. Falk Brunner wrote: > Hello everyone, > > I have a design which consists of two big parts, one is developed by me, the > other by a colleague. > For testing I would like to keep this two modules seperate, so that I create > a EDIF netlist without IO port from both modules and instanciaze them in a > toplevel. So we save time in the compilation. After this I would like to run > a normal design flow (Translate-> Map P&R) to get the final design. > How can I generate such EDIF files. I tried to use the tools supplied by > Xilinx (ngd2 edif) but when translating the final design, I get tons of > warnings (like ".... INIT is not allows on x_LUT3...") and errors, > complaining about x_BRAM4_S1_s1 . . .is not supported". > Any advice will be very appreciated. > > -- > MfG > FalkArticle: 44461
Relax, Hater, if you are as qualified as this guy is you will get the job..... jakab Spam Hater <spam_hater_7@email.com> wrote in message news:3d101eab.4925791@64.164.98.7... > > Notice to potential employers: > > You will be displacing a US citizen who is qualified, and willing to > work for that salary. > > Make sure that you put a statement to that effect on the H1-B transfer > application. > > Nothing personal Farhad. I have a family to feed. > > > > On 17 Jun 2002 21:18:46 -0700, farhad@everdream.com (Farhad Abdolian) > wrote: > > >Hi, > >I am currntly on H1-B visa, and since my current employer has decided > >to close our office, I am looking for a new job, and a company to take > >over my H1-B visa while my green card application goes through (my > >wife is American). > > >Article: 44462
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:3D121892.3202FED7@mail.com... > Tell us what your synthesizer is. Iam using ISE 4.2 with XST. -- MfG FalkArticle: 44463
All ATA signals have at least 44 ohms of series termination between driver and load, with the majority of the signals having 66 ohms or more. Furthermore, the ATA spec says the output drivers should be 4 ma. Since the 5v tolerant issue is really a current issue, 5v --> 3.3v thru 100 ohm ==> Xilinx has a problem when the current exceeds 17 ma, which a 4 ma driver should not be able to do. Dan "Bevan Weiss" <kaizen__@hotmail.NOSPAMcom> wrote in message news:1024560390.776655@aknx2.orcon.net.nz... > None of the ATA specs that I can find (ATA6 or ATA4) even specify the > maximum input or output voltage except to say that the minimum is still TTL > levels (2.4V out high and 0.5V out low, 2.0V in high and 0.8V in low. > > "Ray Andraka" <ray@andraka.com> wrote in message > news:3D1074DE.32670CFE@andraka.com... > > I am pretty sure the ATA-5 still uses 5v, although it may limit the signal > excursions > > to 3.3v. The cable requirements are for the higher modes (don't remember > which one it > > starts on). Basically, there is a length restriction and it requires > every other > > conductor to be a ground. If you are using strictly a UDMA100 drive, you > can design > > to that interface, but if you need backwards compatibility you need to be > able to > > accept 5v signalling. > > > > I think getting an IBIS model for the interface is the stuff of fairy > tales. There > > are too many variations between manufacturers and installations, although > if it is a > > strictly UDMA100 installation it will be a lot more consistent. > > <snip>Article: 44464
"Ray Andraka" <ray@andraka.com> wrote in message news:3D120F32.7321A03@andraka.com... > SpartanII and Virtex have 5v tolerant 3.3v I/O. So does SpartanXL > > Austin Franklin wrote: > > > "Austin Lesea" <austin.lesea@xilinx.com> wrote in message > > news:3D0F9FCF.2AE2A8B3@xilinx.com... > > > > > Also, Virtex is 5V tolerant without any resistor at all (ie 5V PCI > > interface IO > > > standard). It is only in Virtex E and later parts where the resistor is > > going to > > > be (possibly) required. > > > > Hi Austin, > > > > I believe he said he wanted to use a Spartan II. Does the same still apply? > > > > Regards, > > > > Austin > > > > P.S. The 3.3V EDO DRAMs seem to work fine with the 5V Spartan part...I have > > 18 boards that has been used quite heavily, two for a few weeks now, 24 > > hours a day, and we've seen not a wit of a problem. Thanks again for your > > support there! > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759 > >Article: 44465
Thanks Ray Thats an option which I will look into details. pipelining force to anticipate ahead the needed shift ( the module is an huffman coder ) this means which the shifter must move the datas as it will be necessary once reaching the targets registers ... multiplier seems very attrative but it is a shifter only , barrel shifter function will requires additionnal logic at the end logic seems the best way and I will carrefully look at your solution, again thanks for your attention have a nice day -- Use our news server 'news.foorum.com' from anywhere. More details at: http://nnrpinfo.go.foorum.com/Article: 44466
"Kevin Brace" <ihatespam99kevinbraceusenet@ihatespam99hotmail.com> schrieb im Newsbeitrag news:aetdst$qgr$1@newsreader.mailgate.org... > Falk, > > I will assume that you have three modules, two modules that won't have > any I/O pads and one top module with I/O pads that instantiates those > two I/O padless modules. [ Explaination snipped ] This is exactly what I tried, but it wont work, since the two modules contain also instanciated stuff (edn netlists). So XST treats them as black boxes and pushes the work to include the edn files to the design down to the translate level. So my idea was to create a edn netlist AFTER mapping. Is this possible? -- MfG FalkArticle: 44467
Falk Brunner wrote:
>
>
> This is exactly what I tried, but it wont work, since the two modules
> contain also instanciated stuff (edn netlists). So XST treats them as black
> boxes and pushes the work to include the edn files to the design down to the
> translate level.
Falk, are you saying that you got more modules than the two modules in
question, and at least one of those modules also instantiate another
blackbox?
Does your design hierarchy look something like this?
Module A
/ \
Module B(BB) Module C(BB)
|
Module D(BB)
I have never tried this, but if you want Module B to retreat
Module D as a blackbox, you will have to declare another blackbox in
Module B when it is synthesized.
During NGDBUILD, you will also have to point to Module D's netlist
because when Module B is read by NGDBUILD, it will demand a netlist for
Module D.
> So my idea was to create a edn netlist AFTER mapping. Is
> this possible?
>
> --
> MfG
> Falk
Not sure.
It is probably better or maybe the only way to resolve the issue at
NGDBUILD level.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 44468Dan Kuechle wrote: > All ATA signals have at least 44 ohms of series termination between driver > and load, with the majority of the signals having 66 ohms or more. > Furthermore, > the ATA spec says the output drivers should be 4 ma. Since the 5v tolerant > issue > is really a current issue, 5v --> 3.3v thru 100 ohm ==> Xilinx has a problem > when > the current exceeds 17 ma, which a 4 ma driver should not be able to do. > > Dan > > Dan, You forgot that the "tolerance" issue with Virtex-E is current through the clamp diode so for an 0.7V diode drop 100R => problem when current exceeds 10mA (Austing Lesea will correct me if I'm wrong here, say if the diode is a Schottky with drop less than 0.7). Also: Is the 4mA ATA spec. a minimum ? The problem being that some el-cheapo IDE drive might play all sorts of fast and loose games with the ATA spec so at least a QuickSwitch type part might be a safety investment. I've always had a basic rule that no external connector is wired direct into an expensive and hard to replace FPGA ... had too many boards returned where someone thought a 9-pin D-Type was where the mains plugged in :-).Article: 44469
Rick, Absolutely correct. If this is a long cable to/from hell, then a "sacrificial part" is a good investment. Austin Rick Filipkiewicz wrote: > Dan Kuechle wrote: > > > All ATA signals have at least 44 ohms of series termination between driver > > and load, with the majority of the signals having 66 ohms or more. > > Furthermore, > > the ATA spec says the output drivers should be 4 ma. Since the 5v tolerant > > issue > > is really a current issue, 5v --> 3.3v thru 100 ohm ==> Xilinx has a problem > > when > > the current exceeds 17 ma, which a 4 ma driver should not be able to do. > > > > Dan > > > > > > Dan, > > You forgot that the "tolerance" issue with Virtex-E is current through the clamp > diode so for an 0.7V diode drop 100R => problem when current exceeds 10mA > (Austing Lesea will correct me if I'm wrong here, say if the diode is a Schottky > with drop less than 0.7). > > Also: Is the 4mA ATA spec. a minimum ? The problem being that some el-cheapo IDE > drive might play all sorts of fast and loose games with the ATA spec so at least > a QuickSwitch type part might be a safety investment. I've always had a basic > rule that no external connector is wired direct into an expensive and hard to > replace FPGA ... had too many boards returned where someone thought a 9-pin > D-Type was where the mains plugged in :-).Article: 44470
Rick Filipkiewicz wrote: > > Also: Is the 4mA ATA spec. a minimum ? The problem being that some el-cheapo IDE > drive might play all sorts of fast and loose games with the ATA spec so at least > a QuickSwitch type part might be a safety investment. I've always had a basic > rule that no external connector is wired direct into an expensive and hard to > replace FPGA ... had too many boards returned where someone thought a 9-pin > D-Type was where the mains plugged in :-). Which Quickswitches do you you for that ? cheersArticle: 44471
Right, but that is not recommended for new designs at this point.
Theron Hicks wrote:
> "Ray Andraka" <ray@andraka.com> wrote in message
> news:3D120F32.7321A03@andraka.com...
> > SpartanII and Virtex have 5v tolerant 3.3v I/O.
> So does SpartanXL
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44472
The hierarchy introduced some significant delays which can be a problem
for data path designs. There is still some hierarchy, but not like there
was. I think it is a good thing. Data path designs, which is what big
devices are probably going to used for, need a strong local interconnect
and not as much strength in the cross chip connect. I like what I see in
the Stratix so far, although I have not yet had the opportunity to design
with it.
digari wrote:
> Hello all,
> I was just going through altera FPGA architectures. One of the
> observations is that the arch of FLEX was row based, arch of APEX and
> APEX-II was row based and had one level of hierarchy, which is known
> as megalab and Mercury & Stratix again doesn't have any level of
> hierarchy.
> What do u feel about these changes, specially in the terms of
> hierarchy? does it mean that hierarichal architecures doesn't provide
> and benifit for bigger devices.
>
> -Digari
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 44473
Normally you would not want to do that. One port of the block RAM is similar to the old discrete
RAMs that had separated data (input separate from output pins). The reason you have the
bidirectional busses on modern memory chips is to maximize the pin usage. Inside the FPGA, you
should keep the read and write data paths separate, so in most cases you should NOT be using
tristates.
rickman wrote:
> Block ram is not intended to be the same as a RAM chip. There is no tri
> state buffer on the output. If you want to connect it to a bus, you
> need to add the tri state buffer or use a mux.
>
> Do you know how to do that in an HDL?
>
> Nagaraj wrote:
> >
> > Its good that I learnt some more features of BlockRAM (I am new to
> > this). Thanx Peter.
> > Still I have some questions. Suppose the data output of one of the
> > dual ports
> > which I am using as read port is directly connected to the data bus of
> > the system. Then, FPGA should put data onto the databus only when the
> > system master selects the FPGA device AND gives the read clock. But as
> > I see in the dual port BlockRAM module, whenever there is a clock,
> > data is read and put onto the port unconditionally (may create clashes
> > on system databus). Eventhough controlling the "read address latching"
> > is possible, controlling the "read operation" is not possible.
> > Is the above argument correct? If so, Could you please tell me what
> > to do in such cases (reading conditionally)?
> >
> > Peter Alfke <palfke@earthlink.net> wrote in message news:<3D0F5456.26153CA8@earthlink.net>...
> > > This is a fundamental misunderstanding.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
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Article: 44474Oops, I meant to say: After MAP. > functional simulation capabilities. After synthesis, one uses the Newman
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