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In article <ad8apd$njk$1@paris.btinternet.com>, Leon Heller <leon_heller@hotmail.com> wrote: >> Also whether there is any difference in function/ quality ( in terms >> of perfomance or features or testability ) between engineering samples >> and production samples. > >They should be identical, unless they are pre-production units. I've been >caught out by this, before now. Then again, they may not. We have a bunch of ES VirtexE 2000s (to do a student board), 4 of the 8 DLLs don't work on em. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 43751
My 2 Euro worth : ES chips cost Lots more and often don't work properly. <end Xilinx V2 rant> "Leon Heller" <leon_heller@hotmail.com> wrote in message news:ad8apd$njk$1@paris.btinternet.com... > > "Rajat Karol" <rajatkarol@softhome.net> wrote in message > news:a78f7c6d.0205292217.78041f01@posting.google.com... > > Hi, > > > > I wanted to know whether Xilinx or Altera provides engineering samples > > for free? > > I got a sample CPLD (one of the little ones) from Altera. I don't think I > requested it. I haven't got round to trying it yet, though. I might make a > PCB for it at home. I don't think Xilinx or Altera give away samples of > their larger chips on a routine basis, although I have got Altera samples > from my Altera distributor in the past. > > > > > > Also whether there is any difference in function/ quality ( in terms > > of perfomance or features or testability ) between engineering samples > > and production samples. > > They should be identical, unless they are pre-production units. I've been > caught out by this, before now. > > > > > Also are engineering samples available at a lesser rate ?? > > Not generally. They often cost more, because of the small quantities. > > Generally, if you want free samples you are best off approaching your > distributor and seeing if they can help, or a manufacturer's FAE, if you > know one. > > Leon > -- > Leon Heller, G1HSM leon_heller@hotmail.com > http://www.geocities.com/leon_heller > Low-cost Altera Flex design kit: http://www.leonheller.com > > > > > > > >Article: 43752
You really need to register input signals if you don't know what clock they came from, and even then you are into metastability probs. Do a search on this group as this has been covered before. I have done a few VME designs in the past, if you are really stuck mail me and I'll elaborate. Mike p.s. never underestimate the problems async reset can cause in a sync system! "Jerre" <duvister@hotmail.com> wrote in message news:d4b00a9.0205220640.2961a36@posting.google.com... > Hello to everybody, > > I'm working on a design containing a xilinx 4000 series FPGA (Very > old, I know).However recently we had some problems, especially on > reset. It sometimes get's into an unwanted state after a reset or > power on. Put the same code in a spartan and the problem dissapears. > > The FPGA is used as a VME controller (slave device on bus)and it takes > directly the signals from the bus (like SYSRES, DTACK, data strobes, > ...), without registering or making them synchronous. Would that be a > part of my problem? I'm pretty new into this business and have heard > several stories of first double registering your signals before acting > on them. However, I never heard the whole story. > > Maybe it's also because the edge of the signals is not perfectly > straight? Somebody else told me to use a double flip flop but when > and how? > > Anyone out there who could clarify some things? > > Thx, > > JerreArticle: 43753
Agree totally. Never needed a clear yet. "Muzaffer Kal" <kal@dspia.com> wrote in message news:6un4fugkq4rmakrm582icpkm0ddl9f86b9@4ax.com... > On 27 May 2002 06:05:42 -0700, muthu_nano@yahoo.co.in (Muthu) wrote: > > >Hi, > > > >In virtex-II block RAMs, reset signal is there. that will reset the > >output bus value to all "zeros" after giving reset. But it is > >understood that, it will not affect the Memory cell contents. > > > >In most of the situations, during running time we need to clear the > >memory contents. But there is no provision, in BRAM to clear the > >memory contents of the BRAM. So, we have to waste the more memory > >write cycles, to make the memory cell contents to zeros. > > > >My question is: Why there is no clear bit in BRAM? Is that possible or > >not? > > Virtex-II block rams are regular SRAM blocks which have a very high > density. Putting a reset pin into each cell would significantly cut > down on the density so it is undesirable. > If you do a careful design, you don't need to clear memories. Try to > communicate between the state machines which write to and read from > the brams so that no location is read from before it was written. If > your state machines are reset and synchronized, you should almost > never need cleared memory. > > Muzaffer Kal > > http://www.dspia.com > ASIC/FPGA design/verification consulting specializing in DSP algorithm implementationsArticle: 43754
What you have created is a 2-bit Johnson counter. That is, N register bits, with Bit(0) <= not Bit(N-1); If you try the exercise with more than 2 bits you will find a Johnson counter has 2N states, not 2^N. Of course, when N=2, these are identical. It also (for longer registers) has many illegal states: actually every state other than those with a single contiguous block of '1's, and the rest '0', is illegal. jetmarc@hotmail.com (jetmarc) wrote: :Hi. : :I'm working on an address generator for a DMA controller in FPGA. :To save logic resources, I want to use non-sequential addresses. :Instead, I want to use an LFSR. : :The range is 512 byte, or 2^9. The great program "LFSR Testbench" :calculates a variety of possible solutons for this problem. However, :the silicon-efficient solutions have a cycle of (2^n)-1. I need :the whole 2^n to move all 512 bytes. : :Since I am new to LFSRs, I checked the theory with pencil and :paper with a 2-bit LFSR. "LFSR Testbench" suggests: : : feedback := LFSR(1) xor not(LFSR(0)); : LFSR(0) <= feedback; : LFSR(1) <= LFSR(0) xor feedback; : :My pencil & paper work suggests: : : bit1 <= bit0; : bit0 <= not(bit1); : :to count through 00,01,11,10. The latter solution uses less :logic gates, and more important: less WIDE logic inputs. : :With 9 bits, LFSR Testbench suggests a solution with 8 inputs :in one logic equation. This kills FPGA logic area. : :Is it possible to come up with a similar solution for 2^9 like :I did for 2^2? I ask because I don't want to spend 2 days :trying, when it's known to be impossible. : :MarcArticle: 43755
John_H <johnhandwork@mail.com> wrote in message news:<3CF7A8EB.9A9D52F8@mail.com>... > To implement a 9-bit LFSR for the DMA address generator, you need 9 > register bits. To implement a 9-bit counter you need 9 register bits. > No difference in logic resources from the flop standpoint. Since you > need all 9 bits in parallel you can't use a Xilinx SRL16 primitive to > help save resources. > > So... What device architecture are you working with such that the > counter takes up more resources? Atmel AT40K. The design is very complex and won't fit if I don't save where possible. > Efficiency is great but at what cost? Fit versus no fit? Well, maybe XILINX is better at FPGA, but Atmel has chips that combine FPGA with their nice microcontroller in one chip.Article: 43756
Austin Lesea wrote: > > Steve, > > Sorry you feel this way. > > But as you well point out, keeping our hard earned IP confidential is only part > of the issue. The other part is the support. > > Right now our support is 'world class'. It doesn't happen by accident. What > you suggest would fragment resources, cause more customer issues. > > We are daily trying to make FPGAs a "pushbutton" experience for the average > user. I hope that pushbutton effort doesn't extend to PAR. Manual floorplanning is the reason i won't go back to pushbutton designs except for random logic type state machines and things. More effort should be put into the floorplanner tools. > My holy grail is to reduce the ever more difficult signal integrity > issues to something that is closer to the experience of the HDL to bitstream > flow, and less something accomplished by "experts" with magic wands. > > There is no such thing as 'unsupported' documentation. Even these emails have > led to support issues. > > If this philosophy (in part) helps create a market for Xilinx experts, who make > a living from consulting in the (more) optimal use of the FPGAs, I would hardly > lobby to have Xilinx put them out of business.....Article: 43757
And they are expecting ALL this experience from someone who has ONLY THREE YEARS of job experience? And, as a sign of our times, they consider someone who's been "on the job" for 1.5 years not a job hopper... Sigh. Most of my contracts last longer than that. Austin "Chris Lewis" <Chris@n2tech.com> wrote in message news:3cf555e4.22781447@news.qwest.net... > Director of FPGA Design > > Must have an advanced degree from a top EE University!!! > > Looking for a great paycheck and incredible equity at your next job? > Look no further... > > We are a stealthy Biotech start-up, looking for a strong, hands-on > FPGA/ASIC Manager/Director who can build a world class team of Chip > Developers from scratch. > > Ideally, we need you to be a digital systems designer, experienced > with computer architecture, numerical applications, and simulations. > Your designs will help run the worlds most advanced computational > chemistry simulations in the world. Responsible for technology > mapping and FPGA design flows, you will lead cross-functional > development efforts involving software development, design > engineering, applications and technology development. > > You must have stellar academic credentials (i.e. MS/PhD from Stanford, > MIT, Berkley...) and 3+ years full-time work experience POST academia. > > As well as substantial architecture and software development > experience and knowledge of device architecture of most leading FPGA > series, you will ideally have: > · Experience in leading architecture and software teams > · Understanding of the software complexity and ability to co-design > software and hardware. > · Experience in using all leading FPGA tools, synthesis and simulation > tools > · Experience in developing mapping, place and route algorithms, with > the ability to understand the implementation issues of leading > algorithms > · Experience with the Xilinx Virtex line of FPGA's > > We are willing to relocate our perfect candidate!!!!!! > > > If you are interested in this position, please submit your resume > as an attachment in Word format and we will give you a call > once we have a chance to review it. > > For more information about N2 Technologies, please visit our web site: http://www.n2tech.com > > Restrictions: > Due to time constraints, full-time candidates with IMMEDIATE > (1-2 weeks) ability to start only. > No contractors or job-hoppers (1.5 years or more at each position) please. > Local candidates given preference. > > Chris Lewis > Technical Recruiter > N2 Technologies > Tel 650-493-1500 > Fax 650-493-1520 > chris@n2tech.com > http://www.n2tech.com > > Check out my Current Jobs on NTERVIEW > http://www.nterview.com > > If you know someone who would be interested in this > position, and refer that person to us, we will pay > you $2000 if we place your referral candidate and > they stay at the position through the guarantee period > (usually 30-90 days). > > How's it work? Just reply to the position with your > referral's contact info and your contact info including > name, mailing address, phone number and email and we > link your info to the referral in the database. We > will contact you when we place the candidate and a check > for $2000 will soon follow. > That's all it takes!!!Article: 43758
It looks like the AT40K architecture would efficiently use 9 cells to produce a 9 bit counter. There isn't a Xilinx equivalent "direct in" that I can see in the cell structure so a minimum of one LUT would be used for each register in an LFSR. If you use one LUT for a single signal pass through, the other can only give you two input functions with the leftover resources. Are you thinking of implementing an LFSR in a different fashion? Each cell can provide a counter bit and the carry to the next stage so "really wide" functions aren't needed. Are you up against the wall for speed as well and this is why the tradeoff? you might be able to speed things up a tiny bit by using a slight look ahead carry scheme (only 2 bit chunks). I can't figure a nice LFSR approach or alternative counting scheme to help free up some resources. If you have leftover RAM elements, there might be a creative way of manipulating those to get your results. It looks like the IO elements are driven directly by the cells so you cant run a dedicated address counter through alternative resources there. I hope you get all the functionality you need into your part! Good luck. jetmarc wrote: > > John_H <johnhandwork@mail.com> wrote in message news:<3CF7A8EB.9A9D52F8@mail.com>... > > To implement a 9-bit LFSR for the DMA address generator, you need 9 > > register bits. To implement a 9-bit counter you need 9 register bits. > > No difference in logic resources from the flop standpoint. Since you > > need all 9 bits in parallel you can't use a Xilinx SRL16 primitive to > > help save resources. > > > > So... What device architecture are you working with such that the > > counter takes up more resources? > > Atmel AT40K. The design is very complex and won't fit if I don't > save where possible. > > > Efficiency is great but at what cost? > > Fit versus no fit? > > Well, maybe XILINX is better at FPGA, but Atmel has chips that combine > FPGA with their nice microcontroller in one chip.Article: 43759
Hi everyone, I need to communicate between two Celoxica RC100 boards by writing code in Handel-C.Can anyone advise me on how to get started? I know I need the output information of the first board to be input to the second board but how should I implement in code? in terms of bus? Any advice will be greatly appreciated. Thanks and Regards, lktanArticle: 43760
jetmarc wrote: > Hi. > > I'm working on an address generator for a DMA controller in FPGA. > To save logic resources, I want to use non-sequential addresses. > Instead, I want to use an LFSR. > If DMA cycle timing and the AT40K permit could you consider an old fashioned ripple counter? It would only use 9 FFs, trading logic for routing resources.Article: 43761
WTB: Insight SpartanXL Demo board Must be XL. The SpartanII demo board is readily available from their web site. Other demo boards use a very small Spartan. TIAArticle: 43762
I want to try to interface a digital CMOS camera with a computer. Anyone thinks this is possible by using an FPGA chip from the Max 7000 Series? For example. The CMOS camera will be connected to the FPGA then into the microcontroller or computer? I don't know where to start! I would appreciate your responses. Thank you.Article: 43763
Hello all, I use the Chipscope for 3 days now, seems like a good tool as you told me. I used some ILAs @ 75Mhz and everything was fine. Now I am trying to use some ILAs @ 155MHz (thats exactly the xilinx's upper limit) but I get timing errors during PAR. I reduced the number of the timing errors by manual floorplanning (that was tough!) and I add one more pipeline stage. I also noticed that by using triggers as small as possible you get better results (all triggers are of basic type). With the above I succeeded to reach 144MHz but I need some more speed. Has anybody another suggestions? Best Regards, Harris p.s: ILAs' failing paths have 5 levels of logic (the max in my whole design), is there any way that can lead me in logic level reduction?Article: 43764
ae <> wrote: > The default number of failed constraints reported by the timing software is three paths. However, there are many more paths that are failing. I have incrementally bumped up the number of failing paths to be reported each time notcing a longer time to return results. Eventually, the number of paths I request appears to lock the system. Have you tried TRCE instead of timing analyzer? It seems to be faster to do what is more or less the same job. Hamish -- Hamish Moffatt VK3SB <hamish@debian.org> <hamish@cloud.net.au>Article: 43765
On Fri, 31 May 2002 18:28:59 +0200, "Falk Brunner" <Falk.Brunner@gmx.de> wrote: >"Allan Herriman" <allan_herriman.hates.spam@agilent.com> schrieb im >Newsbeitrag news:3cf6e314.346890862@netnews.agilent.com... > >> I still find synthesiser bugs even in purely synchronous designs. I >> don't think gate level sims are going to go away any time soon. > >Yes, there are still synthesizer bug. But would you hunt down such a bug >with a timing simulation of a full FPGA? >I woudnt. I wouldn't do a timing simulation if I was hunting for a functional bug. Full FPGA: definitely. Some bugs don't show up when the modules are simulated one at a time. >Ray Andraka proposed to do post-mapping simulation to veryfy the sythesis >result, since a post-maping is (much?) faster than post P&R. Why is it faster? The simprim blocks take most of the simulation time, and these will be the same post map and post PAR. (Note that you *don't* have to load the SDF if you are doing a post PAR functional simulation.) Allan.Article: 43766
In article <3cf8fc35.13519329@netnews.agilent.com>, Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote: >>Ray Andraka proposed to do post-mapping simulation to veryfy the sythesis >>result, since a post-maping is (much?) faster than post P&R. > >Why is it faster? The simprim blocks take most of the simulation >time, and these will be the same post map and post PAR. >(Note that you *don't* have to load the SDF if you are doing a post >PAR functional simulation.) I think because you end up ignoring all the timing info (which ends up being pretty substantial post-routing. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 43767
I hadn't found this anywhere (forgive the redundancy if someone else already did), so I put together a port of the NIOS GNU Pro environment for Linux. There are three files available: http://www.cryptoapps.com/~chris/NIOS/nios-linux-src.tar.bz2 This is the source for the GNU Pro tool chain and SDK. I some simple instructions (README.FIRST) on compiling and installing the tool chain and SDK. For those that would rather have binaries: http://www.cryptoapps.com/~chris/NIOS/nios-linux-bin.tar.bz2 This will extract to /usr/local/cross/nios To use, add /usr/local/cross/nios/bin to your PATH and set NIOSGNU to /usr/local/cross/nios A compiled up version of the SDK can be found at: http://www.cryptoapps.com/~chris/NIOS/nios-linux-sdk.tar.bz2 I'll be adding more source sometime in the (hopefully near) future. --ChrisArticle: 43768
Hi. I'm prototyping a new design with AT40K FPGA and CompactFlash memory card. The CompactFlash is being talked to in the "common memory mode", meaning that the data is not addressed with ADDRx lines but read by consecutive read cycles to one single address. The CompactFlash card has an internal address pointer that increments after each read cycle. My circuit doesn't work. After reading 512 bytes I find that some are missing, and the buffer is padded with dummy bytes. Obviously the CompactFlash card has taken a few of the read cycles for two (double-clocked on the falling /OE edge), so that its internal address has reached the end while my FPGA was still reading more data. I spent hours already, trying to remove this problem. But no avail. I tried all software options that the AT40K gives (io pin slew rate, pullup/pulldown). I added external RC filters on the /OE, /CS, /WE pins (making the problem worse). I inserted schmitt trigger '244 bus drivers in the signal path. On the scope, the signals look OK, but it is only a 5ns/200MHz model. The problem only occurs when there is a lot of change on the 8bit data bus. Reading a sector with all 0x00 or all 0xff is possible (without errors). The data signals are far away from the clock signals (/OE, /CS, /WE) both on the (short) cable and the FPGA pinout. The same card (with same cable) has previously worked fine on another prototype. That prototype used 5.0v (while the new one uses 3.3V) and connected the CF card to an ATmega microcontroller (while the new one has an AT40K FPGA). I believe that the AT40K IO pin driver generates noisy signals, at least more noisy than the ATmega. I don't know how to fix that. Schmitt trigger buffers didn't help. Do you have an idea what I can try to fix it? MarcArticle: 43769
Hi folks, I am looking for FPGA board that use USB port or IEEE 1394 (Firewire) for downloading to the chip. My notebook only comes with USB and IEEE1394 port so using FPGA board that only use parallel or serial port won't work! Thanks in advance!Article: 43770
This sounds like a bypass or crosstalk problem
Is the chip properly bypassed with a capacitor directly across its power and
ground pins? Do you have some crosstalk from a signal line to a clock line?
Try a small (couple of picofarads) cap on that clock line to see if the excess
clock signals vanish. Is there a data line very close to the clock line?
Isolate it somehow, maybe by running a grounded trace between the two, or by
physically moving the traces apart.
Also check your ground connection to the chip- if it is not very good, you
may still get the chip to operate, but only marginally. And finally, try a
small ferrite bead on the ground line close to the chip.
Cheers!
Chip Shults
My robotics, space and CGI web page - http://home.cfl.rr.com/aichip
Article: 43771If your talking about interfacing a CMOS imager itself then yes, that would be pretty straight forward for someone already skilled in using programmable logic. Imagers built with this technology (as opposed to CCD) interface easily to digital circuits and generally require no external analog references. "Roger King" <roger@king.com> wrote in message news:<iz4K8.173716$t8_.157445@news01.bloor.is.net.cable.rogers.com>... > I want to try to interface a digital CMOS camera with a computer. Anyone > thinks this is possible by using an FPGA chip from the Max 7000 Series? For > example. The CMOS camera will be connected to the FPGA then into the > microcontroller or computer? I don't know where to start! > > I would appreciate your responses. Thank you.Article: 43772
Hi! Look at the CESYS X2S_USB Board at http://www.cesys.de/ They use a Cypress EZ-USB chip for USB communication. If you need Linux download drivers visit https://sourceforge.net/projects/x2susbsfwkit/ (which is actually not usefull) or contact me for the files. Bye HansiArticle: 43773
"jetmarc" <jetmarc@hotmail.com> schrieb im Newsbeitrag news:af3f5bb5.0206011953.44d7423a@posting.google.com... > Obviously the CompactFlash card has taken a few of > the read cycles for two (double-clocked on the falling > /OE edge), so that its internal address has reached > the end while my FPGA was still reading more data. How do you generate the /OE signal? is this signal directly comming from a FlipFlop or logic gates. If it comes from logic gates (a decoder), then it will most probably have some glitches. As the other guy already mentioned, good bypassing is also vital. -- MfG FalkArticle: 43774
On Sat, 1 Jun 2002 17:18:03 +0000 (UTC), nweaver@CSUA.Berkeley.EDU (Nicholas Weaver) wrote: >In article <3cf8fc35.13519329@netnews.agilent.com>, >Allan Herriman <allan_herriman.hates.spam@agilent.com> wrote: >>>Ray Andraka proposed to do post-mapping simulation to veryfy the sythesis >>>result, since a post-maping is (much?) faster than post P&R. >> >>Why is it faster? The simprim blocks take most of the simulation >>time, and these will be the same post map and post PAR. >>(Note that you *don't* have to load the SDF if you are doing a post >>PAR functional simulation.) > >I think because you end up ignoring all the timing info (which ends up >being pretty substantial post-routing. I thought it was possible to ignore all timing in the post-PAR VHDL. You don't have to load the SDF and (in Modelsim) you can use the +notimingchecks command line option to turn off the VITAL timing. I haven't ever done a post-map sim to know if there's a difference or not. Does anyone have any quantitative results? Allan.
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Compare FPGA features and resources
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Authors:A B C D E F G H I J K L M N O P Q R S T U V W X Y Z