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Hello, I guess you can help me with this one, can we put our own strings into the header of the RBT file in place of Design name, Arch, Part, etc (replace it with something like, Name of project, Clearcase Label, Release Number...)? I know the header is automatically generated by the Xilinx tools but I don't know if is part of the CRC Check during the download process. It could be quite useful for some Software guys here. Thanks for your help. -- Ulises Hernandez Digital Design Engineer ECS Technology Limited ulisesh@ecs-tech.comArticle: 43701
On Thu, 30 May 2002 07:42:18 +0100, "Ulises Hernandez" <ulises@britain.agilent.com> wrote: >Hello, > >I guess you can help me with this one, can we put our own strings into the >header of the RBT file in place of Design name, Arch, Part, etc (replace it >with something like, Name of >project, Clearcase Label, Release Number...)? >I know the header is automatically generated by the Xilinx tools but I don't >know if is part of the CRC Check during the download process. >It could be quite useful for some Software guys here. > >Thanks for your help. Yes. The CRC is calculated on the data that loads into the FPGA. Typically you would have written your own program that has as input the .RBT file, and skips the text header section, and gets to the bitstream part for actual down loading. Providing it can deal with your modified header, there should be no problem. Adding lines should also not cause problems, assuming the following sw is looking for the line that starts with "11111111" You should be able to change the lines marked with "<<<<<<" Xilinx ASCII Bitstream <<<<<< Created by Bitstream E.35 <<<<<< Design name: zzz.ncd <<<<<< Architecture: xc4000e <<<<<< Part: 4013epq208 <<<<<< but bad idea Date: Thu May 16 23:14:07 2002 <<<<<< but bad idea Bits: 247968 <<<<<< but bad idea 1111111100100000001111001000100110011111 01010111111111101 etc 1110101111111011111111011 Philip Freidin Philip Freidin FliptronicsArticle: 43702
In article <5e72ca82.0205291247.3d897b63@posting.google.com>, Jeff Mock wrote: > Modelsim is a toy, especially when it comes to doing gate > level simulation of any reasonable size. I have used Modelsim for simulations with millions of ASIC gates. Modelsim is far from a toy, it is one of the big simulators on the market. What do you consider reasonable size simulation? On the other hand you have to know what you are doing when simulating big datasets. Cell libraries should be compiled with certain optimizations (check -fast option in modelsim). Also usage of VHDL/Vital is dumb, verilog netlists are much faster to simulate and more memory efficient. Also on HPUX platform there are some tricks that must be done with memory locking etc. Also Xilinx libraries are not very good compared to many ASIC libraries. Especially the memory models are quite slow. --KimArticle: 43703
Marc,
See below,
Austin
Marc Randolph wrote:
> eyals@hywire.com (Eyal Shachrai) wrote in message news:<70029bf5.0205290917.1320d152@posting.google.com>...
> > 1. is there apossibility to use the same DCM to synthisize two divided clocks?
>
> It depends on what divided values you need. You can use the CLKFX to
> produce M/D ratio of the input clock.
>
> In addition, can also use the CLKDV output to produce one divided
> version of the clock.
>
> > 2. will it be wise to divide a 125 MHz clock in 16 ?
>
> Only if you need 7.8126 MHz. ;-)
>
> Seriously, it should be no problem for the DCM to handle this, and in
> fact, you can divide by up to 32 by enabling the predivider on the
> DCM.
>
> Which raises a question... is there any benefit to using the CLKDV
> output to do a divide by 16 over using the CLKFX output with M=1 and
> D=16? Lower jitter perhaps?
Yes, generally CLKDV will have < 1/2 the jitter of the CLKFX, worst case to worst case. As well, the output
frequency of the CLKFX is 24 MHz, minimum, so the CLKIN exceeds the maximum CLKIN for the DCM (16 X 24 = 384),
so it won't solve the problem, either.
>
>
> What if you needed a divide by 64. Is it better to use two DCM's, one
> each with /8, or one with D=64? Ignore the increased current/power
> consumption due to the 2nd DCM.
M, D = {1,32}, so D = 64 is not recommended.
>
>
> Have fun,
>
> Marc
Article: 43704John_H wrote: > As an example, a 100 MHz phase accumulator generating 10.0001 MHz will > produce one cycle every 10 master clocks for much of the output pulse > train. When the value below the MSbit finally accumulates enough to push > the MSB over one cycle - a single instance of 9 master clocks rather than > 10 - the effect is a full 10 ns shift in the "average" phase position. > This event occurs at about 100 Hz with a 10 ns peak jitter value. <snip> Austin replied: >That is what I thought it would do, too. But it never did. The space >bewteen sideband frequencies is independent of the constant, and depends >only on the number of bits of resolution (size of the adder/register). >The magnitude of the sidebands is more difficult to predict. <snip> The effect John mentioned is present both in single bit and multi-bit sine output DDS's, and can be seen clearly on a phase noise analysis system with a good close in noise floor ( e.g. HP 3048A ). As Luis mentioned, using the DDS as a reference to a loop with a high multiplication factor will also bring them up to a level that can be observed directly with a spectrum analyzer. The best reference I've seen for this sort of stuff is "Direct Digital Frequency Synthesizers", V. F. Kroupa, 1999, IEEE Press, which has reprints of most of the significant DDS related papers, along with some additional introductory material for each chapter. This book reprints some of the (very few) published mentions of this effect that I've seen, which can be found on pages 213 and 217. The first page has phase noise plots at 1/16 clk and (1/16 + 1/2^24) clk, which show the resulting forest of close in spurs for the latter tune word; the second page shows a wider view at (2^29 - 1) / 2^32 clk, where the normal 1/f^n device phase noise floor is completely masked by a continuum of close in spurs. > >I have no answers, just what the spectrum analyzer and wander analysis shows. > The level of these close in spurs is so low that they are obscured by the spectrum analyzer's LO phase noise; also, most telecom clock sources with which I am familiar (OC-48,192) also have fairly lousy close in noise sidebands that would also mask the effect. ( e.g., if the DDS L(f) at 100 Hz offset were to jump from -125 dBc/Hz to -110 dBc/Hz near a 'bad' tune word, would you notice ?) BrianArticle: 43705
Brian, Good news. So basically it is so low close in as to not matter, unless you were unfortunate enough to be trying to make this a reference for a 24 HGz radio system using 1024 QAM (or any other system where the frequency gets multiplied, and the close in phase noise is important). I played around with a MathCad simulation yesterday, and I see the same thing happening as the number of bits of the accumulator gets large, and the constant is an odd number (even numbers reduce the spectral content, so you must simulate an odd number). I don't see some odd numbers being worse than any others, but you can see even numbers throwing more power into fewer spurs (but further away from the fo by factors of two spacing). Peter and I also perused the PhD thesis in German yesterday (my head still hurts). It did not offer any insights into the phase spectrum, only the total jitter noise power. Seems this fellow is Dr. Synthesis in Germany. His website is also interesting, but very narrow in content. Still no closed form math to see the spectrum, but I am happy now with the MathCad simulation, which seems to agree with what I measure, and what you havve seen, Austin Brian Davis wrote: > John_H wrote: > > As an example, a 100 MHz phase accumulator generating 10.0001 MHz will > > produce one cycle every 10 master clocks for much of the output pulse > > train. When the value below the MSbit finally accumulates enough to push > > the MSB over one cycle - a single instance of 9 master clocks rather than > > 10 - the effect is a full 10 ns shift in the "average" phase position. > > This event occurs at about 100 Hz with a 10 ns peak jitter value. > <snip> > > Austin replied: > > >That is what I thought it would do, too. But it never did. The space > >bewteen sideband frequencies is independent of the constant, and depends > >only on the number of bits of resolution (size of the adder/register). > >The magnitude of the sidebands is more difficult to predict. > <snip> > > The effect John mentioned is present both in single bit and multi-bit > sine output DDS's, and can be seen clearly on a phase noise analysis > system with a good close in noise floor ( e.g. HP 3048A ). > > As Luis mentioned, using the DDS as a reference to a loop with a high > multiplication factor will also bring them up to a level that can be > observed directly with a spectrum analyzer. > > The best reference I've seen for this sort of stuff is "Direct Digital > Frequency Synthesizers", V. F. Kroupa, 1999, IEEE Press, which has reprints > of most of the significant DDS related papers, along with some additional > introductory material for each chapter. > > This book reprints some of the (very few) published mentions of this > effect that I've seen, which can be found on pages 213 and 217. The first > page has phase noise plots at 1/16 clk and (1/16 + 1/2^24) clk, which > show the resulting forest of close in spurs for the latter tune word; the > second page shows a wider view at (2^29 - 1) / 2^32 clk, where the normal > 1/f^n device phase noise floor is completely masked by a continuum of close > in spurs. > > > > >I have no answers, just what the spectrum analyzer and wander analysis shows. > > > > The level of these close in spurs is so low that they are obscured by the > spectrum analyzer's LO phase noise; also, most telecom clock sources with > which I am familiar (OC-48,192) also have fairly lousy close in noise > sidebands that would also mask the effect. ( e.g., if the DDS L(f) at 100 Hz > offset were to jump from -125 dBc/Hz to -110 dBc/Hz near a 'bad' tune word, > would you notice ?) > > BrianArticle: 43706
I didn't finish the more detailed elaboration last night - more to come soon. The close-in spurs *will* happen at significant levels in the cases of "close to multiple" accumulator values and many values will provide noticeable phase noise - well above a dirty -60dBc noise floor. One thing may have obscured the observation in practice: did you use a cleanup PLL? The characteristics here can shift some results around. When the phase accumulator MSbit is used for DDFS, the peak-to-peak jitter value (wander included) will be one master clock period (with the exception of the even submultiples of the accumulator modulus). I see this as a given - it's just a question of how well it cleans up. If you had a scope triggered by an independent "clean" frequency at the desired output rate and probed the MSbit, you would see the edge spread across one master clock period. To clean up the signal, a PLL of some form is used. The factor I've forgotten once or twice is that the phase comparator is often done at a frequency 1MHz or lower. The jitter analysis for the DDFS spectrum must be taken at the PLL reference frequency. If you have a 2.01 MHz spur in the DDFS output but divide the output down to get a 1 MHz phase comparator input, the spur aliases down to 10 kHz. This can really mess with the spectrum. A higher master clock will always reduce the peak-to-peak offset that needs to bea cleaned up but the filtering is much more effective when using a high phase comparator frequency where the high frequency spurs don't alias but get filtered out. I'd be intereseted in mimicking your test setup to compare observed values with the "closed end" solution. Even numbers will give you fewer spurs than odd spurs, the question comes down to "How long does it takes the sequence to repeat?" The answer will give you an upper limit on the spurs. Austin Lesea wrote: > Brian, > > Good news. So basically it is so low close in as to not matter, unless you were > unfortunate enough to be trying to make this a reference for a 24 HGz radio system > using 1024 QAM (or any other system where the frequency gets multiplied, and the > close in phase noise is important). > > I played around with a MathCad simulation yesterday, and I see the same thing > happening as the number of bits of the accumulator gets large, and the constant is > an odd number (even numbers reduce the spectral content, so you must simulate an > odd number). I don't see some odd numbers being worse than any others, but you > can see even numbers throwing more power into fewer spurs (but further away from > the fo by factors of two spacing). > > Peter and I also perused the PhD thesis in German yesterday (my head still > hurts). It did not offer any insights into the phase spectrum, only the total > jitter noise power. Seems this fellow is Dr. Synthesis in Germany. His website > is also interesting, but very narrow in content. > > Still no closed form math to see the spectrum, but I am happy now with the MathCad > simulation, which seems to agree with what I measure, and what you havve seen, > > Austin > > Brian Davis wrote: > > > John_H wrote: > > > As an example, a 100 MHz phase accumulator generating 10.0001 MHz will > > > produce one cycle every 10 master clocks for much of the output pulse > > > train. When the value below the MSbit finally accumulates enough to push > > > the MSB over one cycle - a single instance of 9 master clocks rather than > > > 10 - the effect is a full 10 ns shift in the "average" phase position. > > > This event occurs at about 100 Hz with a 10 ns peak jitter value. > > <snip> > > > > Austin replied: > > > > >That is what I thought it would do, too. But it never did. The space > > >bewteen sideband frequencies is independent of the constant, and depends > > >only on the number of bits of resolution (size of the adder/register). > > >The magnitude of the sidebands is more difficult to predict. > > <snip> > > > > The effect John mentioned is present both in single bit and multi-bit > > sine output DDS's, and can be seen clearly on a phase noise analysis > > system with a good close in noise floor ( e.g. HP 3048A ). > > > > As Luis mentioned, using the DDS as a reference to a loop with a high > > multiplication factor will also bring them up to a level that can be > > observed directly with a spectrum analyzer. > > > > The best reference I've seen for this sort of stuff is "Direct Digital > > Frequency Synthesizers", V. F. Kroupa, 1999, IEEE Press, which has reprints > > of most of the significant DDS related papers, along with some additional > > introductory material for each chapter. > > > > This book reprints some of the (very few) published mentions of this > > effect that I've seen, which can be found on pages 213 and 217. The first > > page has phase noise plots at 1/16 clk and (1/16 + 1/2^24) clk, which > > show the resulting forest of close in spurs for the latter tune word; the > > second page shows a wider view at (2^29 - 1) / 2^32 clk, where the normal > > 1/f^n device phase noise floor is completely masked by a continuum of close > > in spurs. > > > > > > > >I have no answers, just what the spectrum analyzer and wander analysis shows. > > > > > > > The level of these close in spurs is so low that they are obscured by the > > spectrum analyzer's LO phase noise; also, most telecom clock sources with > > which I am familiar (OC-48,192) also have fairly lousy close in noise > > sidebands that would also mask the effect. ( e.g., if the DDS L(f) at 100 Hz > > offset were to jump from -125 dBc/Hz to -110 dBc/Hz near a 'bad' tune word, > > would you notice ?) > > > > BrianArticle: 43707
"wuqiang" <wq00001@163.com> schrieb im Newsbeitrag news:32ebf098.0205291650.25752ccf@posting.google.com... > I use mcu 89c51 to PS configure Flex10k10. I have followed the timing > in the altera pdf file, used the content of .ttf(Byte) file as > unsigned char array. Now NStatus signal is ok, but Conf_Done is never > to become hign to inform me to configure success. I check the board > and program again, but no error is found. > Who have finished similar work? Did you generate additional configuration clock cycles after all bits have been loaded into the FPGA(4..6)? There are required to initiate the startup-sequence. -- MfG FalkArticle: 43708
"John_H" <johnhandwork@mail.com> schrieb im Newsbeitrag news:3CF64D20.A761654E@mail.com... [ very good comments about DDS spurs] > I'd be intereseted in mimicking your test setup to compare observed values with the > "closed end" solution. > > > Even numbers will give you fewer spurs than odd spurs, the question comes down to "How > long does it takes the sequence to repeat?" The answer will give you an upper limit > on the spurs. I thinks this is a more or less easyly to aswer question. The sequence repeats when any integer multiple of the increment is also an integer multiple of the phase accumulator max. count+1, so mathematicans would call this smallest common multiple (would they?, I just did a word by word translation from german ;-) Iam afraid this could be lAAAARGe. Imagine a 32 bit accumulator, where the max count is 2^32-1. The highest frequency a DDS can generate (without doing over/undersampling tricks) is 1/2 of its system clock, achieved by using a increment of 1/2 max count. Now decrese this increment by 1, so that after two system clock the phase is 1 count below its previous value. So it takes 2^31 cycles to reach the starting condition again. With a master clock of 100 MHz, this will take somewhere 20 seconds. So there are spurs at 1/20 Hz. Hmm ??? -- MfG FalkArticle: 43709
"Austin Lesea" <austin.lesea@xilinx.com> schrieb im Newsbeitrag news:3CF6422B.CEBF720@xilinx.com... > Brian, > > Peter and I also perused the PhD thesis in German yesterday (my head still > hurts). It did not offer any insights into the phase spectrum, only the total > jitter noise power. Seems this fellow is Dr. Synthesis in Germany. His website ;-))))) -- MfG FalkArticle: 43710
"newman" <newman5382@aol.com> schrieb im Newsbeitrag news:e6038423.0205291054.64aeeb8e@posting.google.com... > nagaraj@accord-soft.com (Nagaraj) wrote in message news:<9c782518.0205290352.417edae5@posting.google.com>... > > Hi all, > > I have a design in vhdl (targeted at xilinx 300k virtex device). > > The post place and route simulation is taking lot of time (several > > days for 1ms worth simulation). I am using ModelSim simulator. > > Any suggestions to reduce the time taken for simulation? I assume you are not using the free version? This is terrible slow on design containing more than 500 lines. ;-) On the other hand side, what do you expect from the p&r simulation? On www.fpgacpu.org there are serval articles about the very limited sense of P&R simulations. They state, that doing a clean synchronous design and using the timing analyzer is a much better approach. No real need for p&R simulations. -- MfG FalkArticle: 43711
There is not a lot of documentation that goes with the bitstream itself that
is why our hardware objects have lots of fields in it. Our HOTMan ($69)
program also has a version control feature that help you track different
design iterations. We then use some standard compression. One of the
problems with using the RBT file is it takes one byte for every bit which
can be quite large. The best compression I've seen is 100x (a V1000 with
one inverter:) but when we used Scott Hauck's, University of Washington, we
compressed bitfile sizes by under 1/2 the original size which means you can
fit two designs where you used to fit one (on average).
Steve Casselman
UofW compression benchmarks
Original = 100%
--------------------
design 35.1%
Mars 51.1%
mem0test 60.2%
Pex 62.9%
rc6 28.7%
Rijndael 60.2%
Serpent 47.3%
u50pc 38.9%
u93pc 56.5%
--------------------
Avg 48.9%
Or a little under 1/2 the size of the original
// F:/Hot/examples/HotJTag/microcon.hot configuration header file
// Created automatically **** DO NOT EDIT ****
#include <Hot.h>
Hot HOTmicrocon;
extern int microconArray[];
void HOTmicroconInit()
{
HOTmicrocon.setConfig ("microcon");
HOTmicrocon.setSource ("F:/Hot/examples/HotJTag/microcon.bit");
HOTmicrocon.setComments ("Micro controller for the VW300");
HOTmicrocon.setAuthor ("Steve Casselman");
HOTmicrocon.setVersion ("0.0.1");
HOTmicrocon.setDateCreated ("Wed Mar 20 14:38:16 2002");
HOTmicrocon.setCreator ("HotMan 1.0");
HOTmicrocon.setSystem ("Virtual");
HOTmicrocon.setBoard ("VW300");
HOTmicrocon.setDBoard ("Virtual");
HOTmicrocon.setPart ("v300bg352");
HOTmicrocon.setAction ("program");
HOTmicrocon.setAck ("Not Sent");
HOTmicrocon.setMessage ("None ");
HOTmicrocon.setSecID ("0000000000000000");
HOTmicrocon.setServer ("localhost");
HOTmicrocon.setUserLib ("HotJtag");
HOTmicrocon.CDataSize = 13011;
HOTmicrocon.UDataSize = 218976;
HOTmicrocon.unit = 1;
HOTmicrocon.port = 555;
HOTmicrocon.dataFormat = 2;
HOTmicrocon.CData = (byte*)microconArray;
}
int microconArray[3253]=\
{
0x9dedda78,0xd51c700f,0xef7fe79d,0x8f4ccf75,0xa49eb234,0x43ff2db1,0x05b63fad
,0x3db1e736,
"Ulises Hernandez" <ulises@britain.agilent.com> wrote in message
news:1022740942.786769@cswreg.cos.agilent.com...
> Hello,
>
> I guess you can help me with this one, can we put our own strings into the
> header of the RBT file in place of Design name, Arch, Part, etc (replace
it
> with something like, Name of
> project, Clearcase Label, Release Number...)?
> I know the header is automatically generated by the Xilinx tools but I
don't
> know if is part of the CRC Check during the download process.
> It could be quite useful for some Software guys here.
>
> Thanks for your help.
>
> --
> Ulises Hernandez
> Digital Design Engineer
> ECS Technology Limited
> ulisesh@ecs-tech.com
>
>
Article: 43712In article <3CEEACDF.88099551@andraka.com>, Ray Andraka <ray@andraka.com> wrote: >I currently do my backups onto a drive on another machine. The hard part is >remembering to do the copy. I don't trust one machine to hold the data >uncorrupted. This is, of course, one of the nice parts of retrospect: You can have a backup server which automatically backs up the clients, onto media of your choice (including disk). A backup onto disk on the server for continual use (automatically at a given time), and occasionally do archive onto tape/CD for offsite backups. I don't know how well it works under Windows, but it works like a dream on the mac. -- Nicholas C. Weaver nweaver@cs.berkeley.eduArticle: 43713
I configured at 10k10 from an 8 bit port using the serial mode and .rbf file, worked fine from diagrams in the app note. wq00001@163.com (wuqiang) wrote in message news:<32ebf098.0205291650.25752ccf@posting.google.com>... > I use mcu 89c51 to PS configure Flex10k10. I have followed the timing > in the altera pdf file, used the content of .ttf(Byte) file as > unsigned char array. Now NStatus signal is ok, but Conf_Done is never > to become hign to inform me to configure success. I check the board > and program again, but no error is found. > Who have finished similar work?Article: 43714
Kim Enkovaara wrote: > In article <5e72ca82.0205291247.3d897b63@posting.google.com>, Jeff Mock wrote: > >>Modelsim is a toy, especially when it comes to doing gate >>level simulation of any reasonable size. > > > I have used Modelsim for simulations with millions of ASIC > gates. Modelsim is far from a toy, it is one of the big simulators on > the market. What do you consider reasonable size simulation? > > On the other hand you have to know what you are doing when simulating > big datasets. Cell libraries should be compiled with certain > optimizations (check -fast option in modelsim). Also usage of > VHDL/Vital is dumb, verilog netlists are much faster to simulate and > more memory efficient. Also on HPUX platform there are some tricks > that must be done with memory locking etc. > > Also Xilinx libraries are not very good compared to many ASIC > libraries. Especially the memory models are quite slow. Yep, and using the Xilinx VHDL/Vital libraries is really slow. For functional simulation, I simply wrote my own VHDL models. This really is surprisingly easy to do. Then by changing the library mapping I can occasionally use the Xilinx libraries, to verify that it produces identical simulation results to my own libraries. -- My real email is akamail.com@dclark (or something like that).Article: 43715
Can someone please send me an orcad schematic for the XCV405E for Orcad version 9.1 or lower. ThanksArticle: 43716
ask them !!! "Rajat Karol" <rajatkarol@softhome.net> wrote in message news:a78f7c6d.0205292217.78041f01@posting.google.com... > Hi, > > I wanted to know whether Xilinx or Altera provides engineering samples > for free? > > Also whether there is any difference in function/ quality ( in terms > of perfomance or features or testability ) between engineering samples > and production samples. > > Also are engineering samples available at a lesser rate ?? > > regards > > RajatArticle: 43717
rajatkarol@softhome.net (Rajat Karol) wrote in message news:<a78f7c6d.0205292217.78041f01@posting.google.com>... > Hi, > > I wanted to know whether Xilinx or Altera provides engineering samples > for free? > Distributors will if they think it will lead to more business.Article: 43718
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<ad5kv8$ue2e2$3@ID-84877.news.dfncis.de>... > "newman" <newman5382@aol.com> schrieb im Newsbeitrag > news:e6038423.0205291054.64aeeb8e@posting.google.com... > > nagaraj@accord-soft.com (Nagaraj) wrote in message > news:<9c782518.0205290352.417edae5@posting.google.com>... > > > Hi all, > > > I have a design in vhdl (targeted at xilinx 300k virtex device). > > > The post place and route simulation is taking lot of time (several > > > days for 1ms worth simulation). I am using ModelSim simulator. > > > Any suggestions to reduce the time taken for simulation? > > I assume you are not using the free version? This is terrible slow on design > containing more than 500 lines. ;-) > On the other hand side, what do you expect from the p&r simulation? > On www.fpgacpu.org there are serval articles about the very limited sense of > P&R simulations. They state, that doing a clean synchronous design and using > the timing analyzer is a much better approach. No real need for p&R > simulations. I can verify this. The free version is supposedly purposefully hamstrung so that you will buy the full version. Funny thing is, they are probably losing business because people don't realize the free version has a governor.Article: 43719
Hi all, I've noticed a few posts about the Atmel FPGAs and the IDS software Atmel offers for free on their website. But from what I can tell, it's not entirely free because it does not include a synthesizer of any kind. I can live without a simulator, and all I need is to synthesize some fairly simple Verilog code. Does anyone know of an inexpensive synthesizer I can use with IDS that meets my relatively simple requirements? Any information would be greatly appreciated. Thanks, Rich LeGrandArticle: 43720
John_H wrote:
>
>The close-in spurs *will* happen at significant levels in the cases
>of "close to multiple" accumulator values and many values will
>provide noticeable phase noise -well above a dirty -60dBc noise floor.
>
I agree that the spur levels can be much higher for MSB-only devices.
Just to clarify my last post, my comments and the references I gave
were directed towards sine output DDS's; namely, I was trying to point
out that the same low rate periodic phase hiccup mechanism you mentioned
for MSB-only devices is also present ( to a lesser extent ) in sine
output devices, where it occurs at the LSB of truncated phase.
( I thought Austin & Luis were discussing sine output devices at
that point in the thread, but I may have misread their posts. )
Some other useful DDS modeling links:
http://www.hit.bme.hu/people/papay/sci/DDS/start.htm
MathCad DDS truncation models, background, paper, DDS links
http://www.geocities.com/CapeCanaveral/5611/dds.html
Matlab DDS model, some background, (old) links
Brian
Article: 43721Fabio G. <9+3@supereva.it> wrote: > Prager Roman <rprager@frequentis.com> ha scritto: >>I use the NIOS core, > I have the Nios developement board, do you? Yes, I do >>One of my biggest problems is that the NIOS core consumes too much space in the >>FPGA > The Apex in the board has 8320 LCs. > How many LCs does the Nios consume? If you add some PIOs (especially with interrupt ability) you soon end up with 2000 LEs. However, if you also want to use internal RAM/ ROM, nearly all of the APEX is used for NIOS. On a recent board I have an APEX 20K400E in the 672pin- BGA- package, but I do not have enough pins left for SRAM and Flash for NIOS. Thats why I decided to use the system flash where the APEX image is stored and use internal flash meory and RAM for Nios. But then it gets very large ( about 7000 LEs). >>However, I think the idea of the SOPC- builder is really great. It is quite >>easy to implement a working system within very short time. > I'm doing the synthetizable version of a RISC processor: > http://xirisc.deis.unibo.it > It is a reconfigurable processor for high performance embedded system: > something similar (but better) to Nios: it has a built in FGPA... so > it's FPGA^2 !! (actual, on Altera I've implemented a smaller version of > the FPGA than the one on the sylicon version). I am not sure what for this is supposed to be useful ? Why do you want to split up the FPGA? > I have to implement my processor in the FPGA but I want that when I shut > down the board, the configuration is not lost. > Do you know how to download the configuration info into the FlashRAM of > the Nios development board? You can use the NIOS to write the new image. There should be a description in the Nios documentation how to write such a routine, or maybe there is already some example included. Roman > Bye! > -- > Per rispondermi via email sostituisci il risultato > dell'operazione (in lettere) dall'indirizzo.Article: 43722
Loi Tran wrote: > > Hi, > > I'm working with WEBpack 4.1 and I was wondering if there is a way to work > with multiple schematics on same level sheets instead of hierarchy sub-level > format. Example, I want 2 separate sheets on the same level to have a common > signal line, and therefore a common net. I tried it and a query tells me > they're two different nets altogether. Please tell me if this can be done? Try using the equivalent of #include if your HDL has it.Article: 43723
The best way to look at the jitter induced by a DDFS output is by analyzing the output of a phase comparator that shows the difference between the DDFS output and the ideal output frequency waveform. The phase error at the phase detector - whether it's the raw value that's filtered in a cleanup PLL or part of a test setup with externally locked frequencies - is where the jitter and wander characteristics would show up. A cleanup PLL won't show a phase error at frequencies well below the loop's cutoff frequency because the VCO tracks the input. A test setup with an external lock (common 10 MHz reference sources, for instance) will show the deviations across the whole range. The jitter can be found to a solid first approximation by analyzing beats. The beat frequencies generated in a DDFS system - looking at the MSbit of a phase accumulator - come from phase offset patterns that repeat themselves as the system runs. The longer the full pattern takes to repeat, the more spurs are generated at lower amplitudes. The strong, short repetitions can be seen easily in the phase error results but the smaller amplitude shifts in these patterns can be identified and they're all related to the beats. The beats come from the progression of the closest fractions that represent the accumulator value. Extra long post. I really need to get a website up for items like this. Apologies to those of you who aren't fascinated by frequency synthesis. Freely ignore the post now or later when your eyes glaze over. Most of the post is observational based on graphically verified correlations between beat frequencies and phase error values. In the example of a 55/128 accumulator value, the closest fraction progression is 1/2, 3/7, and 55/128. The 1/2 denominator gives the most common number of master clock cycles per output cycle with a lesser occurrence of 3 master clocks per output cycle. The 2s and 3s balance out to give a 2.327 average, or 128/55. The average output frequency is the master clock divided by 2.327. The next fraction's denominator provides the next major beat, the repetition between phase adjustments on the first fraction. Since a beat generated by the 1/2 would give a sequence of 2/2/2/2/2, the 3/7 fraction adds an extra phase "nudge" on one of the 2 clock output cycles to generate the 3 clock cycle resulting in a closer approximation of a 2/2/3 repeating cycle, the sum of which is 7 cycles from the denominator. The instantaneous frequency of the beat is 1/7 of the master clock, but the phase values of the sawtooth waveform's "teeth" are nudged as with the original double cycles resulting in an average frequency of 0.141 times the master clock frequency. Where did that number come from? The value is part of the closest fraction sequence calculation and represents the error left over from the first fraction. Multiply the accumulator value (55/128) by the first closest fraction's denominator (2) and subtract out the integers so the result is between -0.5 and +0.5 in a warped modulus kind of way. The excel function would be mod(55/128*2+0.5,1)-0.5. The 0.141 remainder (-0.141 or -18/128 to be more precise) generates the denominator of 7 not from 1/0.141 but from ratios and denominators from the previous calculation(s). The third - in this case final - fraction has the denominator of 128. Every 128 cycles contains one phase nudge from this beat frequency. The phase nudge isn't a single master clock cycle, but one of the two master clock cycle sequences two fractions before. The group of 7 master clock cycles (2/2/3) is repeated 18 times (18*7=126) and a two master cycle phase nudge is added, padding the sequence to 128 master clock cycles. The repetition frequency again comes from the error generated in the closest fraction sequence of about .0078 times the master clock frequency. 1/.0078 is the denominator in this case because the new fraction exactly matches the original ratio. The jitter frequencies come from the beat frequency errors. While my original assertion was the jitter frequencies were directly related to the denominators isn't accurate the denominators do provide the instantaneous frequencies when the sawtooth phase offset waveform(s) aren't phase modulated by the nudges I kept talking about. The phase modulation spreads the energy mostly between the beat frequency error values (0.141 in the instance above) and the denominator defined ratios (1/7 for the fraction corresponding to the 0.141 error). The sequence of nudges continue as the fraction approximations get closer to the phase accumulator ratio, getting lower and lower in frequency. At each step we see a sawtooth waveform in the phase offset corresponding to the beat frequency. Multiple beat frequencies mean multiple sawtooth waveforms are effectively overlaid on each other. The amplitudes of these waveforms can be found to a good first-order approximation. Since we only look at the phase error compared to the ideal waveform transition, the first fraction doesn't result in a sawtooth; the 2 master clock cycle increment (2.327 average) generates the output edge for comparison. The second fraction gives the 2/2/3 sequence where we see our first sawtooth in the phase error. Two master clock cycles only accumulate 110 in the modulus 128 accumulator. The result is a phase error change of ?18/128 per double cycle. Three master clock cycles accumulate 165 which (modulus 128) corresponds to a phase error change of +37/128. Since the phase error of a 2/2/3 cycle is ?18-18+37=+1, an adjustment for the straight-line phase drift results in a peak-to-peak (36 2/3)/128 in the phase error sawtooth for the three output cycles. This is a sawtooth, not a sinusoid, so an FFT will show harmonics at multiples of the frequency. The phase nudges also modulate the value further resulting in sidebands on those spurs. The lower the amplitude of the lower frequency beats, the less this value "smears." The third fraction makes an adjustment for that +1 error at each 2/2/3 cycle. 18 sets are required to accumulate a +18/128 phase error in 126 master clock cycles. It takes a single master clock pair with a phase error change of -18/128 to bring the phase back into alignment. This sawtooth has a beat frequency of 1/128th of the master clock and 18/128 peak-to-peak phase deviation. There is no error left over after this nudge so the 18 doesn't change as did the 37 above. The amplitudes can be derived generically based on the above arguments. I'll have the Excel spreadsheet completed before the weekend is through and present the text output results for the most significant beats with Austin's 48 bit accumulator value of 12AB3120BA81.Article: 43724
>I wanted to know whether Xilinx or Altera provides engineering samples >for free? Do you want Engineering Samples or free samples? "Engineering Sample" usually refers to chips that are not yet in production. They might have logic bugs or timing quirks. Usually the people who want them are happy to pay for them. They are often scarce. If so they get sold/issued to people who can provide the best feedback about how well they work. (or the big customers who need them or ...) If you want free samples... Well, it depends. Are you going to buy lots of chips when your design works? Have you already purchased lots of chips? Do you have a good track record? Are you teaching a class where the next generation of engineers will get hooked on the chips you use? If they give you the chips will you clutter up their support channels? Do you know somebody? (distributor? FAE?) -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
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