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Javi, If you are starting fresh, just use ISE as that's what Xilinx wants us to use. Foundation is their previous technology and is being gradually dropped. Service packs are bug fixes and updates and you have to install the latest available. -- ========================= Mikhail Matusov Hardware Design Engineer Square Peg Communications Tel.: 1 (613) 271-0044 ext.231 Fax: 1 (613) 271-3007 http://www.squarepeg.ca javid <javodv@yahoo.es> wrote in message news:c10cd8da.0206060252.4fd21835@posting.google.com... > Hello, > > I am new to fpgas. I was wondering if anyone could clarify me which is > the difference between ISE 4.2i (design environment PC) and the ISE > foundation 4.2i. I have seen that Xilinx also provide a "Service Pack" > for 4.2i, what is exactly this Service Pack?, Do I need to install it > or it is included in the ISE 4.2i?. > > Thanks a lot and Best regards, > > JaviArticle: 43926
Thank's Allan, I didn't know this group before. Laurent Allan Herriman wrote: > On Thu, 06 Jun 2002 14:59:52 +0200, Laurent Gauch > <laurent.gauch@amontec.com> wrote: > > >>Hi all, >> >>Do you know a good book on the PowerPC architecture (with OPB LPB >>arbitrer description)! >> >>(for introducing my students) >> > > Did you try > news:comp.sys.powerpc.tech or > news:comp.sys.powerpc.misc ? > > Allan. >Article: 43927
Cemal, If there are low Vt nmos transistors (in the interconnect), they have more leakage if the outputs are '1' than if they are at '0'. Depending on where these are used, they state of the logic will determine the output condition. So, yes, you are correct, because of the low Vt nmos. If there are low Vt pmos, the situation might be different. With each device family, the question of which is better, needs to be simulated, and then verified anew. Austin "Cemal Coemert (TIP)" wrote: > Ray Andraka wrote: > > > We also force zeros into the data path when there is no or invalid data at the input. In bit serial (and distributed arithmetic) designs, even constant values can cause considerable power dissipation since they result in bit transitions. > > If I understand you right a flip-flop dissipates less power when it drives '0' than driving '1'. Why ? > Is it maybe because of the leakage current when driving '1' ? > > Regards, CemalArticle: 43928
No. In a bit serial design operations are performed one bit at a time, so even if you are doing an arithmetic operation with a constant, it involves toggling bits. Zeroing the input makes so that no bits toggle in the serial process. The
process is CMOS, so the power dissipation is largely due to switching not for static levels.
"Cemal Coemert (TIP)" wrote:
> Ray Andraka wrote:
>
> > We also force zeros into the data path when there is no or invalid data at the input. In bit serial (and distributed arithmetic) designs, even constant values can cause considerable power dissipation since they result in bit transitions.
>
> If I understand you right a flip-flop dissipates less power when it drives '0' than driving '1'. Why ?
> Is it maybe because of the leakage current when driving '1' ?
>
> Regards, Cemal
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43929If you're generating both clocks, the absolute best way is to run the whole design at 100MHz and only clock in the 25 MHz every fourth clock. No CLKDLL needed! always @(posedge clk100) begin // 1-of-4 pulse generator gives clean clkEna pulses Gate25[3:0] <= |Gate25[2:0] ? Gate25 <<1 : 4'h1; // The ena can be synthesized into logic or into the ena pin on and FDE if( Gate25[3] ) Data25MHz <= Data25MHzIn; end If the 25MHz section wants 40ns for the logic rather than 10ns as suggested by the 100MHz clock, you can apply multi-cycle path timing consstraints to allow the full 40ns cycle for the Xilinx place and route. Otherwise, if your direction is only 25MHz to 100MHz domain, choosing the 270 phase for your 100MHz clock will give you 7.5 ns for the transition between the two domains. If you go back to the 25MHz domain this would result in only 2.5 ns suggesting a 180 clock for 5ns on each side might be better. I think the DLLs like the 0 phase feedback. Ken Mac wrote: > Thanks again John, > > I think I am understanding how to do this - just to confirm: > > I feed a CLKDLL with a 100MHz clock and use it to get a divided by 4 > output - i.e. 25MHz. > > I can then clock my 25MHz sections with this div4 clock and use the other > output of the CLKDLL (i.e. the 100MHz clock) to clock my 100MHz sections. > Was the last part of the 1st paragraph saying that I should use the 90,180 > or 270 phase output of the CLKDLL for the 100MHz clock? Also, which clock > signal should I feedback to the CLKDLL - the 0 phase 100MHz output or the > phase that I am using in my design? > > Sorry for all the detail but I have lost a lot of hours in the past trying > to work with multiple clock domains! > > Thanks for your time, > > Ken > > "John_H" <johnhandwork@mail.com> wrote in message > news:3CFE3720.F639DBA9@mail.com... > > If you use the CLKDLL to generate one clock (or both) you will absolutely > be > > able to make the transition between domains. The metastability question > does > > comes into play. Ray Andraka has pointed out how the clock net loading > and the > > jitter in the DLLs can make the destination edge happen after the source > signal > > has already transitioned the the next cycle, catching the wrong phase of > the > > signal. It may be better to choose a "safe" alignment of the signals so > you > > have a known delay (choose a different phase of the 100MHz clock) that > isn't > > destroyed by jitter and skew. > > > > If your 25MHz data path runs off the 100MHz clock with clock enables every > four > > cycles, your implementation with be clean - no problems with two clock > domains > > since the edged aren't related - they're the same! > > > > > > Ken Mac wrote: > > > > > John, > > > > > > Thanks for the reply. > > > > > > Surely if I use a CLKDLL then the relationship between the two clocks > and > > > the clock to out can be determined deterministically (!) and we can > > > therefore know if it will work or not? > > > > > > Cheers, > > > > > > Ken > > > > > > "John_H" <johnhandwork@mail.com> wrote in message > > > news:3CF79624.E49140E6@mail.com... > > > > Without losing data or inserting junk in your 100 MHz multiplexed > stream, > > > the 25 > > > > MHz has to be related to the 100 MHz in *some* fashion. If the > > > relationship > > > > between these clocks allows good clk-to-out at 25 MHz relative to the > setup > > > and > > > > hold at 100 MHz, accounting for the skew and jitter between the two > > > domains, > > > > everything works. If you don't know the relationship, only that > they're > > > phase > > > > locked, a short FIFO would be the cleanest implementation with a "half > > > full" as > > > > the startup state so the FIFO doesn't over or under fill. > >Article: 43930
"olivier JEAN" <seilebost@aol.com> schrieb im Newsbeitrag news:ad4152cf.0206060043.11943856@posting.google.com... > Hi everybody. > > I want to design a 10 bits counter by using a XILINX SPARTAN and a vhdl code. > I want a small and fast counter. What is fast for you? > How make it ? By using a LSFR counter or an ordinary counter ? LFSR will be faster. How much? Hmm, ask the timing analyzer. For Spartan(XL) I would assume, 10 bit counter can reach 70..80 MHz. Dont quote me, its just a rough guess. With a LFSR you may reach 100..120 MHz. > If I do design my counter by a LSFR's method, I don't know how make it. > Is there a web site whose explain how make it ? Have a look at the Xapps from Xilinx, the have a appnote for LFSRs which is almost foolproof ;-) -- MfG Falk .Article: 43931
"cfk" <cfk_alter_ego@pacbell.net> schrieb im Newsbeitrag news:8GzL8.21541$Wn6.698808495@newssvr21.news.prodigy.com... > Today, I am getting a PCI master device running in a VirtexE and I can see > some ringing and overshoot on my 33Mhz PCI clock signal that I generate. So, > I innocently added NET "PCICLK" IOSTANDARD="PCI33_3" to my UCF file. To my > surprise, there was no difference in the ringing and overshoot. I tried > making it a syntax error to convince myself that this file really was being > read by the ISE software and yes it is. So, I guess one of two things is > happening. 1) The statement NET <netname> IOSTANDARD="PCI33_3" is not being > set by the tool chain or my test setup was unable to see any difference. I > believe the default is LVTTL. Would I be correct in assuming that this is > the correct way to attempt to change the output voltage drive of a VirtexE > chip? No, t set the drive level (of LVTTL/LVCMOS) outputs, use NET my_netname drive=12; which will set to output driver to 12 mA (2/4/6/8/12/16/24 are possible) You can also adjust the slew rate of your outputs NET my_netname FAST; This will make the output faster (an causes more ringing if not propery terminated). The default setting for all outputs is SLOW. -- MfG FalkArticle: 43932
"Damir Danijel Zagar" <dzagar@srce.hr> schrieb im Newsbeitrag news:adn3ne$p9q$1@sunce.iskon.hr... > Hi, > > I've successfuly implemented design on Spartan II 200 but during > JTAG programming (Parallel Cable IV) verification fails on 257 > location. Also, when manualy identifying the JTAG chain, Spartan Hmm, dont know. > is reported as Virtex. Otherwise FPGA works fine and user ID This is just normal, Spartan-II is the low-cost version of virtex. Similar devices (gate count) are bitsteam compatible. -- MfG FalkArticle: 43933
"Damir Danijel Zagar" <dzagar@srce.hr> wrote in message news:<adn3ne$p9q$1@sunce.iskon.hr>... > Hi, > > I've successfuly implemented design on Spartan II 200 but during > JTAG programming (Parallel Cable IV) verification fails on 257 > location. Also, when manualy identifying the JTAG chain, Spartan > is reported as Virtex. Otherwise FPGA works fine and user ID > code is readable without any problem. What could cause the > verification problems? Regards, > > Damir Damir, This is a problem with certain Spartan II devices. They can not be verified by the IMPACT software. If you go to the Xilinx Website they have information about this in the Answers Database. The device should actually program correctly and work. A fix may be out for this in the June/July software update. NickArticle: 43934
Wow Bill, thats an old design, was that one from "The Shooooooo-man"? Maybe there is something pin compatible that the modern tools support? William Lenihan <lenihan3we@earthlink.net> wrote in message news:<3CFF0149.BCB187FC@earthlink.net>... > We have an old board design using xc3042 FPGAs (that's xc3042, not > xc3042A or xc3042L) and a new design for it using Verilog. The current > version of Synplicity Synplify will synthesize it into an xc3000 EDIF > netlist, but the recent versions of Alliance & Foundation do not seem to > support xc3000. > > How far back into Xilinx tool history do we have to go to find a P&R > tool that will handle a xc3042? And what versions of Windows, > Solaris/SunOS does it require? Do we have to go all the way back to > XACT?Article: 43935
Why do you need a PGA package? I don't think anyone is manufactuing CPLD's in PGA's. However, you can probably get an adapter, but they aren't cheap. -- ============================ Mikhail Matusov Hardware Design Engineer Square Peg Communications Tel.: 1 (613) 271-0044 ext.231 Fax: 1 (613) 271-3007 http://www.squarepeg.ca Boris and Cristi Sheikman <borisandcristi@my-beautiful-cristi.com> wrote in message news:7c8e7874.0206051408.5e93e572@posting.google.com... > Hi, > > I'm not sure if I'm posting this to the right newsgroup. Please > forgive the intrusion if I am. > > I am looking for >256 macrocell EEPROM based CPLD similar to the > Altera MAX 7000 series. Specifically it needs to have 5V I/O and it > needs to be in a PGA package. I've looked at Actel, Atmel, Lattice, > and Cypress. None of them seem to support this packaging. I'm not > looking for any backwards compatability but if it is somehow, in > someway, backwards compatable with some Altera devices... that can't > hurt. > > I used to play around with the MAX9000 (EPM9560GC280-20) but now those > are obsolete. > > Thanks! :-) > > -- BorisArticle: 43936
Yeah, seriously, you don't know how much time you will save just using a Spartan-II. If you don't want to redo the board, you can still make a kluge board with a Spartan-II CSP and voltage regulator that will fit onto the old pads or in the old socket. "Jay" <kayrock66@yahoo.com> wrote in message news:d049f91b.0206060827.6cde925c@posting.google.com... > Wow Bill, thats an old design, was that one from "The Shooooooo-man"? > Maybe there is something pin compatible that the modern tools support? > > William Lenihan <lenihan3we@earthlink.net> wrote in message news:<3CFF0149.BCB187FC@earthlink.net>... > > We have an old board design using xc3042 FPGAs (that's xc3042, not > > xc3042A or xc3042L) and a new design for it using Verilog. The current > > version of Synplicity Synplify will synthesize it into an xc3000 EDIF > > netlist, but the recent versions of Alliance & Foundation do not seem to > > support xc3000. > > > > How far back into Xilinx tool history do we have to go to find a P&R > > tool that will handle a xc3042? And what versions of Windows, > > Solaris/SunOS does it require? Do we have to go all the way back to > > XACT?Article: 43937
First of all, what problem are you trying to solve with a delay? In general, this isn't the proper solution, especially in an FPGA. "samlin" <gammalin@seed.net.tw> wrote in message news:<ad8bp5$t07$1@news.seed.net.tw>... > hi... > I have a problem... > if I use a delay in fpga... > How can I do? > Have any delay cell builtin library? > thank you...Article: 43938
Kevin Brace wrote > I tried what you wrote with ISE WebPACK 4.2WP2.0, and although when > synthesis starts, XST will display that it is going to generate an EDIF > and an NGC netlist, at the end, it will only generate an EDIF netlist. You're right. There was a NGC netlist from a previous synthesis run in my project dir, so I misinterpreted things a little. > I have to admit, being able to do everything from ISE's GUI is a lot > more convenient. > However, isn't this option to manually add XST command line options from > ISE's GUI new? > I don't recall ISE WebPACK 4.1 having such an option. > Don't know, I tried this option the first time in ISE4.2i SP2. /MichaelArticle: 43939
Falk Brunner wrote > Ahhm, it looks like that the commercial version of ISE (4.2, SP2) dont offer > this :-( > Anyone got a clue? In my previous post I forgot to mention, that you have to set the environment variable: XIL_PROJNAV_XST_OPTION=1 (or TRUE in UNIX) It should work in ISE4.2i SP2 then. /MichaelArticle: 43940
Hello, on the HP calculators, they are doing division of 20 bits number by 5 by doing a multiplication by $333334h followed by a shift right of 24 bit. This is accurate for every possible 20 bit number but one (where there is a 0.00001% error). I guess it would be as good for a 21bit number. do you need exact accuracy? regards, cyrille "Christopher Saunter" <Christopher.Saunter@durham.ac.uk> wrote in message news:adgamd$si4$1@sirius.dur.ac.uk... > Eyal Shachrai (eyals@hywire.com) wrote: > : does anyone know of an elegant way to divide a number > : of 21 bits by 5 ? > > Eyal, > I've outlined the way I do this for various fixed divisors below, > I hope it is usefull. I also hope I am not doing this in some silly > way... > > How precise do you need the result to be? Is the divisor fixed at 5? > > If the divisor is fixed, you are better of thinking of the operation as a > 'multiply by 1/5.' rather than a 'divide by 5' > > If this is the case, you can do the 'divide' as a multiply by 0.2, which > you can decompose into a series of bit shifts (not really existant in an > FPGA...) and additions. 0.2*X can be aproximated to within ~ 0.02% as > x/8 + x/16 + x/128 + x/256 + x/2048 + x/4096. > > I am doing something similar on data with a highish data rate (~100MHz). > If it is hard to meet the timing requirements of your design adding all 6 > signals in one colck cycle, the additions can be performed in pairs, > pipelined. (how I am doing it) If you have a lower speed reqirement, you > could use bit serial arithmetic, which would result in a highly reduced > logic usage. > > This may be a daft question, but are you sure you can't just divide by 4 > and compensate somewhere else? Probably not! > > Also, I note you are using a Virtex-II - this leads me on to a question / > idea..... I am working on something where a low latency divider > (<10cycles) with variable coeficients (a/b) could be a 'magic bullet' - > b is ~ 16 bits wide, a~10. Is there any reason I can't use the embeded > multiplier, connected to a BlockRAM acting as a look up table for the > coefficients to convert a divider of X into a multiplier of 1/X. I > understand this will have serious scaling issues as the number of bits of > acuracy required by 'b' rises mind... > > If you have a situation of a/b, where a has a high data rate, and b > changes infrequently, perhaps c=1/b could be generated with bit serial > arithmetic, and a fast parallel multiplier used to calculate a*c. > > Comments appreciated! > > Regards, > Chris SaunterArticle: 43941
Thank you so much :)) That helps a great deal!! Love Harkirat "Falk Brunner" <Falk.Brunner@gmx.de> wrote in message news:<adj0ap$11o0g3$2@ID-84877.news.dfncis.de>... > "harkirat" <i1073@yahoo.com> schrieb im Newsbeitrag > news:e3e8e2b7.0206031501.1b67fdb9@posting.google.com... > > Hi:) > > Im trying to implement a Genetic algorithm on the FPGA board which > > will do control computations based on parameters fed to it by the > > 68HC11EVB(which inturn takes the input from a motor which is the motor > > speed) via the serial interface and the sends the control signal back > > to the EVB(and hence to the motor) > > Ok, you want a serial interface between the FPGA and the 68HC11, right? > > > The FPGA board doesnt have any facility for doing this.I was wondering > > ??? > The only thing you need is to take a piece of ribbon cable, attatch some > connectors on both sides and plug the two modules together. > > > what components i need to make it communicate with the EVB via its > > serial interface > > Nothing but some bell wire, if you just want to go 1m (SPI I would guess). > If you need higher distance between the uC and FPGA, go for RS232, maybe > 422. > > > I found this peripheral connector > > http://www.burched.com.au/B5PeripheralConnectors.html > > on the FPGA manufacturers website.Im not too familiar with electronics > > im a mechanical guy..:o)Could you tell me if that would do the trick? > > I dont think you will need this connector.Article: 43942
Wanting to speed up the process of changing some IO buffer strengths I though I could use guided PAR with the previous routed NCD file. Since the EDIFs that had changed (confirmed with a diff) were o The top level where the only difference was in the buffer definitions. o Some INIT statements attached to a "build timestamp" ROM. it seemed like a good candidate for ``exact'' mode. This worked fine in that it matched 100% of the components and 100% of the signals and PAR finished in next to no time .... Unfortunately it totally failed to routed any of the PWR/GND connections - even after a second attempt using the re-entrant routing -k flag! Anyone seen this problem ? it doesn't seem to be mentioned in the answers database. Trying again with ``leveraged'' mode lead to 370 comps that guided placement failed to put back, ~5000 connections unrouted, an overall routing time much greater than the first one [which had hit the timing contraints in the first pass], and a small contsraint failure (32ps total).Article: 43943
hi, When I synthesize my design using Quartus II, the design uses approx. 5700 logic cells (APEX20KE 1500BC device). When the same design is synthesized in Leonardo Spectrum (the version which comes with Quartus II), the design takes 2000 logic cells !! Thats a huge decrease when the synthesis shifts from one synthesizer to another. Is this a normal result or is it be certain that I'm doing something wrong. My design has 2 10x10 multipliers and 8 10x10 adders as major components. Thanks, PrashantArticle: 43944
"Jason T. Wright" wrote: > The guys at Xilinx can correct/clarify this, but I have noticed (perhaps > have read) that the timing score is the sum, in picoseconds, of "total > negative slack;" i.e., add up the values for all of the paths that > didn't meet the constraints, and there you have it. > You are correct, sir! > > The other replies did a reasonable justification to what it means in a > more qualitative sense (i.e., what should I do with this number.) > > Of course, the number out is no better than the constraints in. > > Jason T. Wright > > Noddy wrote: > > > > Hi, > > > > How exactly are Xilinx's Foundation timing scores calculated? Write now I > > have just been comparing different incarnations of my design, and so things > > are relative to each other. But what is a good timing score, say for a 100 > > 000 gate design? > > > > Thanks > > adrian > > -- > Jason T. Wright > > The opinions I express are my own ... > unless otherwise indicated!Article: 43945
I am not surprised at all with your story. I have synthesized a PCI IP core, and the Altera's Quartus II native synthesis tool used about 30% more LEs than when I synthesized with LeonardoSpectrum-Altera. Not only that, the QII native synthesis tool doesn't support IOE FF duplication and a keep attribute to prevent circuit optimization (I need the keep attribute to preserve the structure of a 36-bit parity generator in PCI.). Since LS-Altera is free (Albeit the GUI is buggy.) even for QII Web Edition users (Although I rather get a free crippled ModelSim instead.), there really is no reason to use Quartus II native synthesis tool at all other than maybe some beginners may appreciate it because they won't have to import an EDIF netlist from LS-Altera. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Prashant wrote: > > hi, > > When I synthesize my design using Quartus II, the design uses approx. > 5700 logic cells (APEX20KE 1500BC device). When the same design is > synthesized in Leonardo Spectrum (the version which comes with Quartus > II), the design takes 2000 logic cells !! > > Thats a huge decrease when the synthesis shifts from one synthesizer > to another. Is this a normal result or is it be certain that I'm doing > something wrong. My design has 2 10x10 multipliers and 8 10x10 adders > as major components. > > Thanks, > PrashantArticle: 43946
javid wrote: > Hello, > > I am new to fpgas. I was wondering if anyone could clarify me which is > the difference between ISE 4.2i (design environment PC) and the ISE > foundation 4.2i. Xilinx publishes two different software products: 1. Alliance It only has P&R tools. You must have a synthesizer program to generate gate-level description out of a hardware programming language like VHDL, Verilog. An example of synthesizer program is Synplicity's Synplify (http://www.synplicity.com). Company name is Synplicity, product name is Synplify. 2. Foundation It has design entry (HDL editor), synthesis (FPGA Express AFAIK, it is from Synopsys, http://www.synopsys.com) and P&R tools. P&R tools in Alliance and Foundation are the same. Alliance is good for companies using different technologies, Foundation is good for companies using one technology. > I have seen that Xilinx also provide a "Service Pack" > for 4.2i, what is exactly this Service Pack? Service Pack is official name of Xilinx' software patch. You must follow patches of the software you are using. Xilinx software patches are announced in http://support.xilinx.com. > Do I need to install it > or it is included in the ISE 4.2i?. It is not included. You must download it from web (if you are a legal user). > Thanks a lot and Best regards, > > Javi UtkuArticle: 43947
On Thu, 06 Jun 2002 06:29:12 GMT, William Lenihan <lenihan3we@earthlink.net> wrote: > >We have an old board design using xc3042 FPGAs (that's xc3042, not >xc3042A or xc3042L) and a new design for it using Verilog. The current >version of Synplicity Synplify will synthesize it into an xc3000 EDIF >netlist, but the recent versions of Alliance & Foundation do not seem to >support xc3000. > >How far back into Xilinx tool history do we have to go to find a P&R >tool that will handle a xc3042? And what versions of Windows, >Solaris/SunOS does it require? Do we have to go all the way back to >XACT? You will need to go back to Xact 5.2.1 / 6.0.1 , and you will need the security dongle, and either DOS / W3.11 . I seem to remember that the non GUI 5.2.1 tools can be made to run under NT 4 , under some duress. Is there a business opportunity for my forward looking business to provide P & R services for these no longer supported products? I know I still have the sw and dongles somewhere, as well as the documentation, due to my pathological pack-rat mentality. Philip Freidin Philip Freidin FliptronicsArticle: 43948
I still have mine too and I know exactly where they are, but then I'm not
offering to go back to the stone ages. Makes one think that the pathological
part is not so much the pack-rat thing....I suppose you have a windows 3.1
machine sitting around under that stack of old data books too. Mine got donated
to the pre-school's yard sale last spring.
Anyway, The non-GUI tools will run under windows95, so they are probably also OK
under 98. (forget about doing any floorplanning unless you like doing it on
graph paper. The floorplanner won't work under anything but win3.11) I seem to
recall there being a problem with running XACT5/6 under NT4 because of the
dongle. Don't know if current sentinel drivers would make that OK or not (at
the time there was precious little sentinel support under NT4).
Philip Freidin wrote:
> You will need to go back to Xact 5.2.1 / 6.0.1 , and you will
> need the security dongle, and either DOS / W3.11 .
>
> I seem to remember that the non GUI 5.2.1 tools can be made to
> run under NT 4 , under some duress.
>
> Is there a business opportunity for my forward looking business
> to provide P & R services for these no longer supported products?
>
> I know I still have the sw and dongles somewhere, as well as
> the documentation, due to my pathological pack-rat mentality.
>
> Philip Freidin
>
> Philip Freidin
> Fliptronics
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 43949This may be a side effect of commercialization of Computer Science, but there is a very interesting scientific puzzle that one can observe at next week's Design Automation Conference (DAC). Namely, that although formal verification has been a degenerating research program since at least 1972, nearly every technical paper and new exhibitor is describing tools for formal verification of circuits. These tools supposedly lead to RTL sign off without a need to simulate and verification usally by software checking of user supplied constraints. Seemingly "bread boarding" and its modern equivalent "extracted delay gate level simulation" are no longer needed. Here are Some of the puzzles. 1) because formal proving is related to BDD construction from net lists, this formal analysis should be usable in communication code breaking cryptography. Yet, paper at this year's Eurocrypt showed heuristics for the related NP complete problem do not help. Reference is: Krause, M. "BDD-based Cryptanalysis of Keystream Generators", Proceeding 2002 Eurocrypt, Springer, 2002. Also the objections to formal verification first detailed in the Lighthill Report submitted to the British Government in 1972 still need answers. Some are: 1) how is correctness of human coded assertions verified, i.e. errors in assertions become injected into formally verified circuits?, 2) how can circuit proving data structures not have exponential size? 3) how can verification work when the same formal algorithms are used to synthesize circuit in one direction and verify them in other direction using same "closed system" algorithms. It is unfortunate that DAC technical committee does not try to balance papers that advocate theories with papers that falsify theories. In any case, what is probably the most one side scientific refereeing in the last 500 years should make for interesting listening and observing. -- Steve Meyer Phone: (612) 371-2023 Pragmatic C Software Corp. email: sjmeyer@pragmatic-c.com 520 Marquette Ave. So., Suite 900 Minneapolis, MN 55402
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