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Kevin Brace wrote: > Please, synthesis tools (XST and Synplify), just convert whatever code > is given even if it doesn't make much sense, or something is not being > done in an optimal way. Well, the code isn't PALASM. For some (many?) constructs, the mapping to the target architecture is a matter of judgement. If the tool vendor's judgement does not agree with your, you can always instantiate primitives, which is what I sometimes do for OE if I am working in VHDL. Verilog (no generate just yet) is harder. But I am inclined to agree that Synplicity need to refine the synthesis issue you first raised.Article: 41026
D Brown wrote > With these, ISE can never find the specified NET. So, how do I specify the > NET name? What syntax do I use, especially if it's not in the top level > module? I go along with Hobson. In general, the fastest way to get the syntax correct is to open up the constraints editor, add a few constraints of the correct type, and save the results as something like tmp.ucf. Then look in tmp.ucf.Article: 41027
As indicated already, you conceptualizing it correctly. You just missed a few other pieces. Where I work for instance, we use FIFOs with NEMPTY and NFULL outputs which indicate when the FIFO is empty or FULL to whatever is writing/reading to/from it. This way the hosts (device reading and writing) can tell when to stop reading/writing and when to start reading/writing. LT In article <fb35ea96.0203190148.770f2b6@posting.google.com>, dottavio@ised.it (Antonio) wrote: >I can't understand how a FIFO could work well if it is writed with an >high data rate and it's read with a low data rate, from my point of >view, reallt soon it became full and all the data that continue to be >writed into the FIFO will put away the first data, where's my >conceptual error ?? > >AntonioArticle: 41028
Hi everyone I am using synplicity 6.2.4 to syn and quartus II 1.1 to P&R, in my design, there are two clock, one is 25Mhz to drive the cpu, the other is 33Mhz to drive the timer, this two clock do not have any relation in the timer, the counter can be driven by 25Mhz clock or 33Mhz clock, so I use a controll bit to select them, then use the result to drive counter so when quartus finish his work, he tell me that my design may not function, and 1300 path can not be operational becasue their clock skew larger than logic delay. I think the clock mux will make the clock signal go down the clock net, and become a logic signal, and then drive the FF how to deal with this?Article: 41029
You have several choices. 1. ensure that any mux'ed clock src-dst also uses the muxed clock. Put Global Signal=On assignment onto the mux output 2. cut paths from plain clk to mux'ed clk destinations and visa versa. 3. Use fifo between these type of transitions if they are necessary and you can ensure common src / dst clk net. Guy "ssy" <shengyu_shen@hotmail.com> wrote in message news:f4a5f64f.0203191658.cbeb868@posting.google.com... > Hi everyone > > I am using synplicity 6.2.4 to syn and quartus II 1.1 to P&R, > in my design, there are two clock, one is 25Mhz to drive the cpu, the > other is 33Mhz to drive the timer, this two clock do not have any > relation > > in the timer, the counter can be driven by 25Mhz clock or 33Mhz clock, > so I use a controll bit to select them, then use the result to drive > counter > > so when quartus finish his work, he tell me that my design may not > function, and 1300 path can not be operational becasue their clock > skew larger than logic delay. > > I think the clock mux will make the clock signal go down the clock > net, and become a logic signal, and then drive the FF > > how to deal with this? -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 41030
Hi, Do you know where I can find the open source code of Fixed Point Math Library? thanks, :-)Article: 41031
For LVDS at high speed, the APexII (NOT 20kC) uses embedded blocks and include the SERDES with programmable serialization and parallelization factors for the integrated PLL in the block. Stratix, depending on your schedule will also have the embedded LVDS blocks. FOr embedded LVDS in Xilinx you'll need their VirtexPro devices. guy "Martin Sauer" <msauer@gmx.net> wrote in message news:3C95914A.3030002@gmx.net... > Hello, > > can you tell me which FPGA is better Xilinx Virtex II or Altera Apex 20KC? > I want to use an FPGA in a fastprototyping enviroment with an LVDS > interface. Can I use both FPGAs or there is one better? > > Thank you for your answer. > > bye > > martin sauer -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 41032
Jacky Renaux <renaux.jacky@wanadoo.fr> wrote in message news:<2002319-12443-423681@foorum.com>... > Try > http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack > the free package is very powerfull , be sure you have a large disk space > and fast internet download access. > > regards Altera also has a free software package which is pretty powerful at: https://www.altera.com/support/software/download/sof-download_center.htmlArticle: 41033
I am very curios. Has anyone themselves (without FAE/Expert help) done an Stratix compiles and comparisons to VirtexII? Curious about push-button results and impressions. Now as an independent consultant, I need to sensitize myself to push-button expectations of users. Thanks, Guy Schlacter ex-Altera Field Specialist President Abosulte Consulting, Inc. -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 41034
Hi, I am using Spartan-II chip, I want to know how much possibility that the RTL and gate-level simulation don't match? When they don't match, how can I detect that? It seemed that the synthesis report in ISE 4.1 doesn't give me a warning or error? -- Best Regards,Article: 41035
Harris, Comments on your questions: 1) You aren't doing anything wrong here. If the speed of your reset is critical, we typically recommend not using STARTUP_VIRTEX to control GSR due to the (usually) longer delays on that net. However, if your routing is congested and speed isn't critical, it's a nice little feature. 2) Asynchronous vs. Synchronous reset is purely design dependant. 3) Applying a signal to the GSR pin of the STARTUP_VIRTEX block will reset every flop on the device asynchronously. There is no option to have it be synchronous. The CLK pin on the STARTUP_VIRTEX block is purely to synchronize the startup sequence (the sequence that occurs at the end of configuration) to the clock attached to this pin. It has nothing to do with the GSR pin. Go to http://support.xilinx.com and click on Software Manuals on the left-hand side. More information on the STARTUP_VIRTEX block can be found in the Libraries Guide. Regards, Hobson Xilinx ApplicationsArticle: 41036
The Pragmatic C Verilog simulator called Cver is now being distributed in source form and it is free for non-commercial use. It is a "real world" commercial quality full IEEE P1364 Verilog interpreted simulator, i.e. signals usually have full strength modeled as 3 vector components allowing 128 different values. Some advantages are: 1) Full PLI support (tf_, acc_ and Verilog 2000 vpi_) with no speed penalty for using PLI. 2) Integrated Verilog debugger with gdb style convenience features. 3) P1364 standard modified to match other simulators so seamlessly fits into design flows, 4) Full glitch detection on paths and gates - allows efficient hand crafted design, 5) distributed in source form so it can run on any computer. 6) Designs load at least twice as fast as any other simulator. 7) No design size limitations - why put up with your size limited FPGA Verilog simulator? FPGA tool style pricing for commercial version. It is of interest both for Electronic design and for learning simulator and compiler implementation techniques. Because of the complexity of Verilog operations, interpreters can be competitive in speed without loss of flexibility. More information available at Pragmatic C web site www.pragmatic-c.com. -- Steve Meyer Phone: (612) 371-2023 Pragmatic C Software Corp. email: sjmeyer@pragmatic-c.com 520 Marquette Ave. So., Suite 900 Minneapolis, MN 55402Article: 41037
Typically, you can restrict the reset to a small subset of the flip-flops in the design. Doing so will have the ASIC purists practically stringing you up, but really as long as you can get the design into a known state as a result of resetting a few key flip-flops you accomplish the goal. Keeping it to the few flip flops has the advantage of not needing huge fanouts and not using resources that may be critical to the performance of the design otherwise. For a data path design, you can just reset the outputs from the FPGA and hold them reset for some delay period determined by the latency through the design, and apply reset to one flip-flop/register in each data path loop in the design (eg accumulators, IIR filters etc), and reset the inputs for as long as the reset is applied. The strictly feedforward paths will self clear. Executed properly, this minimal reset is indistinguishable from a full chip reset when viewed from the FPGA pins (except for perhaps fluctuations in the supply current while the internal circuit settles out). Hobson wrote: > Harris, > > Comments on your questions: > > 1) You aren't doing anything wrong here. If the speed of your reset is critical, we typically recommend not using STARTUP_VIRTEX to control GSR due to the (usually) longer delays on that net. However, if your routing is congested and speed isn't critical, it's a nice little feature. > > 2) Asynchronous vs. Synchronous reset is purely design dependant. > > 3) Applying a signal to the GSR pin of the STARTUP_VIRTEX block > will reset every flop on the device asynchronously. There is no > option to have it be synchronous. The CLK pin on the STARTUP_VIRTEX block is purely to synchronize the startup > sequence (the sequence that occurs at the end of configuration) to > the clock attached to this pin. It has nothing to do with the GSR pin. > > Go to http://support.xilinx.com and click on Software Manuals on the > left-hand side. More information on the STARTUP_VIRTEX block > can be found in the Libraries Guide. > > Regards, > Hobson > Xilinx ApplicationsArticle: 41038
Why? Your clients can push the button just as well as you can. How does that set you apart? Guy Schlacter wrote: > Now as an independent consultant, > I need to sensitize myself to push-button expectations of users. > > Thanks, > Guy Schlacter > ex-Altera Field Specialist > > President > Abosulte Consulting, Inc. > > -- > Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 41039
As an active ISE WebPACK 4.1 user, I don't find Altera's free tools as powerful as Xilinx's offerings because Altera doesn't offer a limited version of ModelSim like Xilinx does. Yes, ModelSim XE-Starter (The free version that comes with ISE WebPACK.) slows down after 500 lines of code, but it still lets the user run the simulator past 500 lines of code, and because it is an OEM version of ModelSim, it lets me run HDL testbench code. I personally find the slow down acceptable for my application. However, Altera offerings (Quartus II 2.0) only has a simple waveform simulator which lacks the ability to run HDL testbench code. Plus, Quartus II 1.1/2.0 Web Edition tends to be less reliable compared to ISE WebPACK 4.1 on Windows 98 PCs because QII tends to consume system resources heavily. Also, LeonardoSpectrum-Altera (LS-Altera) tends to be buggier compared to ISE WebPACK's synthesis tool XST (The latest 2002 version is somewhat better, but still has some problems, and I have to question Mentor Graphics' quality control. Do Mentor Graphics/Exempler Logic/Altera test LS-Altera before releasing it? It almost seems like they never test their products.) At least, I personally will like to see Altera letting users use a limited version of ModelSim AE (Altera Edition) for free, but until that happens, I recommend using ISE WebPACK + ModelSim XE-Starter for doing serious hobby projects with free tools. I am sure some die hard Altera fans won't appreciate my comments, but that is too bad because Altera's free tools are clearly inferior compared to Xilinx's offerings. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) "arpit.desai" wrote: > > Jacky Renaux <renaux.jacky@wanadoo.fr> wrote in message news:<2002319-12443-423681@foorum.com>... > > Try > > http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack > > the free package is very powerfull , be sure you have a large disk space > > and fast internet download access. > > > > regards > > Altera also has a free software package which is pretty powerful at: > > https://www.altera.com/support/software/download/sof-download_center.htmlArticle: 41040
Jacky Renaux wrote:
>
> Try
> http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=ISE+WebPack
> the free package is very powerfull , be sure you have a large disk space
> and fast internet download access.
>
Yes, I am downloading ISE WebPACK 4.2WP0.0 right now with a 56K
modem . . .
I usually download the full version (120MB for ISE WebPACK + 35MB for
ModelSim XE-Starter II), and will like take 12 hours to do so . . .
Supposedly, the new ModelSim XE-Starter II has less restriction on the
slow down issue of ModelSim XE-Starter, so I will play around with it,
and see what happens.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41041
My question starts from the fact that I've a QPSK modulator
the incoming data rate is 2 bit x 27.5Mbps, I apply the clock
governing this data rate to the write clock of my fifo while the write
enable is tied to VCC, the read clock instead is (27.5x4)MHz but it is
produced internally to the FPGA while the read enable is at 27.5MHz.
This is not burst transmission, so I'm a little bit in trouble that if
I have also a little frequency error all my system doesn't work. Maybe
the FIFO is not the right solution in this application, what do you
think about ??
Thanks
Antonio
Article: 41042>Remember that the period constraint must be reduced by 1/2 of the total peak to >peak jitter if you expect to meet your timing. Now that we routinely have >clocks of 100 to 300 MHz, the usually ignored jitter is now a significant >factor. Why only 1/2 of the P-P? Can't I get a worst case late followed directly by a worst case early? -- These are my opinions, not necessarily my employer's. I hate spam.Article: 41043
Falk Brunner wrote:
>
>
> Hmm, this thread is going on for a while and I didnt feel to say somthing.
> Until now.
> Kevin, why do you complain about this.? With XST doing so,
>
> a) Tco is getting better
> b) you dont loose any FlipFlop, since the IOB FF are "free" anyway.
>
Compared to using a regular CLB FF, using an IOB OE FF makes Tsu
worse because routing distance will get longer, and will get only worst
if the device's die gets larger.
Also, for a path starting from unregistered control signals of PCI bus
(FRAME#, IRDY#, DEVSEL#, TRDY#, and STOP#) to AD[31:0] or C/BE#[3:0]'s
OE FFs, I already got 4 levels of 4-input LUT, and so far, I haven't
been successful reducing the level of LUT.
Therefore, I decided to not to use IOB OE FFs, and use only two CLB FFs
for OE (one for AD[31:0] and one for C/BE#[3:0].) so that the signal
paths with 4 levels of LUT can meet PCI's setup time much more easily
than using IOB OE FFs.
However, I will still need the output FFs to be inside IOBs to meet Tco
requirements of PCI, and they have to be duplicated to allow even parity
calculation.
Yes, not putting OE FFs inside IOBs will make Ton/Toff much worst than
Tco, but what happens is that PCI specification has a thing called
Address/Data Stepping which allows PCI devices to turn on output buffers
a cycle or more later.
Xilinx and Altera use this technique in their PCI IP cores, so I decided
to use it, too.
But the problem is XST overrides my design of using one OE FF for
AD[31:0], and one OE FF for C/BE[3:0], and duplicates them 32 times and
4 times, respectively.
Attaching "keep" attribute didn't help either.
> > If I wanted the OE FFs merged into IOBs, I will manually duplicate them
> > in my code, but I chose not to do so.
>
> So there are command line/GUI settings that allows this. But you have to
> know how to handle your tools. And AKAIK, a VHDL compiler isnt a
> tamagotchi??
> ;-))
>
> Regards
> Falk
I thought Tamagotchi was dead.
Regardless, I already read XST user guide, and studied all the synthesis
and command options, but couldn't find anything that will solve my
problem.
There is nothing more irritating than the tool doing something
differently than what the design does.
Kevin Brace (In general, don't respond to me directly, and respond
within the newsgroup.)
Article: 41044Hello Does anyone look at the fastest fpga of the market? Specially about the io input timing, to record data of an ADC? Which sample frequency can be reach? Thanks ========================= Michel Le Mer Satellite Terminal Access 12, square du Chene Germain 35510 Cesson-Sevigne Tel. 33 (0)2 23 20 04 72 =========================Article: 41045
I am looking for used ones. Does anyone have what I am looking for? Where do I go to find a dealer for that, I don't mind buying used ones as long as they work.Article: 41046
With PCI interface only! Jimmy Zhang wrote in message <_lYl8.74605$ZR2.35796@rwcrnsc52.ops.asp.att.net>... >I am looking for used ones. Does anyone have what I am looking for? >Where do I go to find a dealer for that, I don't mind buying used ones as >long as they work. > >Article: 41047
Steve Meyer <sjmeyer@www.tdl.com> wrote: : The Pragmatic C Verilog simulator called Cver is now being distributed : in source form and it is free for non-commercial use. It is ... I am interested in user reports about CVER. Could people using or having used CVER report their experience her? B.t.w, thanks to Steve for his offer! Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 41048
Tool-> Account ->news ->append->news.... and nntp is "news.cn99.com "Sniper Daryl" <e-engineer@eastday.com> ??????:289dc5a9.0203132210.32599f08@posting.google.com... > if anyone would tell me how to set in Outlook ExpressArticle: 41049
Hi, under Quartus, programming in VHDL, i use a component instantiated with some OPEN ports, like: MYINST: My_Entity port map( FIRST_IN => DATA1, SECND_IN => OPEN, FIRST_OUT => DATA2, SECND_OUT => OPEN ); I get the error: Association List error: OPEN association element is incompatible with formal SECND_IN and the context-sensitive help says: "CAUSE: The VHDL Design File (.vhd) contains an association element that is incompatible with the specified formal. The association element and the formal must be compatible. ACTION: Edit the file to correct the error and recompile the design." and then gives the suggestion to check Section(s) 4.3.2 of the IEEE Std 1076-1993 IEEE Standard VHDL Language Reference Manual, that I cannot access. But in every manual and book i got it seems that what I did is considered correct. Do you know such an incompatibility? thank you Luigi
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