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Hi Russel, There are a couple ways that I can think of that might allow you do do what you want. The synthesizer is doing logic reduction and changing the names and meanings of signals in this process. 1) Put your clock generator in its own module definition, then turn on Leonardo's "preserve hierarchy" button, to maintain hopefully the port names and meaning. 2) Generate a seperate EDIF for your clock generator, and wire it into your design in Quartus using the name you like for the clock net. 3) Make the clock a primary I/O of your EDIF so Leonardo can't rename it. Having said that, in general, you don't generate clocks in FPGA's from the output of counters. You usually would use the outputs of your counters as ENABLES for flops and clock everything directly from that high frequency net. Burns power, limits speed, but makes the tools happy. Regards rjshaw@iprimus.com.au (russell) wrote in message news:<c3771dbf.0202260038.5876fcc3@posting.google.com>... > Hi all, > > I've just started using web Quartus-2 to compile > an edif file from leonardo spectrum (acex 1k30). > > In the edif file (and in the vhdl code), i have a > signal called clk1M25 (an internal node). I wanted > to set a timing constraint on it in relation to the > clock input it is derived from (thru a counter circuit). > > However, clk1M25 doesn't appear anywhere using > the node-finder search box. How can i find it?Article: 40076
"X. Q." wrote: > Hi, Andy: > > Thanks for your information. If I am not wrong, did they ship products to > Britain also? Yes they did - don't think we even paid! I don't know about package pin types, I've been dealing with another ASIC we've been retargetting (didn't have time to test an FPGA version). We did pay to get another one made with ceramic casing. > I was doubt whether I would get the chip since I am in Singapore. don't see why that should be a problem - ask. AndyArticle: 40077
I think if FPGA Express did anything with EDIF, it would be as output not input. I am sure there is no way to take ViewDraw EDIF into FPGA Express. What you probably can do is create EDIF from ViewDraw of a block (that is implemented with schematic) and make a reference to it (black box) from within your VHDL or Verilog that is the input to FPGA Express. The output Edif from FPGA Express will reference the ViewDraw block. When this output from FPGA Express is fed into the P & R sw (ngdbuild if you are using Xilinx), then it will reach out and pull in the EDIF from ViewDraw. I.E. HDL top level referencing a schematic submodule. Philip Freidin On 25 Feb 2002 16:07:22 GMT, c.heise@XYtu-bs.de (Carsten) wrote: > >Hello, > >has anybody used an EDIF netlist in FPGA Express? The documentation tells >that it is possible to do so, but whenever I take an EDIF netlist (in my >case from ViewDraw) as source file and want to create an implementation >from it, there are no errors or warnings, but I cannot look at the >schematic and the EDIF netlist, that can be exported from FPGA Express is >nearly empty: > >(edif NUR_EDIF > (edifVersion 2 0 0) > (edifLevel 0) > (keywordMap > (keywordLevel 0) > ) > (status > (written > (timeStamp 2002 2 20 14 41 6) > (program "FPGA Express" > (version "3.3.1.4719") > ) > (author "carsten") > ) > ) > (library DESIGNS > (edifLevel 0) > (technology > (numberDefinition) > ) > (cell NUR_EDIF > (cellType GENERIC) > (view Netlist_representation > (viewType NETLIST) > (interface) > (contents) > ) > ) > ) > (design NUR_EDIF > (cellRef NUR_EDIF > (libraryRef DESIGNS) > ) > ) >) > >Can anybody send me a hint? >Thanks > >Carste Heise Philip Freidin FliptronicsArticle: 40078
I have done this after a bit of effort figuring it out. You can in fact import EDIF into FPGA Express if you use the correct netlist export command: edifneto -L unit -L hard -X $BLOCKNAME You should do this by customizing your tools menu and adding an item for FE netlists with "edifneto" as the command, and "-L unit -L hard -X $BLOCKNAME" as the argument. Make sure to pass the "Schematic Checker" first. -robert Carsten wrote: > Hello, > > has anybody used an EDIF netlist in FPGA Express? The documentation tells > that it is possible to do so, but whenever I take an EDIF netlist (in my > case from ViewDraw) as source file and want to create an implementation > from it, there are no errors or warnings, but I cannot look at the > schematic and the EDIF netlist, that can be exported from FPGA Express is > nearly empty: > > (edif NUR_EDIF > (edifVersion 2 0 0) > (edifLevel 0) > (keywordMap > (keywordLevel 0) > ) > (status > (written > (timeStamp 2002 2 20 14 41 6) > (program "FPGA Express" > (version "3.3.1.4719") > ) > (author "carsten") > ) > ) > (library DESIGNS > (edifLevel 0) > (technology > (numberDefinition) > ) > (cell NUR_EDIF > (cellType GENERIC) > (view Netlist_representation > (viewType NETLIST) > (interface) > (contents) > ) > ) > ) > (design NUR_EDIF > (cellRef NUR_EDIF > (libraryRef DESIGNS) > ) > ) > ) > > Can anybody send me a hint? > Thanks > > Carste Heise >Article: 40079
> If you want to have a slower clock in your design, the clean way to do > it is you generate a flip flop enable at the lower frequency and > continue to run the high frequency clock to all the flip flops. Burns > power but its what the componant architecture wants to see. The > general rule is that the only thing the clock net should drive is a > clock pin on a flop, and the only thing a reset line should drive is > the reset pin of a flop. If you can structure your logic around those > constraits, the tool will be a happy camper and you will get no > warnings. Hi, What to do when I have negative reset (as usual with uP) and I connect reset signal to fpga, but internal ffs wants to get positive reset (f.e. MAX3000). When I place inverter and all ffs are feed from inverted signal I got messages 'non global signal usage may result'. jerryArticle: 40080
Peter Alfke <palfke@earthlink.net> wrote in message news:3C7BAC5E.4841D273@earthlink.net... > Sorry, jut reading your question again: > For a 2 megabit ROM, you would need almost all the resources in a big FPGA. > I would go for an external EEPROM. > > Peter Alfke > Actually, a 2 Mb ROM fits pretty nicely into a medium-sized Altera Stratix part (EP1S30) leaving 170 4Kb blocks and almost 300 0.5Kb blocks available for other stuff. Logic-wise it's about the same size as a XC2V3000. -Pete-Article: 40081
On Mon, 25 Feb 2002 17:29:49 -0000, "Paul" <nospam@nospamplease.com> wrote: >Having come back to logic design after a 5 year break, I had a bit of a >culture-shock with the myriad of different tools and their inherent >strengths and weaknesses. > >I'm hoping to help make it a bit easier for others and expand my current >limited understanding by creating a set of forums for discussion. There already seem to be enough news groups that cover these topics. >My aim in creating the forums was: > >1) Provide a forum for discussion of various programmable logic tools and >how best to use them. Sufficient groups already exist. >2) Provide a place to store tips and techniques used by programmable logic >designers. For FPGAs there is www.fpga-faq.com >3) Complement the discussions on the main programmable logic newsgroups and >perhaps go into more specific detail and provide more tutorial information >to supplement the newsgroup information. You are welcome to create content for www.fpga-faq.com and have it added to the FAQ section, or write separate tutorials. >4) Provide an edited summary of valuable discussions on the newsgroups. The full archive of comp.arch.fpga from its inception is maintained at www.fpga-faq.com , with extensive indexing and thread reading. >At present I'd appreciate any comment and assistance in starting up the >process. > >http://pub64.ezboard.com/bfpgatipsandtricks Well, clearly I believe that the news groups, and www.fpga-faq.com (which I host ) already fills this need. >Because the forums are new I've focussed on Altera-based tools, but over the >coming weeks if there is sufficient interest I'll attempt to extend them to >other device toolsets. > >I should point out that there is little useful content on the forums as yet, >which is where your assistance would be invaluable. > >You will need to register a user name, email and some details to post >(viewing doesn't require this). How accurately you want to do this is >entirely up to you. None of this is required for the news groups or www.fpga-faq.com . >If you need to contact me, try pauljnospambaxter@hotnospammail.com without >the nospam bits. > >Feedback appreciated. > Philip Freidin, Regular contributor to comp.arch.fpga and host of www.fpga-faq.com Philip Freidin FliptronicsArticle: 40082
It's in help\data\xdl Steve "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3C71A5E1.53D596F4@algor.co.uk... > > Anyone know where the XDL documentation has got to ? In my 2.1i > installation it was in the `userware' directory but this doesn't seem to > exist for 3.3i & 4.1i. > >Article: 40083
Peter Ormsby wrote > > Actually, a 2 Mb ROM fits pretty nicely into a medium-sized Altera Stratix > part (EP1S30) leaving 170 4Kb blocks and almost 300 0.5Kb blocks available > for other stuff. Logic-wise it's about the same size as a XC2V3000. Xilinx is shipping today - and has been shipping for many months - FPGAs with such a memory capacity. The Virtex-II family started shipping more than a year ago. Let's keep this newsgroup clean, without confusing anybody's future plans with reality. Otherwise we get into arguments like: "My dream is much better than your dream". And that serves nobody. Peter Alfke > > > -Pete-Article: 40084
I've pretty much came to the decision to use the Virtex-II device. The DCI feature means I don't need thousands of series resistors everywhere to guarantee timing (plus it has a lot more RAM). The HSTL I/O standard appears to be the fastest (from using the Virtex-II ibis model). Anybody used/verified this ibis model? Any advice? I've noticed some of these new fast (300MHz+) DDR/QDR SRAMs have HSTL I/O levels. Thanks, Steve rickman <spamgoeshere4@yahoo.com> wrote in message news:<3C6F58FB.1E11DA9B@yahoo.com>... > I see that this question has met with no reply after two weeks. I guess > that is the answer... > > > > Russell Shaw wrote: > > > > Guy Schlacter wrote: > > > > > > QuartusII v2.0 just released Friday and has been producing very good > > > results for both this new family and ApexII. > > > > When is Quartus web edition going to include Acex 1k devices? > > > > > As far as GATE COUNTING, every vendor and family uses differnet > > > nomenclature. For the user, you are best off descregarding gate counts > > > and comparing > > > 4input LUTs > > > Available Memory counts > > > Other dedicated Resources Multipliers etc. > > > > > > Best of Luck, > > > Guy Schlacter > > > Altera Corp. > > > > > > "Steve Holroyd" <spholroyd@iee.org> wrote in message > > > news:b623f4cf.0201111039.2a16155@posting.google.com... > > > > > > > I am currently task of recommending the largest, fastest and most > > > > memory FPGA that's readily available the first half of this year for a > > > > FPGA Array Card. > > > > > > > > The choices have been narrowed down to two families Altera's APEX-II > > > > (EP2A70) and XILINX Virtex-II (XC2V6000). > > > > > > > > Which can operate at the highest speed? > > > > > > > > Steve > > > > > > -- > > > Posted via Mailgate.ORG Server - http://www.Mailgate.ORG > > > > -- > > ___ ___ > > / /\ / /\ > > / /__\ Russell Shaw, B.Eng, M.Eng(Research) / /\/\ > > /__/ / Victoria, Australia, Down-Under /__/\/\/ > > \ \ / \ \/\/ > > \__\/ \__\/ > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 40085
Because some modules of my design are generated by high-level and logic synthesis engines,or developed by others.In this case,some internal nets and signals have no sources and involves VCC and GROUND after logic synthesis by Leonardo and XST.They passed most of the implementation process except the configuration.So what these errors originated from?And what can I do with them? BTW,I am using xcv800-4hq240. Hope your kind help.Article: 40086
There are error messages. Tue Feb 26 10:19:25 2002 Running DRC. ERROR:DesignRules:368 - Netcheck: Sourceless. Net U1/ram_1_move_true_net_ram_1 has no source. ERROR:DesignRules:10 - Netcheck: The signal "U1/ram_1_move_true_net_ram_1" is completely unrouted. ERROR:DesignRules:368 - Netcheck: Sourceless. Net U1/bus_1_romctrl_17 has no source. ERROR:DesignRules:10 - Netcheck: The signal "U1/bus_1_romctrl_17" is completely unrouted. ERROR:DesignRules:368 - Netcheck: Sourceless. Net U1/nx5384 has no source. ERROR:DesignRules:368 - Netcheck: Sourceless. Net U2/U3/u0_seq_I1_VCC has no source. ERROR:DesignRules:10 - Netcheck: The signal "U2/U3/u0_seq_I1_VCC" is completely unrouted. ERROR:DesignRules:368 - Netcheck: Sourceless. Net U2/U3/u_left_I9_GND has no source. ERROR:DesignRules:10 - Netcheck: The signal "U2/U3/u_left_I9_GND" is completely unrouted. ERROR:DesignRules:368 - Netcheck: Sourceless. Net U2/&__A__37 has no source. ERROR:DesignRules:10 - Netcheck: The signal "U2/&__A__37" is completely unrouted. ERROR:DesignRules:368 - Netcheck: Sourceless. Net U2/&__A__1 has no source. ERROR:DesignRules:10 - Netcheck: The signal "U2/&__A__1" is completely unrouted. WARNING:DesignRules:367 - Netcheck: Loadless. Net U1/IPB_1_CTRL_OUT has no load. WARNING:DesignRules:367 - Netcheck: Loadless. Net U1/SOF has no load. WARNING:DesignRules:367 - Netcheck: Loadless. Net U2/LADC_OUT<15> has no load. WARNING:Bitgen:25 - DRC detected 13 errors and 3 warnings.Article: 40087
Hi, pls help with refrences for simulation of EEPROM in software. Thanks, AlexArticle: 40088
Strangely,I find that,compared with the version 2.1,4.1,ISE3.1 lacks some very important functions.For example,the schematic editor lacks "create symbol from edif netlist", and the "add source to project" has no edif format. Maybe,it is because of I haven't found these functions yet.Article: 40089
Steve Casselman wrote: > It's in help\data\xdl > > Steve > > Thanks. Doesn't seem to have improved over the 2.1i doc though, still showing a date of July 2000!Article: 40090
Hi, We generally write behavioral models for serial EEPROMs. We build our Flash models based on the FMF model. Also, check denali.com and determine whether their memory modeling software has what you need. good luck <voytov@ihpc.net> wrote in message news:3c7c5d9f_1@news1.prserv.net... > Hi, > pls help with refrences for simulation of EEPROM in software. > Thanks, > Alex > >Article: 40091
Now everything is clear for me, thank you all AntonioArticle: 40092
Hi, I am trying out QuickWorks 9.1. It is all right for me to synthesize and place & route. But it seems quite sluggish to me, since it won't finish long after I pressed Save. I understand that this is an evaluation version. Does anybody have any comments on Quick Works 8.22 and the true version of QuickWorks? Is it fast and stable? How large is the size of .chp file for a QL3060 bitstream? -- Best Regards, ----------------------------------------------------------------- Xu Qijun Engineer OKI Techno Centre (S) Pte Ltd Tel: 770-7049 Fax: 779-1621 Email: qijun@okigrp.com.sgArticle: 40093
Thanks a lot for your answers! CarstenArticle: 40094
Where can I find detailed description of the FPGA implemetation: 1. AM demodulation (quadrature) 2. Time delay estimation (TDE) by cross-correlation applied on the 100MHz IF (intermediate frequency) signals with PW=1-10us. MichalArticle: 40095
"Falk Brunner" <Falk.Brunner@gmx.de> wrote in news:a5e8n8$6ho3e$5@ID-84877.news.dfncis.de: > "J Kenens" <jo_no_spam_please_.kenens@acunia.com> schrieb im > Newsbeitrag news:Xns91C09903E1CAA556677@195.129.110.141... >> The problem I'am having is the following: >> >> I'm working on a design which uses a cpld to configure the fpga in >> parallel mode. Additinally the cpld and the fpga are configurable true >> jtag. (they are connected in serial, FPGA-TDO connected to CPLD-TDI) >> When I try to configure the Spartan2 and a the cpld true jtag, there's >> no problem. When I replace the Spartan2 by a virtex-E, the Xilinx >> Impact tools do recognize the cpld but the Virtex-E remains invisible. >> When I try to configure the cpld, I get an error. >> Note that the Spartan2 and Virtex-E are almost completely >> pin-compatible > > ??? Are you SURE?? Last time I compared these two families the where > not (at all). Maybe there is a short between VCC and GND, or other > weired missconnection. Just today I found a pinout compare tool on the > Xilinx website. > I'm using the spartan2 200 and a Virtex-E 300.(FG456 package). I did check pin compatibility. The virtex has some pins that are nc on the Spartan.I did not check for IO pins with special features since i'm using all pins as standard io. The Virtex does requires a vccint of 1.8 instead of the 2.5 for the spartan but I'm able to change these voltages so there shouldn't be any problem there. J Kenens > -- > MfG > Falk > > > > >Article: 40096
autogenerate@hotmail.com (Me) wrote in message news:<e4fdc9fb.0202141227.520d646@posting.google.com>... > tamar.poker@mailandnews.com (Tamar Poker) wrote in message news:<f77ba402.0202121007.47ce13c@posting.google.com>... > > Hi. > > I am looking for an excell sheet to do power estimation for virtex2 > > device. > > Unfortunately the excell sheet I found on the web is only for Virtex > > ane Virtex-E (xapp152). > > > > Is there something similiar for Virtex2 ? > > > > Tamar. Yes, there is a Excel sheet for Virtex II device power calculation. If you wish I am glad to send you a copy. Perhaps, you may also get it at hotline@xilinx.com Thanks, Ismail ismailb@ctd.hcltech.comArticle: 40097
> > For FPGAs there is www.fpga-faq.com > I think this site is a wonderful resource as are these newsgroups. The main niche I was trying to target was that of getting various tools to work well and cover their bugs/quirks and optimisations to improve them. There is some information regarding Xilinix-based optimisations on your site but little mention of Altera, no mention of Altera tools and nothing about third-party tools (e.g. Active-HDL overview or effectively using Modelsim). If you are happy to include information on those aspects of FPGA development, I would be happy to contribute to your site instead. Nobody wants a small fragments of information everywhere and your site deserves to be seen by every FPGA designer as there are a lot of useful tips there. Regards Paul BaxterArticle: 40098
X. Q. <qijun@okigrp.com.sg> wrote: : Hi, : I am trying out QuickWorks 9.1. It is all right for me to synthesize and : place & route. But it : seems quite sluggish to me, since it won't finish long after I pressed Save. : I understand that this is an evaluation version. Does anybody have any : comments on Quick : Works 8.22 and the true version of QuickWorks? Is it fast and stable? How : large is the size : of .chp file for a QL3060 bitstream? .chp files are quite large and take their time to store. .lof files are smaller, and store probably a little faster. Consider using newer Quicklogic families, if you can live with smaller voltages. The older PASIC families are slower, smaller and more expensive. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 40099
J Kenens wrote: > The problem I'am having is the following: > > I'm working on a design which uses a cpld to configure the fpga in parallel > mode. Additinally the cpld and the fpga are configurable true jtag. (they > are connected in serial, FPGA-TDO connected to CPLD-TDI) > When I try to configure the Spartan2 and a the cpld true jtag, there's no > problem. > When I replace the Spartan2 by a virtex-E, the Xilinx Impact tools do > recognize the cpld but the Virtex-E remains invisible. When I try to > configure the cpld, I get an error. > Note that the Spartan2 and Virtex-E are almost completely pin-compatible > (the ones that don't match are not used). I can change the applied Vccint > Voltage to 2.5 V for the Spartan2 or 1.8V for the Virtex-E. > > Does anyone have an idea what could be wrong? > Maybe there are some differences between the Spartan2 and the Virtex-E I > didn't noticed? Am I forgetting something else? > > thanks in advance, > Jo Kenens Two things you might check: o are the bank(s) with the JTAG pins are being powered from 3.3V? o the Virtex-E pins are not 5V tolerant but the Spartan2 ones are. IIRC this applies to the JTAG pins as well. Maybe not relevant but ... We had a similar situation where the first device in a chain wasn't being recognised but the second was. In our case the 1st = XC18V04 and the second = XC95144XL. What we had done is to copy the Parallel-III cable logic onto the board but 1. replaced the HC125s with LS125s. 2. Removed the Schottky diode between the 5V power supply and the LS125's VCC pins. `Initialise Chain' was see the CPLD but not the XC18V04. Looking further I could see that nothing was coming out of the XC18V04's JTDO pin [There's an answer in the Xil database that explains how init chain works and shows how this could happen i.e. the end device recognised but the previous one not]. The "fix" was to put the Schottky back in, reducing the LS125's power by all of 0.3V !? The devices were now both recognised but we were getting erratic programming failures. Reverting to HC parts powered from 3.3V seems to have completely "cured" the problem.
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