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Although I have never used the Orca stuff, it looks like you are using a schematic flow, with viewlogic tools (Powerview). My guess is that you are using a schematic to edif netlist writer, and you failed to set the "Level" attribute. The clue is that among the primitives that it is complaining about, is "UDFDL" which I am fairly sure is a Viewsim simulation primitive. This should not be in an implementation netlist. In the "schematic edif netlist writer" window, look for a level attribute, and set it to something like ATT/ORCA/Lucent/Agere/HP Philip Freidin On 14 Feb 2002 14:29:06 -0800, ikumar@cs.utah.edu (Inder) wrote: >I am trying to simulate a controller circuit on ORCA (OR3T00 >architecture) FPGA. >For schematic capture and EDIF file generation I am using Powerview >6.1 tool. >But in the Build operation, which translates and converts the input >EDIF netlist >into ORCA generic database file(*.ngd), I have been getting this >error: > >ERROR - ngdbuild: Could not expand block '....' with TYPE='...' > >and after lot of looking around havent been able to solve the problem. >Can anyone tell me where and what am I doing wrong.. > >There was no error while generating EDIF file with Powerview tool and >I used the >Orca3 library in Powerview. >Here is a relevent part of log file generated by Orca. > > >ORCA Foundry Control Center Log File -- Thursday, February 14, 2002 >14:25 > >---------------------------------------------------------------------- >/usr/local/apps/ORCA/bin/sol/edif2ngd -l or3c00 "abcd.edn" >"/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo" >---------------------------------------------------------------------- >edif2ngd: version ORCA Foundry 2000 Production-w/SP-B (14) >Copyright 1991-1995 by NeoCAD Inc. All rights reserved. > Copyright (c) 1995-2000 Lucent Technologies. All rights >reserved. >WARNING - edif2ngd: Ampersands will be removed from numeric/underscore > identifiers. >WARNING - edif2ngd: GLOBAL property on a net other than power or >ground - > ignoring... > On or above line 113 in file abcd.edn >WARNING - edif2ngd: GLOBAL property on a net other than power or >ground - > ignoring... > On or above line 664 in file abcd.edn >WARNING - edif2ngd: GLOBAL property on a net other than power or >ground - > ignoring... > On or above line 3814 in file abcd.edn >Writing the design to /home/ikumar/3700-pv/orca/abcd_1/abcd.ngo... > >---------------------------------------------------------------------- >/usr/local/apps/ORCA/bin/sol/ngdbuild -a or3t00 -p >"/home/ikumar/3700-pv/orca/sch" -p "/home/ikumar/3700-pv/orca" >"/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo" "abcd_1/abcd_1.ngd" >---------------------------------------------------------------------- >ngdbuild: version ORCA Foundry 2000 Production-w/SP-B (14) >Copyright 1991-1995 by NeoCAD Inc. All rights reserved. > Copyright (c) 1995-2000 Lucent Technologies. All rights >reserved. >Reading '/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo' ... >Loading NGL library '/usr/local/apps/ORCA/or3c00/data/orc3clib.ngl'... >Loading NGL library '/usr/local/apps/ORCA/data/neoprims.ngl'... >Loading NGL library '/usr/local/apps/ORCA/data/neomacro.ngl'... >Loading device for application ngdbuild from file 'or3t12x12.nph' in > environment /usr/local/apps/ORCA. >Loading macro from file "/home/ikumar/3700-pv/orca/sch/all4_3lut.nmc". >Loading macro from file >"/home/ikumar/3700-pv/orca/sch/bottom2_3lut.nmc". >Loading macro from file "/home/ikumar/3700-pv/orca/sch/top3_3lut.nmc". >Loading macro from file >"/home/ikumar/3700-pv/orca/sch/bottom3_3lut.nmc". >ERROR - ngdbuild: Could not expand block '$1I53106/$1I9' with >TYPE='BUF' >ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST998' with > TYPE='UDFDL' >ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST995' with > TYPE='PW' >ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST6' with > TYPE='UDFDL' >ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST34' with > TYPE='NOT' >ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST27/$1I9' with > TYPE='BUF' >ERROR - ngdbuild: Could not expand block '$1I99402/INST1' with >TYPE='NOT' >ERROR - ngdbuild: Could not expand block '$1I99428/INST1' with >TYPE='AND3' >ERROR - ngdbuild: Could not expand block '$1I99428/BFI3' with >TYPE='BUF' >ERROR - ngdbuild: Could not expand block '$1I99428/BFI2' with >TYPE='BUF' > is unexpanded > >********* around 10000 such errors ************ > >WARNING - ngdbuild: logical net 'DPRAM08-11/DO2' has no driver >WARNING - ngdbuild: logical net 'DPRAM08-11/DO3' has no driver >WARNING - ngdbuild: logical net 'DPRAM12-15/A0' has no driver >WARNING - ngdbuild: logical net 'DPRAM12-15/A1' has no driver >WARNING - ngdbuild: logical net 'DPRAM12-15/A2' has no driver >. >. >. > >WARNING - ngdbuild: logical net 'TP3' has no driver >WARNING - ngdbuild: logical net 'TP3' has no load >WARNING - ngdbuild: logical net 'TP4' has no driver >WARNING - ngdbuild: logical net 'TP4' has no load >WARNING - ngdbuild: logical net 'TP5' has no driver >WARNING - ngdbuild: logical net 'TP5' has no load >WARNING - ngdbuild: logical net 'TP6' has no driver >WARNING - ngdbuild: logical net 'TP6' has no load >WARNING - ngdbuild: logical net 'TP7' has no driver >WARNING - ngdbuild: logical net 'TP7' has no load >ERROR - ngdbuild: DRC failed with 9865 errors and 492 warnings > >Design Results: > 19 blocks expanded >Writing 'abcd_1/abcd_1.ngd' ... Philip Freidin FliptronicsArticle: 39651
Just curiosity, but why does Modelsim have a Rhinoceros in it's logo?Article: 39652
This is a multi-part message in MIME format. --------------0098745D3A03F09C382749D5 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Have you verified that the PROG_B line is not being held low? This will cause the 2V6000's TAP to reset itself continuously breaking the chain. Dave shparekh@yahoo.com wrote: > Hi All, > > Your wisdom, 2 cents, etc. will be much appreciated. > > I have a jtag chain with 5 xc18v04 plcc and a Virtex 2 XC2V6000 BF957. > I use "Initialize Chain" in Xilinx's IMPACT. Unfortunately, I cannot > readback anything. Apparently, with much probing and isolating the > proms and the fpga from the jtag chain, I see that IMPACT can readback > IDCODES and get chain information from the eeproms, but cannot get > anything out of the fpga. > > I am not sure why this happens. I probed all the signals on jtag > chain going to the fpga and do not see any difference between the > signal quality on the eproms and the fpga. > > I would appreciate your feedback. > > Thank you. > -sanjayArticle: 39654
If you ran it all the way through the tools again, there will be differences due
to a different place and route solution. I've programmed XCV50's with an XC2S50
bitstream and vice-versa.
"X. Q." wrote:
> I suspect it was because in the download board they used a Vertex family.
> while in the daughter board I put in a Spartan-II chip and daughter board.
> I tried to synthesize with spartan-ii chip and program the device, it
> displayed
> 200,123 differences. Could anybody know how to tackle these differneces?
>
> --
> Best Regards,
> Qijun.
>
> ********************************************************************
> Xu Qijun
> Design Engineer, RFIC Group
> OKI Techno Centre (S) Pte Ltd
> 20 Science Park Rd, #02-06/10
> Teletech Park,Science Park II,
> Singapore 117674
> DID: 7707049 Fax: 7792382
> "Kevin Brace" <ihatespamkevinbraceusenet@ihatespamhotmail.com> wrote in
> message news:a4ht0v$la0$1@newsreader.mailgate.org...
> > Nope.
> > Because some people may disagree with me, I checked both datasheets.
> > Also see Xilinx Application Note 138 and 176.
> > That should confirm what I wrote.
> > I am pretty sure that I read somewhere that Xilinx doesn't
> > guarantee both bitstreams to be 100% compatible, but I forgot where I
> > read that.
> > Peter Alfke (I haven't seen him for a week or so.) may know more about
> > that issue.
> >
> >
> >
> > Kevin Brace (Don't respond to me directly, respond within the
> > newsgroup.)
> >
> >
> >
> > "X. Q." wrote:
> > >
> > > The diference may come because you create them at different time,
> > > the Time and Device Type in the bit file makes up the difference in file
> > > size.
> > >
> > > --
> > > Best Regards,
> > > Qijun.
> > >
> > > ********************************************************************
> > > Xu Qijun
> > > Design Engineer, RFIC Group
> > > OKI Techno Centre (S) Pte Ltd
> > > 20 Science Park Rd, #02-06/10
> > > Teletech Park,Science Park II,
> > > Singapore 117674
> > > DID: 7707049 Fax: 7792382
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39655
In article <a4injb$t8o$1@rdel.co.uk>, Jock <ian.mcneil@uk.thalesgroup.co
m> writes
>Just curiosity, but why does Modelsim have a Rhinoceros in it's logo?
Might be something to do with the Mentor CEO's name :-)
--
Jonathan Bromley
DOULOS Ltd.
Church Hatch, 22 Market Place, Ringwood, Hampshire BH24 1AW, United Kingdom
Tel: +44 1425 471223 Email: jonathan.bromley@doulos.com
Fax: +44 1425 471573 Web: http://www.doulos.com
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Article: 39656
You may have trouble with your flags operating it with a gated clock. The
fifo is not designed for gated clocks. The correct way of dealing with the
long setup for the enable and we pins is to modify the address counts
according to the push and pop signals. A FIFO works well with it: you
don't advance the write pointer unless the write data is good. It doesn't
matter if you write garbage to the memory at the write pointer location for
unqualified data, as long as you don't advance the pointer, therefore you
can leave the WE and ENA pins active all the time. On the read side, you
only advance the read pointer for a pop. Again, you can leave the ENA
active full time. Unfortunately (at least last time I checked), the Xilinx
macros use the WE and ENA pins, so it means designing your own.
G wrote:
> Howdy,
>
> Bob Perlman <no-spam@sonic.net> wrote:
> > The problems with using clock pulses or gated clocks have been pretty
> > much beaten to death in this newsgroup, so I won't belabor the point.
>
> Do you mean _asynchronous_ clock pulses/gated clocks here? I was
> just about to rewrite a section of my design to only generate clocks
> to the coregen FIFO when necessary, keeping the enable active.
>
> My current problem is the enable line to the BlockRAMs in the FIFO
> is the critical path. If I can generate pulses only when I need them,
> then I can run the system a little faster.
>
> The idea is to use a FF to divide the main clock by two. This would
> then become the FIFO read clock. I would limit the pulses by using
> the clock enable on that FF. If I can constrain the path from the
> rising/falling edge of the main clock through the FF, through the FIFO,
> and to the inputs of a set of FF's, then I don't immediately see
> where the problems lie.
>
> Thanks,
> G
>
> P.S. Sorry about the email address. I have 'misplaced' the slip of
> paper with my Yahoo Email password.. :(
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39657
Utku Ozcan wrote:
> Ray Andraka wrote:
>
> > I've found 4.1 to be just about useless for anything other than VirtexII designs. [snip]
>
> This "result" proves our opinion which claims that newest version of Xilinx tools
> only improves newest Xilinx devices.
>
> So probably a v5.1i, a next major release will be optimized for a new Xilinx device
> coming in, for a Xilinx counterpart of Altera's Stratix maybe?
I think they are going to call that counter part "VirtexII" ;-0
>
>
> Utku
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39658Targetting something at a SpartanII in Webpack 4.1WP3.x I am told that The register symbol m2_shiftin_<xx> has the property IOB=TRUE, but failed to join an I/O component. Please try constraining the register together with a valid pad or I/O buffer symbol. where xx covers all the bits of a shift register which in turn is fed by a single bit input. What exactly is it trying to tell me ? Cheers, JonArticle: 39659
Hello I want to access a synchronous RAM via a state machine for reading and writing. With a positive edge the address and the DataIn are registered to the Ram. Can I activate the WriteEnable Pin after the pos clock edge, to write the Data into the Ram, or must the WE be activated before the edge of the Clock. Ciao, JensArticle: 39660
The WE is sampled by the clock in the Altera and Xilinx devices I'm familiar with. You should find setup and hold times specified for WE in the timing numbers for any FPGA with memory elements which requires a sampled WE. Jens Niemann wrote: > Hello > I want to access a synchronous RAM via a state machine for reading and > writing. > With a positive edge the address and the DataIn are registered to the Ram. > Can I activate the WriteEnable Pin after the pos clock edge, to write the > Data into the Ram, or must the WE be activated before the edge of the Clock. > > Ciao, > JensArticle: 39661
I'm not answering all your questions here, just making a comment from my own experience. When simulating a SpartanII device, the Verilog simulation library had a couple elements that I had to go back into the post-layout generated Verilog file and substitute in my own "version" of the device. One of those was the SRL16E because my simulator was doing its transitions *within the primitive* at time t+0ps but the primitive was "requiring" a finite delay (#1 minimum). It wasn't a factor of external timing parameters but timing within the simulation primitive. Mostly my troubles arose from propagation of "x" states from the bogus error. Perhaps you're having a similar problem? Antonio wrote: > I've symply do the following : > use different configuration of core generator single port blockram > read only of dimension > 12x4096 and working on rising edge of the clock, at the address input > I apply a counter that > produce a different address at every clock cycle and a FFD to change > rapidly from rising to > falling edge, my expectation is to have a new output value at every > clock cycle, > but this are the result : > > 1) only registered output -> a result every 2 clock cycles > 2) unregistered input and output -> a result every 2 clock cycles if > the address change on rising > edge otherwise if change on falling edge I've no output and a lot > of : > # : WARNING: */RAMB4_S1 SETUP Low VIOLATION ON ADDR(0) WITH RESPECT > TO CLK; > # : Expected := 0.01 ns; Observed := 0 ns; At : 1250 ns > > 3) only registered input -> no output regardless on the fact that > address change on rising or on falling edgeArticle: 39662
This is a multi-part message in MIME format. --------------8E58F6898667C6040E2E17B3 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Jon, It is possible to make a shifter using the IO registers but is that what you want? If the synthesizer has placed the property on all bits of the shifter, then it is a bug. I would advise turning this feature off, and using the MAP -pr b command to achieve the same thing. Dave Jon Schneider wrote: > Targetting something at a SpartanII in Webpack 4.1WP3.x I am told that > > The register symbol m2_shiftin_<xx> has the property IOB=TRUE, > but failed to join an I/O component. Please try constraining the > register > together with a valid pad or I/O buffer symbol. > > where xx covers all the bits of a shift register which in turn is fed by > a single bit input. What exactly is it trying to tell me ? > > Cheers, > > JonArticle: 39663
Hi, I have no experience using FPGA. I have to choose some family, from Altera or Xilinx. I suppose both should have a family that suits my needs, but I need some advice considering what I have to do: - I have to do a PCB w/FPGA logic. Main requirement is to include in-system reconfiguration, I mean, to change code loaded in FPGA without desoldering the device. I have learned that a configuration PROM is in charge of this, or even a JTAG interface. Is it correct? Do I need a CPU to control FPGA as well? - I have worked with Texas' DSPs boards before. In that, I load programs and debug the application with JTAG interface. I understand Virtex devices have the same interface. Is software provided by these people similar in this way to DSP's software? Is it possible to write a program and inmediately load it in FPGA? - Which family should be best choice considering I have to design a PCB w/reconfiguration capability? - I'm thinking in buying a demo board to achieve experience w/FPGA programming, which one is convenient, considering I have to implement a PCB ? Is it a good choice to think in a demo board or it's better to study and design the PCB right now? Thanks in advance. -Dani-Article: 39664
There are variable amounts of don't care bits in the bitstream that account for slight variations in counting the total bitstream length. The Spartan-II data sheet has been updated a couple times since the 3/3/2000 version, with the current one from March 2001 indicating the same bitstream length as the XCV100: 781,216, which is the current bitstream length created by the Xilinx development system. Bitstreams created for one family may work in another, but Xilinx does not test the parts that way and cannot guarantee that they will work. We strongly recommend creating the bitstream for the target device. The Spartan-II and Virtex families share the same JTAG family ID code, as do the Spartan-IIE and Virtex-E families. The software ignores any variations in revision, so it cannot differentiate between Virtex and Spartan devices of the same CLB matrix. Kevin Brace wrote: > That is not true. > According to Virtex datasheet dated 1/28/2000, the configuration bit > length for XCV100 is 781,216. > However, according to Spartan-II datasheet dated 3/3/2000, the > configuration bit length for XC2S100 is 781,248. > > Kevin Brace (Don't respond to me directly, respond within the > newsgroup.) > > Ray Andraka wrote: > > > > The bitstreams for virtex and spartanII for same size device are the same. > > > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759 -- Marc Baker Xilinx Applications (408) 879-5375Article: 39665
hi one my friends told me that if i use the output of an inv to feed its input, A DANGER of *oscillation* could happen. is that right even for LUT based on SRAM.what about a simple buffer. say also i have a 3 ports "and", one of its inputs will be the output of that port, is there any risk of oscillation? thanks -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 39666
Dani Guzman wrote: > > Hi, > I have no experience using FPGA. I have to choose some family, from > Altera or Xilinx. I suppose both should have a family that suits my > needs, but I need some advice considering what I have to do: > > - I have to do a PCB w/FPGA logic. Main requirement is to include > in-system reconfiguration, I mean, to change code loaded in FPGA > without desoldering the device. I have learned that a configuration > PROM is in charge of this, or even a JTAG interface. Is it correct? Do > I need a CPU to control FPGA as well? First, let me say that in terms of configuration, there is very little real difference between the two vendors you mention. You can use a (EE)PROM to configure the FPGA or you can use a micro. But JTAG is not a viable option for normal operation of your board. JTAG is used during debug to save the trouble of downloading designs to the (EE)PROM or to what ever storage your micro is using. One question you need to answer is when/how do you plan to do the updates? Will your board be connected to a PC which can download the updates? Do you want to plug in a small memory module to update the download? Will there be a remote comms connection of some kind? This is the first question you need to answer. > - I have worked with Texas' DSPs boards before. In that, I load > programs and debug the application with JTAG interface. I understand > Virtex devices have the same interface. Is software provided by these > people similar in this way to DSP's software? Is it possible to write > a program and inmediately load it in FPGA? Yes, JTAG works about the same with an FPGA as it does with the DSP. I have not used JTAG to download FPGAs before, but the process is not complex. The development software has an option of preparing a JTAG format output file. I believe the vendors offer a PC compatible cable to connect to your target board. > - Which family should be best choice considering I have to design a > PCB w/reconfiguration capability? I don't think you will find much difference between the different vendors or families. I do know that you could use a standard EPROM with the older Xilinx parts, but is not supported with the newer parts. But that was a bit of a kludge requiring a large number of address lines in addition to the data bus. > - I'm thinking in buying a demo board to achieve experience w/FPGA > programming, which one is convenient, considering I have to implement > a PCB ? Is it a good choice to think in a demo board or it's better to > study and design the PCB right now? I can't recommend a demo board vendor. But there are many out there. If you really want to use the JTAG method, find one that works with JTAG. I recommend that you skip the demo board and use the bit serial slave mode or the byte wide parallel slave mode on your own board. I find these two to be the easiest configuration modes when used with a micro processor. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39667
David Hawke wrote: > > It is possible to make a shifter using the IO registers but is that what you > want? If the synthesizer has placed the property on all bits of the shifter, > then it is a bug. No I'm not trying to do anything funny at all. I also stuffed the design through Leonardo Spectrum targetted to EPF10K10 and that was fine. What warnings it did come up with were actually useful. JonArticle: 39668
Jon, As David said, the synthesis tools has put IOB=TRUE constraints on the registers which directs Map to pack them into IOB components. The warning message in map is to let you know that the constraint could not be followed either due to connectivity conflicts or other constraints. This means that the registers were packed into slice components instead. You can safely ignore the message unless you actually do want them packed into IOBs. Regards, Bret Jon Schneider wrote: > Targetting something at a SpartanII in Webpack 4.1WP3.x I am told that > > The register symbol m2_shiftin_<xx> has the property IOB=TRUE, > but failed to join an I/O component. Please try constraining the > register > together with a valid pad or I/O buffer symbol. > > where xx covers all the bits of a shift register which in turn is fed by > a single bit input. What exactly is it trying to tell me ? > > Cheers, > > JonArticle: 39669
Leon de Boer wrote:
> Leonardo Spectrum
> Never picks RAM/ROM blocks unless you specify it
Uses block ram fine, if your code matches
the block ram template.
> Has the most bugged and erratic synthesis of the 3
I haven't experienced any synthesis problems in versions 1999-2001.
> Puts up far to much minor warnings on screen that means you wade through
> piles of crap.
Warnings do not stop synthesis, you can ignore them all if you like.
Most of the warnings are valid, and they have helped me improve my code.
-- Mike Treseler
Article: 39670
Connecting the output of an inverter back to the input results in an
oscillator no matter what the technology. Think about hwat happens. Say it
starts up with '0' at its output. That '0' value will go into the input, be
inverted making the output drive a '1'. The '1' then causes the output to
drive a zero and the cycle repeats. This is known as a ring oscillator. It
will oscillate at a frequency determined by the delay through the inverter
and the feed back path. It oscillates because there is no stable state.
Now, if your feedback instead made it land in a stable state, then you'd get
no oscillation. A cross-coupled set of NAND gates is a good example of
that. In that case, the feedback is through a second inverter so there is a
stable state. The second input on each NAND gate serve as a set and reset
for the circuit so that you can control the state you are driving it to.
Hristo Stevic wrote:
> hi
> one my friends told me that if i use the output of an inv to feed its
> input, A DANGER of *oscillation* could happen. is that right even for
> LUT based on SRAM.what about a simple buffer.
>
> say also i have a 3 ports "and", one of its inputs will be the output of
> that port, is there any risk of oscillation?
>
> thanks
>
> --
> Posted via Mailgate.ORG Server - http://www.Mailgate.ORG
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 39671"Ray Andraka" <ray@andraka.com> schrieb im Newsbeitrag news:3C6C2084.EA7C7C7F@andraka.com... > I should probably cut and paste this into the FAQ, huh? Remember all those coding style guides? How was this about Reuse . . .?? ;-) -- MfG FalkArticle: 39672
"jetmarc" <jetmarc@hotmail.com> schrieb im Newsbeitrag news:af3f5bb5.0202141341.4d0bfbcb@posting.google.com... > Hi. > > For a project I like to invent and implement a lean (co)processor that handles > serial protocols (such as SPI, I2C, UART, etc). It should be software Uuuups, havent we meet before in another newsgroup?? ;-)) So you know my comments. -- MfG FalkArticle: 39673
Bret Wade wrote: > > As David said, the synthesis tools has put IOB=TRUE constraints on the > registers which directs Map to pack them into IOB components. But why has it done that ? JonArticle: 39674
"Eric Smith" <eric-no-spam-for-me@brouhaha.com> schrieb im Newsbeitrag news:qheljn33wc.fsf@ruckus.brouhaha.com... > "Paul Taylor" <p.taylor@ukonline.co.uk> writes: > > It seems strange to me for Xilinx to not bother supporting XL in this latest > > software, especially if they can't offer a free alternative for XL with > > VHDL?! > > That's because they aren't interested in selling the Spartan and Spartan > XL to new customers. It's now considered a legacy part. They're happy > to keep selling the chips to existing customers, but they want you > to buy the Spartan II or Spartan IIE for new designs. Yes, and why not? Have a look at the prices www.nuhorizons.com there you will see that Spartan is INCREDIBLE expensive, compared to SpartanXL. But even XL is way more expensive than Spartan-II. There are not much reasons for using Spartan(XL). I can just think of 2 -- You want to do a real low power design, here Spartan(XL) is better, because of lower leakage -- You can/want do a workaround for the power-on surge of Spartan-II On all other issues, Spartan-II is the far better choice. -- MfG Falk
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