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maybe use Risc5x at opencores.org as a starting point ? Mike "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3C6C37E6.6F8D@designtools.co.nz... > jetmarc wrote: > > > > Hi. > > > > For a project I like to invent and implement a lean (co)processor that handles > > serial protocols (such as SPI, I2C, UART, etc). It should be software > > programmable like a processor, so that new protocols can be added without > > changes to the VHDL source / bitstream. On the other hand, it should be > > almost as lean and light weight as a simple state machine. I plan to fit > > several such processors (in parallel) into a small 50K gate FPGA. > > > > I'm not sure yet about the optimum instruction set, nor about the other > > characteristics of such a processor. I think about a structure where the > > PC addresses 64 instructions, and all instructions operate on bits (not bytes). > > The bits include 8 I/O pins, a byte-buffer register (possibly only MSB > > and LSB addressable), handshake lines from/to the host, and two temp bits. > > > > My idea is to have two parallel processors per serial channel, one for TX > > and one for RX. The instruction set of them can be biased towards the data > > direction (TX processor can read from byte-buffer and write to I/O pin, while > > RX processor reads from I/O pin and writes to byte-buffer). > > > > What do you think about this? Is there any code or other work available that > > might serve as inspiration for nailing down a good and practical instruction > > set? > > > > Marc > > Interesting idea. > Scenix(ubicom) use a PIC 12 bit opcode variant core, and a Soft > peripheral. > > You could also look at Bit-Slice processors - I have seen a number on > the WEB. > > You could see if a subset-opcode of the PIC12 could be used, as even > that small > opcode has more 'reach' than you need - and then you can use the PIC or > SX core > tools and even silicon, as test vechicle. > > A simple 12 Bit Opcode -> Smaller Converter/error catcher pgm, would > take any > PIC file, and ready it for your FPGA engine. > > Code the tasks first, then see what subset of opcode and RAM coverage > was needed, and use that subset for your 'state engine'. > > Some BYTE operations could be usefull for loop counters, and FIFO > construction, > and MACRO blocks can always be used if the PIC opcodes do not map well > to this. > ( here two/three/four... opcodes would map onto one of your new opcodes > ) > eg PIC uses a skip/jump construct, but more efficent is a short jump > opcode > as seen in COP8, and Fairchild ACE1101 > > > IIRC, Philips also had some sort of communications engine chip, that > made it to data > a while ago, using a similar idea of a fast, state engine like core for > data > packet pumping ( tho this used underlying silicon as well ) > > -jgArticle: 39626
I am trying to simulate a controller circuit on ORCA (OR3T00
architecture) FPGA.
For schematic capture and EDIF file generation I am using Powerview
6.1 tool.
But in the Build operation, which translates and converts the input
EDIF netlist
into ORCA generic database file(*.ngd), I have been getting this
error:
ERROR - ngdbuild: Could not expand block '....' with TYPE='...'
and after lot of looking around havent been able to solve the problem.
Can anyone tell me where and what am I doing wrong..
There was no error while generating EDIF file with Powerview tool and
I used the
Orca3 library in Powerview.
Here is a relevent part of log file generated by Orca.
ORCA Foundry Control Center Log File -- Thursday, February 14, 2002
14:25
----------------------------------------------------------------------
/usr/local/apps/ORCA/bin/sol/edif2ngd -l or3c00 "abcd.edn"
"/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo"
----------------------------------------------------------------------
edif2ngd: version ORCA Foundry 2000 Production-w/SP-B (14)
Copyright 1991-1995 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995-2000 Lucent Technologies. All rights
reserved.
WARNING - edif2ngd: Ampersands will be removed from numeric/underscore
identifiers.
WARNING - edif2ngd: GLOBAL property on a net other than power or
ground -
ignoring...
On or above line 113 in file abcd.edn
WARNING - edif2ngd: GLOBAL property on a net other than power or
ground -
ignoring...
On or above line 664 in file abcd.edn
WARNING - edif2ngd: GLOBAL property on a net other than power or
ground -
ignoring...
On or above line 3814 in file abcd.edn
Writing the design to /home/ikumar/3700-pv/orca/abcd_1/abcd.ngo...
----------------------------------------------------------------------
/usr/local/apps/ORCA/bin/sol/ngdbuild -a or3t00 -p
"/home/ikumar/3700-pv/orca/sch" -p "/home/ikumar/3700-pv/orca"
"/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo" "abcd_1/abcd_1.ngd"
----------------------------------------------------------------------
ngdbuild: version ORCA Foundry 2000 Production-w/SP-B (14)
Copyright 1991-1995 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995-2000 Lucent Technologies. All rights
reserved.
Reading '/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo' ...
Loading NGL library '/usr/local/apps/ORCA/or3c00/data/orc3clib.ngl'...
Loading NGL library '/usr/local/apps/ORCA/data/neoprims.ngl'...
Loading NGL library '/usr/local/apps/ORCA/data/neomacro.ngl'...
Loading device for application ngdbuild from file 'or3t12x12.nph' in
environment /usr/local/apps/ORCA.
Loading macro from file "/home/ikumar/3700-pv/orca/sch/all4_3lut.nmc".
Loading macro from file
"/home/ikumar/3700-pv/orca/sch/bottom2_3lut.nmc".
Loading macro from file "/home/ikumar/3700-pv/orca/sch/top3_3lut.nmc".
Loading macro from file
"/home/ikumar/3700-pv/orca/sch/bottom3_3lut.nmc".
ERROR - ngdbuild: Could not expand block '$1I53106/$1I9' with
TYPE='BUF'
ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST998' with
TYPE='UDFDL'
ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST995' with
TYPE='PW'
ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST6' with
TYPE='UDFDL'
ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST34' with
TYPE='NOT'
ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST27/$1I9' with
TYPE='BUF'
ERROR - ngdbuild: Could not expand block '$1I99402/INST1' with
TYPE='NOT'
ERROR - ngdbuild: Could not expand block '$1I99428/INST1' with
TYPE='AND3'
ERROR - ngdbuild: Could not expand block '$1I99428/BFI3' with
TYPE='BUF'
ERROR - ngdbuild: Could not expand block '$1I99428/BFI2' with
TYPE='BUF'
is unexpanded
********* around 10000 such errors ************
WARNING - ngdbuild: logical net 'DPRAM08-11/DO2' has no driver
WARNING - ngdbuild: logical net 'DPRAM08-11/DO3' has no driver
WARNING - ngdbuild: logical net 'DPRAM12-15/A0' has no driver
WARNING - ngdbuild: logical net 'DPRAM12-15/A1' has no driver
WARNING - ngdbuild: logical net 'DPRAM12-15/A2' has no driver
.
.
.
WARNING - ngdbuild: logical net 'TP3' has no driver
WARNING - ngdbuild: logical net 'TP3' has no load
WARNING - ngdbuild: logical net 'TP4' has no driver
WARNING - ngdbuild: logical net 'TP4' has no load
WARNING - ngdbuild: logical net 'TP5' has no driver
WARNING - ngdbuild: logical net 'TP5' has no load
WARNING - ngdbuild: logical net 'TP6' has no driver
WARNING - ngdbuild: logical net 'TP6' has no load
WARNING - ngdbuild: logical net 'TP7' has no driver
WARNING - ngdbuild: logical net 'TP7' has no load
ERROR - ngdbuild: DRC failed with 9865 errors and 492 warnings
Design Results:
19 blocks expanded
Writing 'abcd_1/abcd_1.ngd' ...
Article: 39627Modelsim XE is able to do everything that Modelsim PE can (according to Xilinx). I have used both. The XE version can be used without ISE software. You can use Modelsim XE, for example, for compiling Foundation VHDL libraries and then using them (Simprim, Unisim, Coregen, etc.). While slower then PE/SE, Modelsim XE will be able to perform pre-PAR simulation for you. However... if you want to do a post PAR functional (and possibly include the timing information) simulation then you are in for a treat. I attempted to use Modelsim XE for simulating post PAR 60% utilized Spartan-II-200. All I can say is there is a better way to spend my time. The simulation was taking forever without any timing info. If I new ahead of time that ModelSim XE would be such a poor piece of software I would never have advised my emploer to purchase it. I guess you get what you pay for stands ($900 can not buy you a desent simulator).Article: 39628
Maybe you should have a look at KCPSM from Xilinx. http://www.xilinx.com/xapp/xapp213.pdf G=F6ran Bilski "Mike Johnson > maybe use Risc5x at opencores.org as a starting point ? > Mike > "Jim Granville" <jim.granville@designtools.co.nz> wrote in message > news:3C6C37E6.6F8D@designtools.co.nz... > > jetmarc wrote: > > > > > > Hi. > > > > > > For a project I like to invent and implement a lean (co)processor t= hat > handles > > > serial protocols (such as SPI, I2C, UART, etc). It should be softw= are > > > programmable like a processor, so that new protocols can be added > without > > > changes to the VHDL source / bitstream. On the other hand, it shou= ld be > > > almost as lean and light weight as a simple state machine. I plan = to > fit > > > several such processors (in parallel) into a small 50K gate FPGA. > > > > > > I'm not sure yet about the optimum instruction set, nor about the o= ther > > > characteristics of such a processor. I think about a structure whe= re > the > > > PC addresses 64 instructions, and all instructions operate on bits = (not > bytes). > > > The bits include 8 I/O pins, a byte-buffer register (possibly only = MSB > > > and LSB addressable), handshake lines from/to the host, and two tem= p > bits. > > > > > > My idea is to have two parallel processors per serial channel, one = for > TX > > > and one for RX. The instruction set of them can be biased towards = the > data > > > direction (TX processor can read from byte-buffer and write to I/O = pin, > while > > > RX processor reads from I/O pin and writes to byte-buffer). > > > > > > What do you think about this? Is there any code or other work avai= lable > that > > > might serve as inspiration for nailing down a good and practical > instruction > > > set? > > > > > > Marc > > > > Interesting idea. > > Scenix(ubicom) use a PIC 12 bit opcode variant core, and a Soft > > peripheral. > > > > You could also look at Bit-Slice processors - I have seen a number on= > > the WEB. > > > > You could see if a subset-opcode of the PIC12 could be used, as even > > that small > > opcode has more 'reach' than you need - and then you can use the PIC = or > > SX core > > tools and even silicon, as test vechicle. > > > > A simple 12 Bit Opcode -> Smaller Converter/error catcher pgm, would > > take any > > PIC file, and ready it for your FPGA engine. > > > > Code the tasks first, then see what subset of opcode and RAM coverage= > > was needed, and use that subset for your 'state engine'. > > > > Some BYTE operations could be usefull for loop counters, and FIFO > > construction, > > and MACRO blocks can always be used if the PIC opcodes do not map wel= l > > to this. > > ( here two/three/four... opcodes would map onto one of your new opcod= es > > ) > > eg PIC uses a skip/jump construct, but more efficent is a short jump > > opcode > > as seen in COP8, and Fairchild ACE1101 > > > > > > IIRC, Philips also had some sort of communications engine chip, that > > made it to data > > a while ago, using a similar idea of a fast, state engine like core f= or > > data > > packet pumping ( tho this used underlying silicon as well ) > > > > -jgArticle: 39629
"Aaron Eberhart" <aaron.eberhart@mx.iff.navy.mil> wrote in message
news:ee74db4.-1@WebX.sUN8CHnE...
> I have been provided with a schematics based project as well as an HDL based
project, each of which were previously successfully implemented. I am tasked
with re-implementing the project to a new working chip. So far, attempts at
recreating the projects in Foundations 3.1 (for the schematics project) and
ISE4.1 (for the HDL project) have failed. I have been able to recreate the HEX
prom files from the provided bit strems and load these into the system active.
However I have been unable to go from the code or schematic level to working HEX
files. My new thought is to try creating a bit stream from the provided NCD
files which would put me on track to figure out what implementation options were
in use. Any ideas on how to go directly from an NCD to a BIT file for
implementation?
>
From a makefile (the comments come from files in the xilinx
directories, such as bitgen.usg):
dn=foobar
# bitgen generates a programming file, options:
# Usage: bitgen [-d] [-j] [-b] [-w] [-l] [-m] [-t] [-n] [-u] [-a] {-g
# <setting_value>} <infile[.ncd]> [<outfile>] [<pcffile[.pcf]>]
# Where:
# -d = Don't Run DRC (Design Rules Checker)
# -j = Don't create bit file
# -b = Create rawbits file
# -w = Overwrite existing output file
# -f <cmdfile> = Read command line arguments from file <cmdfile>
# -g <opt:val> = Set option to value, options are (1st is default):
#
# commands in bitgen.ut as follows:
# -g ConfigRate 4
# -g StartupClk Cclk
# -g CclkPin Pullup
# -g DonePin Pullup
# -g M0Pin Pullup
# -g M1Pin Pullup
# -g M2Pin Pullup
# -g ProgPin Pullup
# -g TckPin Pullup
# -g TdiPin Pullup
# -g TdoPin Pullup
# -g TmsPin Pullup
# -g DONE_cycle 3
# -g GSR_cycle Done
# -g GWE_cycle Done
# -g GTS_cycle Done
# -g LCK_cycle NoWait
# -g Persist No
# -g DriveDone Yes
# -g DonePipe Yes
#
# promgen options:
# -b Disable bit swapping. Only valid for hex format (-p hex).
#
# -s <size> PROM size in K bytes (must be power of 2), multiple sizes imply
# splitting the bitstream(s) into multiple PROMs.
#
# -x <xilinx_prom>
# Specific Xilinx PROM, multiple PROMs imply splitting the
# bitstream(s) into multiple PROMs.
#
# -p <format> PROM format (mcs, exo, hex, or tek)
#
# -o <file> Output PROM file name (default matches first .bit file),
# multiple names may be specified when splitting PROMs.
#
# -u <hexaddr> <file[.bit]> {<file[.bit]>}
# Load .bit file(s) up from address. Multiple .bit files are
# daisychained to form a single PROM load.
#
# -d <hexaddr> <file[.bit]> {<file[.bit]>}
# Load .bit file(s) down from address. Multiple .bit files are
# daisychained to form a single PROM load.
#
# -n <file[.bit]> {<file[.bit]>}
# Load .bit file(s) up or down starting from the next address
# following previous load. Multiple .bit files are daisychained
# to form a single PROM load. Must follow a -u, -d, or -n option.
#
# -r <promfile>
# Load the PROM file. The -r and the -u, -d and -n options are
# mutually exclusive.
#
# -f <cmdfile>
# Read command line arguments from file <cmdfile>.
#
#At least one -r, -u, or -d option must appear in the command line.
$(dn).bit : $(dn).ncd bitgen.ut
bitgen $(dn).ncd -w -f bitgen.ut
promgen -p hex -s 512 -o $(dn).hex -u 0 $(dn).bit
Article: 39630"Paul Taylor" <p.taylor@ukonline.co.uk> writes: > It seems strange to me for Xilinx to not bother supporting XL in this latest > software, especially if they can't offer a free alternative for XL with > VHDL?! That's because they aren't interested in selling the Spartan and Spartan XL to new customers. It's now considered a legacy part. They're happy to keep selling the chips to existing customers, but they want you to buy the Spartan II or Spartan IIE for new designs. Of course, you certainly *can* use the Spartan and Spartan XL for new designs; just don't expect as much encouragement (e.g., free tools) out of Xilinx if you do that.Article: 39631
That is not true. According to Virtex datasheet dated 1/28/2000, the configuration bit length for XCV100 is 781,216. However, according to Spartan-II datasheet dated 3/3/2000, the configuration bit length for XC2S100 is 781,248. Kevin Brace (Don't respond to me directly, respond within the newsgroup.) Ray Andraka wrote: > > The bitstreams for virtex and spartanII for same size device are the same. > > > -- > --Ray Andraka, P.E. > President, the Andraka Consulting Group, Inc. > 401/884-7930 Fax 401/884-7950 > email ray@andraka.com > http://www.andraka.com > > "They that give up essential liberty to obtain a little > temporary safety deserve neither liberty nor safety." > -Benjamin Franklin, 1759Article: 39632
The diference may come because you create them at different time, the Time and Device Type in the bit file makes up the difference in file size. -- Best Regards, Qijun. ******************************************************************** Xu Qijun Design Engineer, RFIC Group OKI Techno Centre (S) Pte Ltd 20 Science Park Rd, #02-06/10 Teletech Park,Science Park II, Singapore 117674 DID: 7707049 Fax: 7792382 "Kevin Brace" <ihatespamkevinbraceusenet@ihatespamhotmail.com> wrote in message news:a4hq5d$l33$1@newsreader.mailgate.org... > That is not true. > According to Virtex datasheet dated 1/28/2000, the configuration bit > length for XCV100 is 781,216. > However, according to Spartan-II datasheet dated 3/3/2000, the > configuration bit length for XC2S100 is 781,248. > > > > > Kevin Brace (Don't respond to me directly, respond within the > newsgroup.) > > > > > Ray Andraka wrote: > > > > The bitstreams for virtex and spartanII for same size device are the same. > > > > > > -- > > --Ray Andraka, P.E. > > President, the Andraka Consulting Group, Inc. > > 401/884-7930 Fax 401/884-7950 > > email ray@andraka.com > > http://www.andraka.com > > > > "They that give up essential liberty to obtain a little > > temporary safety deserve neither liberty nor safety." > > -Benjamin Franklin, 1759Article: 39633
Yury wrote:
>
> Modelsim XE is able to do everything that Modelsim PE can (according
> to Xilinx). I have used both. The XE version can be used without ISE
> software. You can use Modelsim XE, for example, for compiling
> Foundation VHDL libraries and then using them (Simprim, Unisim,
> Coregen, etc.). While slower then PE/SE, Modelsim XE will be able to
> perform pre-PAR simulation for you. However... if you want to do a
> post PAR functional (and possibly include the timing information)
> simulation then you are in for a treat. I attempted to use Modelsim XE
> for simulating post PAR 60% utilized Spartan-II-200. All I can say is
> there is a better way to spend my time. The simulation was taking
> forever without any timing info.
One thing I noticed when I did a P&R simulation with ModelSim
XE-Starter (Not the paid version ModelSim XE you used.) is that it took
something like 20 to 30 minutes to start responding (Getting data on a
Wave window.).
Perhaps if you leave the computer running for an hour or so, you should
start seeing something on a Wave window.
I simulated a design that occupied about 60% of XC2S150, at 33MHz for
10us.
That took about 4 hours to finish, but I must say that's far better than
paying several thousands of dollars for a full version of ModelSim
(Wasn't it $4,500 for ModelSim PE?) because I cannot afford that.
The design I simulated here was a PCI IP core I developed with Xilinx's
secret PCILOGIC (That mysterious IRDY and TRDY box thing people were
discussing sometime ago.) attached to my PCI IP core.
The PCI IP core simulated absolutely fine with that secret PCILOGIC,
which I was a little surprised since that feature is Xilinx's guarded
secret (unfair advantage).
> If I new ahead of time that ModelSim XE would be such a poor piece of
> software I would never have advised my emploer to purchase it. I guess
> you get what you pay for stands ($900 can not buy you a desent
> simulator).
I am poor, so at least I am happy that I can use some kind of
ModelSim without paying anything even though it is slow (I believe Post
P&R simulation is always slow.).
This may not be acceptable to you, but perhaps having a second computer
for the sole purpose of doing Post P&R simulation in ModelSim XE might
not be a bad idea.
After all, a fairly decent computer (Much faster one than the one I use
right now.) nowadays costs $900 or less.
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
Article: 39634
Nope.
Because some people may disagree with me, I checked both datasheets.
Also see Xilinx Application Note 138 and 176.
That should confirm what I wrote.
I am pretty sure that I read somewhere that Xilinx doesn't
guarantee both bitstreams to be 100% compatible, but I forgot where I
read that.
Peter Alfke (I haven't seen him for a week or so.) may know more about
that issue.
Kevin Brace (Don't respond to me directly, respond within the
newsgroup.)
"X. Q." wrote:
>
> The diference may come because you create them at different time,
> the Time and Device Type in the bit file makes up the difference in file
> size.
>
> --
> Best Regards,
> Qijun.
>
> ********************************************************************
> Xu Qijun
> Design Engineer, RFIC Group
> OKI Techno Centre (S) Pte Ltd
> 20 Science Park Rd, #02-06/10
> Teletech Park,Science Park II,
> Singapore 117674
> DID: 7707049 Fax: 7792382
Article: 39635I suspect it was because in the download board they used a Vertex family. while in the daughter board I put in a Spartan-II chip and daughter board. I tried to synthesize with spartan-ii chip and program the device, it displayed 200,123 differences. Could anybody know how to tackle these differneces? -- Best Regards, Qijun. ******************************************************************** Xu Qijun Design Engineer, RFIC Group OKI Techno Centre (S) Pte Ltd 20 Science Park Rd, #02-06/10 Teletech Park,Science Park II, Singapore 117674 DID: 7707049 Fax: 7792382 "Kevin Brace" <ihatespamkevinbraceusenet@ihatespamhotmail.com> wrote in message news:a4ht0v$la0$1@newsreader.mailgate.org... > Nope. > Because some people may disagree with me, I checked both datasheets. > Also see Xilinx Application Note 138 and 176. > That should confirm what I wrote. > I am pretty sure that I read somewhere that Xilinx doesn't > guarantee both bitstreams to be 100% compatible, but I forgot where I > read that. > Peter Alfke (I haven't seen him for a week or so.) may know more about > that issue. > > > > Kevin Brace (Don't respond to me directly, respond within the > newsgroup.) > > > > "X. Q." wrote: > > > > The diference may come because you create them at different time, > > the Time and Device Type in the bit file makes up the difference in file > > size. > > > > -- > > Best Regards, > > Qijun. > > > > ******************************************************************** > > Xu Qijun > > Design Engineer, RFIC Group > > OKI Techno Centre (S) Pte Ltd > > 20 Science Park Rd, #02-06/10 > > Teletech Park,Science Park II, > > Singapore 117674 > > DID: 7707049 Fax: 7792382Article: 39636
You are correct it is a bug. I worked it out last night that if you have signals that only appear in the ELSE part of a less than or grater than test (IF > THEN ELSE ENDIF) and are all zero on one everywhere else Leonardo decides to optimize them away for some reason. If I invert the test so the test becomes (IF = THEN ELSE END IF) the signals are in the first equals part then and not in the else part and Leonardo doesn't optimize them away. "Jay" <kayrock66@yahoo.com> wrote in message news:d049f91b.0202131822.6d1deb40@posting.google.com... > Sounds more like a bug than a gate limit. Report it as a bug along > with associated files, that usually gets their attention. > > > "Leon de Boer" <ldeboer@iprimus.com.au> wrote in message news:<3c6a780f$1_1@news.iprimus.com.au>... > > I have found while using Leonardo spectrum and Baseline for an Altera design > > that when I get to 10-15K gates the design leaves bits out of the synthesis. > > I have had this sort of behaviour with Actel licenses where they have a gate > > limit. I can't seem to get anyone at Altera or exemplar to be able to tell > > me absolutely if the free baseline, Leonardo version is gate limited. Does > > anyone know? > > > > Regards LeonArticle: 39637
> That's because they aren't interested in selling the Spartan and Spartan > XL to new customers. It's now considered a legacy part. They're happy > to keep selling the chips to existing customers, but they want you > to buy the Spartan II or Spartan IIE for new designs. > > Of course, you certainly *can* use the Spartan and Spartan XL for new > designs; just don't expect as much encouragement (e.g., free tools) out > of Xilinx if you do that. OK, but why not add a message "Not recommended for new designs" when you run the fitter, instead of just not providing support? Akin to taking the datasheet off the web page? :-) I understand, and like, the differences between -XL and -II, but I put a lot of effort into making this experimentation PCB!Article: 39638
It has been quite a while since I have worked with the Lucent tools, but I seem to remember seeing this problem before. I think it was due to using a component that was not in the library for the chip. Or I may have had the libraries wrong. I was working with two different chips (2T and 3T) and had some trouble setting them up the first time. Verify that the buffers that are giving you the problem are in the library. Also verify that you are pointing to the correct library(s). I do not remember any components called "BFI" anything. Inder wrote: > > I am trying to simulate a controller circuit on ORCA (OR3T00 > architecture) FPGA. > For schematic capture and EDIF file generation I am using Powerview > 6.1 tool. > But in the Build operation, which translates and converts the input > EDIF netlist > into ORCA generic database file(*.ngd), I have been getting this > error: > > ERROR - ngdbuild: Could not expand block '....' with TYPE='...' > > and after lot of looking around havent been able to solve the problem. > Can anyone tell me where and what am I doing wrong.. > > There was no error while generating EDIF file with Powerview tool and > I used the > Orca3 library in Powerview. > Here is a relevent part of log file generated by Orca. > > ORCA Foundry Control Center Log File -- Thursday, February 14, 2002 > 14:25 > > ---------------------------------------------------------------------- > /usr/local/apps/ORCA/bin/sol/edif2ngd -l or3c00 "abcd.edn" > "/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo" > ---------------------------------------------------------------------- > edif2ngd: version ORCA Foundry 2000 Production-w/SP-B (14) > Copyright 1991-1995 by NeoCAD Inc. All rights reserved. > Copyright (c) 1995-2000 Lucent Technologies. All rights > reserved. > WARNING - edif2ngd: Ampersands will be removed from numeric/underscore > identifiers. > WARNING - edif2ngd: GLOBAL property on a net other than power or > ground - > ignoring... > On or above line 113 in file abcd.edn > WARNING - edif2ngd: GLOBAL property on a net other than power or > ground - > ignoring... > On or above line 664 in file abcd.edn > WARNING - edif2ngd: GLOBAL property on a net other than power or > ground - > ignoring... > On or above line 3814 in file abcd.edn > Writing the design to /home/ikumar/3700-pv/orca/abcd_1/abcd.ngo... > > ---------------------------------------------------------------------- > /usr/local/apps/ORCA/bin/sol/ngdbuild -a or3t00 -p > "/home/ikumar/3700-pv/orca/sch" -p "/home/ikumar/3700-pv/orca" > "/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo" "abcd_1/abcd_1.ngd" > ---------------------------------------------------------------------- > ngdbuild: version ORCA Foundry 2000 Production-w/SP-B (14) > Copyright 1991-1995 by NeoCAD Inc. All rights reserved. > Copyright (c) 1995-2000 Lucent Technologies. All rights > reserved. > Reading '/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo' ... > Loading NGL library '/usr/local/apps/ORCA/or3c00/data/orc3clib.ngl'... > Loading NGL library '/usr/local/apps/ORCA/data/neoprims.ngl'... > Loading NGL library '/usr/local/apps/ORCA/data/neomacro.ngl'... > Loading device for application ngdbuild from file 'or3t12x12.nph' in > environment /usr/local/apps/ORCA. > Loading macro from file "/home/ikumar/3700-pv/orca/sch/all4_3lut.nmc". > Loading macro from file > "/home/ikumar/3700-pv/orca/sch/bottom2_3lut.nmc". > Loading macro from file "/home/ikumar/3700-pv/orca/sch/top3_3lut.nmc". > Loading macro from file > "/home/ikumar/3700-pv/orca/sch/bottom3_3lut.nmc". > ERROR - ngdbuild: Could not expand block '$1I53106/$1I9' with > TYPE='BUF' > ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST998' with > TYPE='UDFDL' > ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST995' with > TYPE='PW' > ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST6' with > TYPE='UDFDL' > ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST34' with > TYPE='NOT' > ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST27/$1I9' with > TYPE='BUF' > ERROR - ngdbuild: Could not expand block '$1I99402/INST1' with > TYPE='NOT' > ERROR - ngdbuild: Could not expand block '$1I99428/INST1' with > TYPE='AND3' > ERROR - ngdbuild: Could not expand block '$1I99428/BFI3' with > TYPE='BUF' > ERROR - ngdbuild: Could not expand block '$1I99428/BFI2' with > TYPE='BUF' > is unexpanded > > ********* around 10000 such errors ************ > > WARNING - ngdbuild: logical net 'DPRAM08-11/DO2' has no driver > WARNING - ngdbuild: logical net 'DPRAM08-11/DO3' has no driver > WARNING - ngdbuild: logical net 'DPRAM12-15/A0' has no driver > WARNING - ngdbuild: logical net 'DPRAM12-15/A1' has no driver > WARNING - ngdbuild: logical net 'DPRAM12-15/A2' has no driver > . > . > . > > WARNING - ngdbuild: logical net 'TP3' has no driver > WARNING - ngdbuild: logical net 'TP3' has no load > WARNING - ngdbuild: logical net 'TP4' has no driver > WARNING - ngdbuild: logical net 'TP4' has no load > WARNING - ngdbuild: logical net 'TP5' has no driver > WARNING - ngdbuild: logical net 'TP5' has no load > WARNING - ngdbuild: logical net 'TP6' has no driver > WARNING - ngdbuild: logical net 'TP6' has no load > WARNING - ngdbuild: logical net 'TP7' has no driver > WARNING - ngdbuild: logical net 'TP7' has no load > ERROR - ngdbuild: DRC failed with 9865 errors and 492 warnings > > Design Results: > 19 blocks expanded > Writing 'abcd_1/abcd_1.ngd' ... -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39639
I agree totally having used FPGA Express, Leonardo Spectrum and Xilinx ISE 4 for designs around the 10K-150K range I would rank them 1). ISE 4.x Xilinx 2). FPGA Express 3). Leonardo Spectrum. Strong Points. ISE 4.x Xilinx Gives best predictable and stable synthesis Picks use of ram/rom blocks from design readily Usually gives smaller and faster design All warnings during compilation are coloured Yellow (easy to see amongst the spool to screen) FPGA Express Very intuative to setup and use and has good online help Gives good warnings but you have to wade through the report. Leonardo Spectrum Good editor with nice colourization of source (easy to read) Weak Points. ISE 4.x Xilnx Exhaustive fit usually results in to many product terms and program crashes Pin assigning and locking is not intuitive (whats wrong with a graphical view of chip and place signals) Gate resource level view of synthesis is hopeless. FPGA Express Generally will not pick and use ROM/RAM blocks unless you specify it. Can give erratic synthesis at times. Leonardo Spectrum Never picks RAM/ROM blocks unless you specify it Has the most bugged and erratic synthesis of the 3 Puts up far to much minor warnings on screen that means you wade through piles of crap. "Sanket Bandyopadhyay" <sanket@insight.memec.co.in> wrote in message news:ee74a6c.1@WebX.sUN8CHnE... > Well, XST is more stable and has the better QoR than FPGA Express. > You can make a small design of a PWM and see for yourself. > You will see that,after synthesising with FPGA express,you may get slightly different P&R results every time, but with XST you get repeatedly same P&R results after synthesis.XST is better.Moreover you can actually feel the difference in a more than million gate design.That is actually the trial by fire.Article: 39640
I have been reading about configuration of the SpartanIIE parts in
SelectMAP (Slave Parallel) mode and it is not all that straight forward.
But with XAPP_176, it looks like I have it down. But I am still not
clear about what to do with the CCLK signal.
I have very few (one) dedicated IO signal to drive the configuration
with. I could come up with another, but I would have to give up a
feature elsewhere. But I have several signals from the DSP that can be
used as general IO during configuration if I can then use them as their
dedicated function after the SpartanIIE is fully configured. It looks
like I can do this for nearly all the required configuration signals.
Other than PROGRAM-, the configuration signals are all inputs or open
driver outputs (open when properly configured) which can be paralleled
with a user IO. This will let me use the DSP signals as they are needed
after configuration.
The only fly in the ointment is CCLK. As far as I can tell, it is
ignored when CS- is not asserted. I plan to connect CCLK to the WE- bus
signal. This will give me a single CCLK rising edge for each data word
(byte) while configuring. But once configuration is over, is it ok to
continue to toggle CCLK? I seem to remember that in some modes on other
Xilinx parts, CCLK should stop toggling once the part is fully
configured and operational. Will there be a problem in SelectMAP mode if
CCLK continues to toggle after configuration is complete?
I believe I have all the issues covered for the configuration. CS- is
generated from the DSP decoded Chip Select, Write- is a DSP IO pin,
PROGRAM- comes from a board control output on an MCU and DONE and INIT-
go to DSP IO pins. DONE is paralleled with an FPGA user IO to allow the
DSP IO pin to be used after config and the INIT- signal becomes a user
IO as does the CS-. And of course the 8 data bits are connected to the
low 8 data bits from the DSP and become 8 of the 32 data bus bits once
configured.
MCU DSP FPGA
--------------------------
PRGM- > > PRGM-
TINP0 < < DONE (with a user IO)
TINP1 < < INIT-
AWE- > > CCLK (with a user IO)
ED[7:0] > > D[0:7]
CE3- > > CS-
TOUT0 > > WRITE-
Now I just need to make sure toggling the CCLK pin won't muck things up
after config is complete.
--
Rick "rickman" Collins
rick.collins@XYarius.com
Ignore the reply address. To email me use the above address with the XY
removed.
Arius - A Signal Processing Solutions Company
Specializing in DSP and FPGA design URL http://www.arius.com
4 King Ave 301-682-7772 Voice
Frederick, MD 21701-3110 301-682-7666 FAX
Article: 39641Howdy, Bob Perlman <no-spam@sonic.net> wrote: > The problems with using clock pulses or gated clocks have been pretty > much beaten to death in this newsgroup, so I won't belabor the point. Do you mean _asynchronous_ clock pulses/gated clocks here? I was just about to rewrite a section of my design to only generate clocks to the coregen FIFO when necessary, keeping the enable active. My current problem is the enable line to the BlockRAMs in the FIFO is the critical path. If I can generate pulses only when I need them, then I can run the system a little faster. The idea is to use a FF to divide the main clock by two. This would then become the FIFO read clock. I would limit the pulses by using the clock enable on that FF. If I can constrain the path from the rising/falling edge of the main clock through the FF, through the FIFO, and to the inputs of a set of FF's, then I don't immediately see where the problems lie. Thanks, G P.S. Sorry about the email address. I have 'misplaced' the slip of paper with my Yahoo Email password.. :(Article: 39642
Hi, I'm doing a post PAR sim on a Virtex XCV300. We have an output enable pin which enables a tristate bus. When it's enabled, sometimes the bus goes from all 'Z's to the output value, but transitions thru' a bunch of 'X's for maybe a couple of nanosecs. There is no bus contention apparently (using Modelsim & "check contention add <signame>). Is this to be expected? It seems that as the relevent output is enabled, it turns on in a strange way! tia, niv.Article: 39643
Ray Andraka wrote: > I've found 4.1 to be just about useless for anything other than VirtexII designs. [snip] This "result" proves our opinion which claims that newest version of Xilinx tools only improves newest Xilinx devices. So probably a v5.1i, a next major release will be optimized for a new Xilinx device coming in, for a Xilinx counterpart of Altera's Stratix maybe? UtkuArticle: 39644
I've symply do the following : use different configuration of core generator single port blockram read only of dimension 12x4096 and working on rising edge of the clock, at the address input I apply a counter that produce a different address at every clock cycle and a FFD to change rapidly from rising to falling edge, my expectation is to have a new output value at every clock cycle, but this are the result : 1) only registered output -> a result every 2 clock cycles 2) unregistered input and output -> a result every 2 clock cycles if the address change on rising edge otherwise if change on falling edge I've no output and a lot of : # : WARNING: */RAMB4_S1 SETUP Low VIOLATION ON ADDR(0) WITH RESPECT TO CLK; # : Expected := 0.01 ns; Observed := 0 ns; At : 1250 ns 3) only registered input -> no output regardless on the fact that address change on rising or on falling edgeArticle: 39645
My circuit is now really symple, I've the following :
In->FF_fallingEdge-->FIFO_15x1_falling_edge-->Shift_register_SIPO_falling_edge
| | | | | | | | | 1 | 2| | | |
| | | 9|
| | | | | | | | |
BLOCKRAM_12x4096_rising_edge --> OUT
for the FIFO I use the new Xilinx CORE version 4.0 and also for the
RAM I use the new CORE version 4.0 , I've the following problems :
1) If I choose registered input and output for the blockram I've no
output from it
2) if I choose unregistered input and output I've an output from the
blockram but I've also a big amount of warning like this from ALDEC :
# : WARNING: */RAMB4_S1_S1 SETUP Low VIOLATION ON ADDRB(1) WITH
RESPECT TO CLKB;
# : Expected := 0.01 ns; Observed := 0 ns; At : 164625 ns
# : Time: 164625 ns, Iteration: 3, Instance: /U1/U10/B7.
# : WARNING: */RAMB4_S1_S1 SETUP Low VIOLATION ON ADDRB(0) WITH
RESPECT TO CLKB;
# : Expected := 0.01 ns; Observed := 0 ns; At : 164625 ns
# : Time: 164625 ns, Iteration: 3, Instance: /U1/U10/B7.
# : WARNING: */RAMB4_S1_S1 SETUP Low VIOLATION ON ENB WITH RESPECT TO
CLKB;
# : Expected := 0.01 ns; Observed := 0 ns; At : 164625 ns
I've read from the Xilinx Problem Solver that this could happen cause
the asynchronous FIFO works with 2 different clock and this could be a
problem for the synchronization logic that It's inside but the output
of the circuit seems to be sensitive to these warnings.
Article: 39646Hello, I was just wondering if you got your asynchronous FIFO to work by now. For some days I'm also trying to get my design using one of these to work, without success yet (ISE 4.1 & Model Sim XE Starter). I am using continuous read and write clocks with synchronous enables. Behavioral simulation works fine, but as soon as I proceed to a post translate simulation I get 'open' select signals of internal fifo-muxes in the translate file. P&R works, just the post P&R simulation is not exactly what I expected it to be, as if the behavioral model and the coregen netlist were not consistent. Any new ideas yet? Thanks JonasArticle: 39647
I have set the viewlogic's powerview to use the orca3 architecture macro library and there is no error or warnings when i convert the schematic design to EDIF file... FYI, I am working on schematic files created by somebody else, also using powerview's viewdraw tool .. I also think that there is something wrong with the library settings but am not able to locate it.. i dont think its because of some component not in the library otherwise powerview should have given the error ? i'll appreciate any furthur help in this.. rickman <spamgoeshere4@yahoo.com> wrote in message news:<3C6C86AA.9D8A8903@yahoo.com>... > It has been quite a while since I have worked with the Lucent tools, but > I seem to remember seeing this problem before. I think it was due to > using a component that was not in the library for the chip. Or I may > have had the libraries wrong. I was working with two different chips (2T > and 3T) and had some trouble setting them up the first time. > > Verify that the buffers that are giving you the problem are in the > library. Also verify that you are pointing to the correct library(s). I > do not remember any components called "BFI" anything. > > > > Inder wrote: > > > > I am trying to simulate a controller circuit on ORCA (OR3T00 > > architecture) FPGA. > > For schematic capture and EDIF file generation I am using Powerview > > 6.1 tool. > > But in the Build operation, which translates and converts the input > > EDIF netlist > > into ORCA generic database file(*.ngd), I have been getting this > > error: > > > > ERROR - ngdbuild: Could not expand block '....' with TYPE='...' > > > > and after lot of looking around havent been able to solve the problem. > > Can anyone tell me where and what am I doing wrong.. > > > > There was no error while generating EDIF file with Powerview tool and > > I used the > > Orca3 library in Powerview. > > Here is a relevent part of log file generated by Orca. > > > > ORCA Foundry Control Center Log File -- Thursday, February 14, 2002 > > 14:25 > > > > ---------------------------------------------------------------------- > > /usr/local/apps/ORCA/bin/sol/edif2ngd -l or3c00 "abcd.edn" > > "/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo" > > ---------------------------------------------------------------------- > > edif2ngd: version ORCA Foundry 2000 Production-w/SP-B (14) > > Copyright 1991-1995 by NeoCAD Inc. All rights reserved. > > Copyright (c) 1995-2000 Lucent Technologies. All rights > > reserved. > > WARNING - edif2ngd: Ampersands will be removed from numeric/underscore > > identifiers. > > WARNING - edif2ngd: GLOBAL property on a net other than power or > > ground - > > ignoring... > > On or above line 113 in file abcd.edn > > WARNING - edif2ngd: GLOBAL property on a net other than power or > > ground - > > ignoring... > > On or above line 664 in file abcd.edn > > WARNING - edif2ngd: GLOBAL property on a net other than power or > > ground - > > ignoring... > > On or above line 3814 in file abcd.edn > > Writing the design to /home/ikumar/3700-pv/orca/abcd_1/abcd.ngo... > > > > ---------------------------------------------------------------------- > > /usr/local/apps/ORCA/bin/sol/ngdbuild -a or3t00 -p > > "/home/ikumar/3700-pv/orca/sch" -p "/home/ikumar/3700-pv/orca" > > "/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo" "abcd_1/abcd_1.ngd" > > ---------------------------------------------------------------------- > > ngdbuild: version ORCA Foundry 2000 Production-w/SP-B (14) > > Copyright 1991-1995 by NeoCAD Inc. All rights reserved. > > Copyright (c) 1995-2000 Lucent Technologies. All rights > > reserved. > > Reading '/home/ikumar/3700-pv/orca/abcd_1/abcd.ngo' ... > > Loading NGL library '/usr/local/apps/ORCA/or3c00/data/orc3clib.ngl'... > > Loading NGL library '/usr/local/apps/ORCA/data/neoprims.ngl'... > > Loading NGL library '/usr/local/apps/ORCA/data/neomacro.ngl'... > > Loading device for application ngdbuild from file 'or3t12x12.nph' in > > environment /usr/local/apps/ORCA. > > Loading macro from file "/home/ikumar/3700-pv/orca/sch/all4_3lut.nmc". > > Loading macro from file > > "/home/ikumar/3700-pv/orca/sch/bottom2_3lut.nmc". > > Loading macro from file "/home/ikumar/3700-pv/orca/sch/top3_3lut.nmc". > > Loading macro from file > > "/home/ikumar/3700-pv/orca/sch/bottom3_3lut.nmc". > > ERROR - ngdbuild: Could not expand block '$1I53106/$1I9' with > > TYPE='BUF' > > ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST998' with > > TYPE='UDFDL' > > ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST995' with > > TYPE='PW' > > ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST6' with > > TYPE='UDFDL' > > ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST34' with > > TYPE='NOT' > > ERROR - ngdbuild: Could not expand block 'GO_READ+13/INST27/$1I9' with > > TYPE='BUF' > > ERROR - ngdbuild: Could not expand block '$1I99402/INST1' with > > TYPE='NOT' > > ERROR - ngdbuild: Could not expand block '$1I99428/INST1' with > > TYPE='AND3' > > ERROR - ngdbuild: Could not expand block '$1I99428/BFI3' with > > TYPE='BUF' > > ERROR - ngdbuild: Could not expand block '$1I99428/BFI2' with > > TYPE='BUF' > > is unexpanded > > > > ********* around 10000 such errors ************ > > > > WARNING - ngdbuild: logical net 'DPRAM08-11/DO2' has no driver > > WARNING - ngdbuild: logical net 'DPRAM08-11/DO3' has no driver > > WARNING - ngdbuild: logical net 'DPRAM12-15/A0' has no driver > > WARNING - ngdbuild: logical net 'DPRAM12-15/A1' has no driver > > WARNING - ngdbuild: logical net 'DPRAM12-15/A2' has no driver > > . > > . > > . > > > > WARNING - ngdbuild: logical net 'TP3' has no driver > > WARNING - ngdbuild: logical net 'TP3' has no load > > WARNING - ngdbuild: logical net 'TP4' has no driver > > WARNING - ngdbuild: logical net 'TP4' has no load > > WARNING - ngdbuild: logical net 'TP5' has no driver > > WARNING - ngdbuild: logical net 'TP5' has no load > > WARNING - ngdbuild: logical net 'TP6' has no driver > > WARNING - ngdbuild: logical net 'TP6' has no load > > WARNING - ngdbuild: logical net 'TP7' has no driver > > WARNING - ngdbuild: logical net 'TP7' has no load > > ERROR - ngdbuild: DRC failed with 9865 errors and 492 warnings > > > > Design Results: > > 19 blocks expanded > > Writing 'abcd_1/abcd_1.ngd' ... > > -- > > Rick "rickman" Collins > > rick.collins@XYarius.com > Ignore the reply address. To email me use the above address with the XY > removed. > > Arius - A Signal Processing Solutions Company > Specializing in DSP and FPGA design URL http://www.arius.com > 4 King Ave 301-682-7772 Voice > Frederick, MD 21701-3110 301-682-7666 FAXArticle: 39648
I am using it as part of the NIOS development kit and have used it successfully for 200K gate devices, with no problems. The only limitation I know of is that it can only be used for Altera devices. Maybe the Baseline version is different than the one supplied with NIOS (but I did compile a NIOS v1.0 design with the original Leonardo early in 2001) Victor "Leon de Boer" <ldeboer@iprimus.com.au> wrote in message news:3c6a780f$1_1@news.iprimus.com.au... > I have found while using Leonardo spectrum and Baseline for an Altera design > that when I get to 10-15K gates the design leaves bits out of the synthesis. > I have had this sort of behaviour with Actel licenses where they have a gate > limit. I can't seem to get anyone at Altera or exemplar to be able to tell > me absolutely if the free baseline, Leonardo version is gate limited. Does > anyone know? > > Regards Leon > > >Article: 39649
"X. Q." <qijun@okigrp.com.sg> wrote in message news:<3c6b8a49@news.starhub.net.sg>...
> Hi, gurus:
>
> I am programming with Spartan-II chip.
> How come iMPACT indicates vcx100 when initializing the chain
> while my FPGA chip is actually an XC2S100-5PQ208.
I experienced a similar problem a while ago, with Spartan IIEs. Are
you using the Xilinx Webpack? I found that there were some .bsd files
missing from the WebPack installation, and I had to download them from
the Xilinx website. Check if you have the correct .bsd files for your
part.
Cheers,
Dave
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