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I've done 24 bits. Typically though, it is around 12-16 bits. A rule of
thumb is you get about 5db stop band to pass band range for each bit in the
coefficient. With careful selection of coefficients you do better, but I
don't know of any algorithm to optimize the coefficients for minimum bits
for a given response requirement.
Ken Mac wrote:
> Hello folks,
>
> Can you let me know what the maximum FIR filter coefficient width is you
> have implemented on FPGA please?
>
> Also, what are the typical widths you find yourself implementing.
>
> Thanks for your time,
>
> Ken
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45651Hi, I'm in desperate need of a few xc2v3000-fg676-5, so one of you guys wouldn't happen to have some lying around that you don't need right now ? thanks, -Lasse -- // Lasse Langwadt Christensen // Aalborg, DanmarkArticle: 45652
I am trying to implement a 14x10 multiplier into slices in the Virtex II (not the dedicated multipliers) using LeonardoSpectrum and Xilinx ISE 4.1i. I have added a register after the multiply so that LeonardoSpectrum will pipeline the multiplier. But when I place & route, I am only getting speeds of about 70 MHz (when the LUT max fanout is set to 5); however, when I do a similar design for the Stratix (multiplier implemented in logic elements, not dsp blocks), the design runs over 150 MHz. The only difference is that I am using Quartus II's MegaWizard to generate the multiplier instead of Leonardo. I find it hard to believe that there is that much difference between the FPGAs. Has anybody else had better luck with the Virtex II (either with Synplify or Leonardo)? Thanks, Ben HoweArticle: 45653
You are comparing apples to oranges to some degree here. The megawizard
multiplier is optimized for the altera structure where the one you are
generating with leo is not necessarily optimized to any architecture. A
fairer comparison would be to use the same code with leonardo and
changing just the target part. You could also use the core generator to
generate a fabric core (I think it works now for V2). I've got some
15x8 mutlipliers in a design I am working on here in V2-4, fully
pipelined coming in at slightly over 200 MHz with a 4 clock latency. It
is interesting to note that the carry chains in VIrtexII are not as fast
as one would expect given the speeds of the rest of the fabric. The
culprit seems to be the inordinately long time to get off the carry chain
and into the register in the same half-slice, which is on the order or
1.5ns. There is also a fairly fat delay getting onto the carry chain.
Still, that shouldn't kill the performance all the way down to 70 MHz
unless it isn't pipelined, placement is really poor, or the design just
isn't right for the architecture.
Ben Howe wrote:
> I am trying to implement a 14x10 multiplier into slices in the Virtex
> II (not the dedicated multipliers) using LeonardoSpectrum and Xilinx
> ISE 4.1i. I have added a register after the multiply so that
> LeonardoSpectrum will pipeline the multiplier. But when I place &
> route, I am only getting speeds of about 70 MHz (when the LUT max
> fanout is set to 5); however, when I do a similar design for the
> Stratix (multiplier implemented in logic elements, not dsp blocks),
> the design runs over 150 MHz.
>
> The only difference is that I am using Quartus II's MegaWizard to
> generate the multiplier instead of Leonardo. I find it hard to
> believe that there is that much difference between the FPGAs. Has
> anybody else had better luck with the Virtex II (either with Synplify
> or Leonardo)?
>
> Thanks,
> Ben Howe
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 45654Ray, Thanks for the quick response - I appreciate you passing on your experience. Cheers, Ken > I've done 24 bits. Typically though, it is around 12-16 bits. A rule of > thumb is you get about 5db stop band to pass band range for each bit in the > coefficient. With careful selection of coefficients you do better, but I > don't know of any algorithm to optimize the coefficients for minimum bits > for a given response requirement. --- Outgoing mail is certified Virus Free. Checked by AVG anti-virus system (http://www.grisoft.com). Version: 6.0.380 / Virus Database: 213 - Release Date: 24/07/2002Article: 45655
You want to hook up a passive element to an FPGA and know what its impedance is? Not gonna happen. It appears you aren't asking the entire question. Are you looking at an impedance measurement test set application with an FPGA at the core? The system level design can be put together in too many different ways to have "one" way to implement impedance measurement well. Please explain a little better what you're trying to accomplish. Daniel wrote: > I'm looking for an app note or article that has an example of implementing impedance measuring code in an FPGA (preferably the Virtex-II Pro). > > Any advice/comments are welcome. > > DanielArticle: 45656
Hi, we have a gadget that receives a lot of clocked serial data words, in chunks of 20 bits. Each 20 bit word comes into our chip (Xilinx XC2S50) with its own data and clock lines, and each gives us a burst of 20 clocks + data at approximately an expected time (actually, when a laser fires). We have a bunch of these, too many to use an official clock net to clock each 20-bit shift register. So we're just using a regular net as the clock line; we're doing plain vanilla schematic design under ISE4.2i. The burst clock frequencies are nominally 20 MHz, and the available 'official' clock is 20 MHz, so there are no obvious resynchronization tricks available. So, is this safe? Since the flipflops are fast and routing delays are sorta random, it's possible for flop N to be clocked before N+1; then, if the Qn to Dn+1 path is fast, the N+1 flipflop could conceivably strobe the wrong data. Any thoughts? Thanks, JohnArticle: 45657
Sorry, I wasn't clear enough. I'm looking for an example or a reference on building a system with the FPGA at the core for measuring a passive element's impedance. Basically, i'm looking for some examples of the different ways to implement impedance measurement.Article: 45658
John Larkin (John@0.com) wrote: : Hi, : we have a gadget that receives a lot of clocked serial data words, in : chunks of 20 bits. Each 20 bit word comes into our chip (Xilinx : XC2S50) with its own data and clock lines, and each gives us a burst : of 20 clocks + data at approximately an expected time (actually, when : a laser fires). : We have a bunch of these, too many to use an official clock net to : clock each 20-bit shift register. So we're just using a regular net as : the clock line; we're doing plain vanilla schematic design under : ISE4.2i. : The burst clock frequencies are nominally 20 MHz, and the available : 'official' clock is 20 MHz, so there are no obvious resynchronization : tricks available. : So, is this safe? Since the flipflops are fast and routing delays are : sorta random, it's possible for flop N to be clocked before N+1; then, : if the Qn to Dn+1 path is fast, the N+1 flipflop could conceivably : strobe the wrong data. : Any thoughts? Instead of a 20 bit SR you can use a 40 bit one with the even flops clocked off one phase of the clock and the odd flops off the other. Or bring each channel into a 4 bit SR. That would be smaller and easier to time. Once that fills then save the 4 bits into a output latch and then into a 4X5 SR running of the system clock. That would be at 1/4 the frequency and easier to handle. John EatonArticle: 45659
That's a general question of analog measurement, digitizing, and control. Depending on the frequency or frequencies of interest, range of impedances, voltage levels, and so on there is a vast array of bridge and other circuits to convert the unknown values to a measurable voltage, current, or frequency. If a voltage or current, the next step is digitizing; if frequency, counting. Finally, controlling the measurement circuitry and conversion of the raw data to meaningful results is the domain of digital circuitry - discrete, FPGA, microprocessor, or some combination of them. Again, some idea of the range of what you want to measure will make all the difference. You can also find lots of examples of realized systems in the literature. A familiarity with them is what makes Agilent, Tektronix, and so on profitable... Jim Horn, WB9SYN/6 (was with Agilent for ten years)Article: 45660
Thanks Michael, that did the trick. I looked everywhere to find this
mapping. The block ram documentation 'aspect ratio' table leads you to
believe that it is mapped like conventional memory, that is addr 0
gets bits 3 downto 0 on port a or 7 downto 0 on port b. Anyway, thanks
for helping me get it right. This one gets filed away in my 'important
notes' folder.
Mike
On Tue, 30 Jul 2002 13:54:20 +0200, "Michael Rhotert"
<mrhotert@yahoo.com> wrote:
><mrmikehicks@earthlink.net> wrote
>> Am I portmapping this wrong., Has anybody else had this problem with
>> dual ports of different sizes?
>> Mike
>
>Connect the "bram_b_data" bus in this way:
>
>bram_fr_b1:
>dob(3 downto 0) => bram_b_data(3 downto 0)
>dob(7 downto 4) => bram_b_data(39 downto 36)
>
>bram_fr_b2:
>dob(3 downto 0) => bram_b_data(7 downto 4)
>dob(7 downto 4) => bram_b_data(43 downto 40)
>
>...
>
>bram_fr_b9:
>dob(3 downto 0) => bram_b_data(35 downto 32)
>dob(7 downto 4) => bram_b_data(71 downto 68)
>
>This may give you the result you expect
>Michael
>
>
Article: 45661Does anyone have an Intel .hex to Xilinx .coe format conversion program in C or Perl? Thanks, ScottArticle: 45662
You really need to clarify your problem: Do you mean the DDR SDRAM controller (DDR) entity and the test entity (TEST) are the primary blocks (sub-designs) at the top level of one FPGA design? Or is each one of them a stand-alone FPGA? Or is the DDR an FPGA and TEST is really a "Test Bench" (which is only used in simulation, not synthesis)? Are you 'black-boxing' any of the sub-designs of the FPGA? Ersin wrote: > Hello Friends, > > I have a DDR SDRAM controller entity and a test entity in a synplify > project. I can compile & implement & route successfuly. However, if I > produce a netlist out of DDR SDRAM controller entity and use this with the > test entity it doesn't work correctly. > > Does anyone had a similar problem? > > Thanx, > Ersin -- ============================== William Lenihan lenihan3we@earthlink.net ==============================Article: 45663
Thanks, that was kind of what I thoght was going on, but you put it really clearly! -- Børge "Speedy Zero Two" <david@manorsway.NOSPAMPLEASE.freeserve.co.uk> wrote in message news:ahpe89$ra1$1@newsg3.svr.pol.co.uk... > Hi Børge, > > The constraints editor only works on synthesised logic so if you break your > design It will complain. > > Ever time you change a file, webpack will recompile the code first. > The errors are because you broke your code and not coming from the > Constraints editor. > > Hope this makes sense, > Dave > > "Børge Strand" <borge.strand.remove.if.not.spamming@sintef.no> wrote in > message news:1027612806.9313@halvan.trd.sintef.no... > > Thanks Troy, > > > > I'm a lot less confused now, at least when it comes to the pinout. I > played > > with wait's and @'s the other day, and the Constraints Editor had strong > > opinions on those as well. I'll look more deeply into those tomorrow > morning > > and post again if there are still problems. > > > > -- > > Børge > > snip > >Article: 45664
I'd personally run the 555 at a higher speed and then use a counter to divide the clock back to your desired frequency. The resistors and capacitors needed for a 1Hz oscillator might not be very handy. The counter would also buffer the signal and, depending on circuit family, provide other rise/fall times than the 555. Regards, Børge "Jim Granville" <jim.granville@designtools.co.nz> wrote in message news:3D430D08.34B0@designtools.co.nz... > suchitra wrote: > > > > hello all > > i just wanted to know that can 555 be used for cplds as clock input if > > the frequency is very low something like 1 hz. > > regards > > Probably, but you might prefer to look at > - Tiny Logic SChmitt gates ( X14 ), in SOT23 packages > - XX4060 counter chains, in SO16/TSSOP16, that have 2^14 dividers, > so allow more precise and smaller/cheaper RC components, as well as > a fast test mode. > 1Hz in a NE555 will be something of a lottery :) > -jgArticle: 45665
No it is not a simulation testbench. Let me tell my problem more detailed. I have two vhdl files, they are: ddr_sdram.vhd and ddr_wrapper.vhd (this is the test entity). I use Synpify to compile the whole project and produce a netlist. I use this netlist with a constraints file (*.ucf) in Xilinx Ise environment and generate my bit stream file. Everything is fine. However, if I generate two netlists with synplify (ddr_sdram.edif and ddr_wrapper.edif) and build them with Ise tools, the resultant bit file doesn't run correctly altogugh place & route results are better for timing constraints. Ersin "William Lenihan" <lenihan3we@earthlink.net> wrote in message news:3D4799ED.5ED8AE50@earthlink.net... > > You really need to clarify your problem: > > Do you mean the DDR SDRAM controller (DDR) entity and the test entity (TEST) > are the primary blocks (sub-designs) at the top level of one FPGA design? > > Or is each one of them a stand-alone FPGA? > > Or is the DDR an FPGA and TEST is really a "Test Bench" (which is only used in > simulation, not synthesis)? > > Are you 'black-boxing' any of the sub-designs of the FPGA? > > > Ersin wrote: > > > Hello Friends, > > > > I have a DDR SDRAM controller entity and a test entity in a synplify > > project. I can compile & implement & route successfuly. However, if I > > produce a netlist out of DDR SDRAM controller entity and use this with the > > test entity it doesn't work correctly. > > > > Does anyone had a similar problem? > > > > Thanx, > > Ersin > > -- > ============================== > William Lenihan > lenihan3we@earthlink.net > ============================== > >Article: 45666
At the beginning of the year I was using latest versions of both SynplifyPro and Leonardo Level 2 on the same design. Synplify was much easier to use and synthesised the design several times faster. Both produced good synthesis results, achieving difficult timing and layout with Xilinx Virtex families, but you need to use the TCL scripting language with Leonardo to get the results. If you are new to synthesis, SynplifyPro would be a less painful start. It also allows you to switch to SynplifyAsic very easily, as we did. If your company is in bed with Mentor, you'll have no choice, but it does produce good output! If you have a choice, get them competing on price!Article: 45667
I solved the problem, it was a missing attribute of a tristate signal. following lines solved the problem attribute syn_black_box : boolean; attribute syn_black_box of ddr_sdr_cesys: component is true; attribute black_box_tri_pins : string; attribute black_box_tri_pins of ddr_sdr_cesys : component is "tristate_q"; Ersin "Ersin" <eozalp@cesys.com> wrote in message news:ai64jk$11rsqv$1@ID-73344.news.dfncis.de... > Hello Friends, > > I have a DDR SDRAM controller entity and a test entity in a synplify > project. I can compile & implement & route successfuly. However, if I > produce a netlist out of DDR SDRAM controller entity and use this with the > test entity it doesn't work correctly. > > Does anyone had a similar problem? > > Thanx, > Ersin > > > >Article: 45668
Hi !
I'm trying to interface a device with 2.75V IO to an
Xilinx Virtex/Spartan 2e device. The specific characteristics
of this device are:
Min Max
VOH 2.2 2.75
VOL 0 0.6
VIH 1.93 2.75
VIL 0 0.5
The FPGAs offer a LVCMOS2 IO standard that comes VERY close.
Specifically the Spartan2E data sheet says:
Min Max
VOH 1.9
VOL 0.4
VIH 1.7 2.7
VIL 0.5 0.7
Cross referencing these two tables results in only two
slight mismatches:
Xilinx VOH Max is 1.9V - My Device VIH Min is 1.93V
and
Xilinx VIH Max is 2.7V - Device VOH Max is 2.75V
As subtle as these differences are, I must make find a
solution around that problem that will guarantee that
the equipment we are building works !
The first thing that came to my mind was to rise the
IO Ring Voltage (Vcco) from 2.5V nominal to 2.7V nominal.
Any suggestions/recommendation/real life stories ?
Thanks a million !
rudi
Article: 45669Hi all, here's a new newbie question from me: On a Spartan IIE, what is the net name that Verilog uses for the global reset? I guess this signal is active low. Regards, BørgeArticle: 45670
Hi, I'm curious if it's possible to quantify the performance of FPGA's.. i.e in terms of Operations per second. What i'm really confused about is when say the FPGA is doing FFT computations it must do it at say X ops/sec, but while the same chip is doing a DCT it would do it at Y ops/sec. how can one quantify it? more over if one part of the fpga is doing FFT and another part is doing a DCT how many ops does that make it.. thanks, AutoArticle: 45671
"John Larkin" <John@0.com> schrieb im Newsbeitrag news:nc1ekucejrhdgou12htoi6srlm89cht9l7@4ax.com... > The burst clock frequencies are nominally 20 MHz, and the available > 'official' clock is 20 MHz, so there are no obvious resynchronization > tricks available. > > So, is this safe? Since the flipflops are fast and routing delays are > sorta random, it's possible for flop N to be clocked before N+1; then, > if the Qn to Dn+1 path is fast, the N+1 flipflop could conceivably > strobe the wrong data. Yes and no. In general its a good idea to stay on the dedicated clock nets. But in real life, you alway run out of clock nets ;-) So what can you do? I solved this problem in the past by using normal routing for clock distribution BUT while keeping the logic on this clock to a minimum ( a dozen of FlipFlops or so). The best way is to use a asynchronous FIFO. Write the data with the clock on the non clock net (for each individual incomming channel), read the data on the other side with a global clock net. This means, move the whole processing stuff to one common clock net and just use the incomming clock for synchronization. -- MfG FalkArticle: 45672
Anyone give me ideas of how to do FM tone detection of TTL pulse train in VHDL code. What I have is two frequencies I want a high for 1 and a low for the other. Regards LeonArticle: 45673
> From: Leon de Boer [mailto:ldeboer@attglobal.net] > Subject: tone detection... > > Anyone give me ideas of how to do FM tone detection of TTL > pulse train in VHDL code. > > What I have is two frequencies I want a high for 1 and a low > for the other. And what if neither is present? :-) Speed? Accuracy? Is the tone guaranteed pure, or could it be contaminated with other signal transitions? If you have a nice clean input signal and it's at a fairly low frequency (e.g. TV remote control application) you could simply measure the period (time between rising transitions) and assert your output when you've seen a decent number of cycles all within some tolerance of the expected value. That's pretty easy (unless viewed from the standpoint of an undergraduate who has an assignment to do). If the frequency is rather high, you may do better to build a proper frequency counter that measures the number of input cycles in a given time interval. That's a system with two clock domains, needing some care at the clock domain crossings. Choice of measurement interval will be determined by the bandwidth of the modulation data source, depth of FM modulation (deviation), carrier frequency and perhaps other factors. If there could be noise, drift or other horribleness, you may need to do a proper digital demodulator, in which case a reasonable acquaintance with DSP will come in handy. -- Jonathan Bromley HDL Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project = Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 = 1AW, UK Tel: +44 (0)1425 471223 mail: = jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: = http://www.doulos.com This e-mail and any attachments are confidential and Doulos Ltd. = reserves all rights of privilege in respect thereof. It is intended for the use = of the addressee only. If you are not the intended recipient please delete = it from your system, any use, disclosure, or copying of this document = is unauthorised. The contents of this message may contain personal views = which are not the views of Doulos Ltd., unless specifically stated.Article: 45674
This might not be the exact answer you are looking for, but with the lack of any other replies, I thought it might be better than nothing. http://www.fpga-faq.com/FAQ_Pages/0027_Creating_PCB_symbols_for_FPGAs_using_ORCAD.htm Walt Jerry wrote: > > Does anyone know where I can find an ORCAD capture library symbol for a PQ240 VirtexE part?
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