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Hi !
I'm reading documentation and i can read detail description of spartan
pin-outs but I need just simple information - how much available i/o pins
can be located in xc2s100 when i use pq-208 and fg-256 - i need just like
that. Thanks for your help.
Regards,
Maciek
Article: 45726Hi all, I'm trying to make Spartan II BlockRAM clocks active on falling edge. When I simply invert the clock (eg: clk_inv <= not clk, using VHDL) the implementation tool (WebPack + XST) complains about non clock connections of the clk signal. I'm afraid it could impact the design performance or add skew. In the Spartan II datasheet (and numerous other places) it is stated that on a BlockRAM "control pins for each port have independent inversion control as a configuration option". Nowhere I'm told how to use this inversion control. Browsing through datasheets, appnotes and on Google yields no results. Any help is appreciated. -- :wqArticle: 45727
Hi, What's the equivalent of ALTERA EP20K200-2X (APEX 200 000 gates), on XILINX device? it's a VIRTEX device with 200 000 gates? And what's the equivalent of XILINX XC2S100-5 (SPARTAN2 100 000gates), on ALTERA device? it's a FLEX device with 100 000 gates? I want to know it, because i made a benchmark study on signal processing between NIOS(on APEX dev. board) and MICROBLAZE(on SPARTAN2 demo board) softcore and i want to relativize with chi's performances. ThanksArticle: 45728
> The burst clock frequencies are nominally 20 MHz, and the available > 'official' clock is 20 MHz, so there are no obvious resynchronization > tricks available. Why dont you produce a higher system clock "SYSCLK" out of your official clock ? The SPARTAN-II CLKDLL can do it. Then you could sample the 20 input clocks and input data using "SYSCLK". If you detect a rising input clock, you store the sampled data. This works only if the data is valid +/- Periodlength(SYSCLOCK) relative to the data's clock. -ManfredArticle: 45729
Hi Stan, You might not aware that equivalent checker is just one type of formal verification. Formal verification simply means to proof something formally, or using mathematics. One type of formal verification is "formal model checker". You define a certain properties, and some constraints, and then you proof it using "formal model checker". An example is that every request must be acknowledge within 5 cycles. Another type of formal verification is "clock domain checker". You can prove that all clock domain crossing following a pre-determined synchroniser etc etc. Assertion checker from the company 0-in has a "semi-formal" checker... Many new inventions of the use of formal technique are coming out from the EDA start-up. Regards, Eng Han www.eda-utilities.com Stan wrote: > > Also, formal verification of hardware is much easier than of software > > because hardware is simpler in its nature. > > The only formal verification for hardware simply tests equivalence between > two representations of the same design, it does not prove any kind of > correctness; don't let the vendors tell you any different! In the software > world, it would be analagous to a tool that verifies that an executable does > exactly what the source does, that is, the compiler does not have bugs. > > -StanArticle: 45730
Hi, I know this comes up periodically, but does anyone (from Xilinx) have guaranteed skew figures for the GSR net in Virtex-E and Virtex-2? The datasheet lists figures for TGSRQ, which I think is the delay from the GSR input of the startup block to the Q outputs of flip flops, but it does not give any skew figures. TGSRQ represents an upper bound for the skew (since the minimum delay can't be less than zero) but I think the skew will be much less than this. Old c.a.f posts have mentioned figures of "a few ns". Thanks, Allan.Article: 45731
The Spartan-II datasheet "Spartan-II 2.5V FPGA Family: Introduction and Ordering Information" Page 3, Table 3. http://www.xilinx.com/partinfo/ds001_1.pdf The intro data sheets are the first of four for each family of devices and are much smaller than the detailed functional data sheets. Maciek wrote: > Hi ! > I'm reading documentation and i can read detail description of spartan > pin-outs but I need just simple information - how much available i/o pins > can be located in xc2s100 when i use pq-208 and fg-256 - i need just like > that. Thanks for your help. > Regards, > MaciekArticle: 45732
"Vincent JADOT" <vjadot@digitalsurf.fr> schrieb im Newsbeitrag news:3d4a9f4a$0$211$4d4eb98e@read.news.fr.uu.net... > Hi, > > What's the equivalent of ALTERA EP20K200-2X (APEX 200 000 gates), on XILINX > device? it's a VIRTEX device with 200 000 gates? > > > And what's the equivalent of XILINX XC2S100-5 (SPARTAN2 100 000gates), on > ALTERA device? it's a FLEX device with 100 000 gates? > > I want to know it, because i made a benchmark study on signal processing > between NIOS(on APEX dev. board) and MICROBLAZE(on SPARTAN2 demo board) > softcore and i want to relativize with chi's performances. If you want to compare the performance of two softcore processor, why do you need the gatecount? -- MfG FalkArticle: 45733
"Andrzej Ekiert" <reply@to.invalid> schrieb im Newsbeitrag news:aidut6$ati$1@news.tpi.pl... > Hi all, > > I'm trying to make Spartan II BlockRAM clocks active on falling edge. When > I simply invert the clock (eg: clk_inv <= not clk, using VHDL) the This is the right way to do this. > implementation tool (WebPack + XST) complains about non clock connections > of the clk signal. I'm afraid it could impact the design performance or add This is another problem. You are using the clock signal as an data input for other logic functions, or you route it to an output pin. Thats why the tools warn you. The clock inversion for the BRAM will work fine. -- MfG FalkArticle: 45734
Falk wrote: >> I'm trying to make Spartan II BlockRAM clocks active on falling edge. >> When I simply invert the clock (eg: clk_inv <= not clk, using VHDL) > > This is the right way to do this. Great ! >> implementation tool (WebPack + XST) complains about non clock connections >> of the clk signal. > > This is another problem. You are using the clock signal as an data input > for other logic functions, or you route it to an output pin. The confusing part is that I neither use this signal as ordinary data, nor route it to any outputs. To check it out I removed the 'not' from clock line and the warning disappeared. It doesn't matter whether I declare a signal clk_inv, or put "not clk" within port map during RAMB4_S#_S# component instantation - I get the warning whenever the clock is iverted. Should I worry ? Thank you for your help. -- :wqArticle: 45735
I think reposting this question at news:comp.arch.embedded sounds more appropriate, since that newsgroup handles more system specific issues, but to answer your question, if you are going to count something with a timer (Presumably within an FPGA), and the timer's counting has to be accurate, you should not rely on PCI's clock. That's because at least for 33MHz PCI, the clock can be stopped due to power management reasons, at least in theory. I am told that almost no PCI system actually does actually stop the clock, but since the specification says for 33MHz PCI that the clock can be stopped, you should never rely on it for counting purposes. So, if you want to count something accurately, you sound have your own clock oscillator on the PCI card. Kevin Brace (In general, don't respond to me directly, and respond within the newsgroup.) Speedy Zero Two wrote: > > Hi group, > I have a PCI design which requires the addition of using the interrupt. > The operation is that the software will write a value to a down counter > which when it reaches zero an interrupt is generated. > Can anyone help as to explain the actual operation and possible problems > associated with the calibration of the "timer" > This delay is used in software timing so I would be interested in any > help/advice > > Thanks in advance > DaveArticle: 45736
Hi Comp.Arch.FPGAers, I am working on my master's thesis and in it I am trying to compare modern architectures, Raw (What my group does and I built part of), FPGAs and ASICs for some applications. To properly do this comparison I need to get some area numbers for Xilinx FPGAs. I have scoured pretty heavily and surprisingly I have had a hard time figuring out even the total die size of any current Virtex II FPGA. This surprised me because the overall die size doesn't tell anything secret, or at least info I couldn't get from simply disassembling a Virtex II part. Anyways I was wondering if anybody has area numbers for the die size of a Virtex II part(Any one will do because I will normalize it)? Ultimately what I really want is the area in mm^2 of a Slice/CLB on this architecture. I am most interested in those numbers because I want to try to mitigate area expansion caused by block RAMs. Unfortunately even Slice/CLB size is not completely accurate because of area caused by the switches but I can try a fudge factor. Oh, some of you may be wondering why I want Virtex II specifically, well the comparisons I am making are all in 0.15um and I have heard that the UMC process that Xilinx is using for these is very similar to the 0.15um that we are using with IBM, and thus a fair comparison. But if anybody knows of these area numbers for a Virtex-E that would also be appreciated. Also if anybody knows of a good document with these numbers, all pointers will be appreciated, and rewarded with some cookies, yes I am willing to mail cookies to get accurate numbers for my thesis. Thanks, David WentzlaffArticle: 45737
Andrzej Ekiert <treikeSSSPAAAMM@zeus.polsl.gliwice.pl> wrote in news:aieg9j$63$1@zeus.polsl.gliwice.pl: > Falk wrote: > >>> I'm trying to make Spartan II BlockRAM clocks active on falling >>> edge. When I simply invert the clock (eg: clk_inv <= not clk, using >>> VHDL) >> >> This is the right way to do this. > > Great ! > >>> implementation tool (WebPack + XST) complains about non clock >>> connections of the clk signal. >> >> This is another problem. You are using the clock signal as an data >> input for other logic functions, or you route it to an output pin. > > The confusing part is that I neither use this signal as ordinary data, > nor route it to any outputs. To check it out I removed the 'not' from > clock line and the warning disappeared. It doesn't matter whether I > declare a signal clk_inv, or put "not clk" within port map during > RAMB4_S#_S# component instantation - I get the warning whenever the > clock is iverted. > > Should I worry ? > > Thank you for your help. > Hi, IIRC spartans don't have inverting buffers for clk inputs, but I'm not so sure, you should check the doc...Anyway, your problem may be that onr part of the design is clocked on rising edge, and the other on falling edge. The 'good way to implement this is through a clkdll, and the use of both CLK0 and CLK180 outputs, each routed to a specific BUFG hth Sylvain YonArticle: 45738
From what I understand, it won't damage the part, but it will change your input switching levels somewhat. I had a LVDS design that was input only on the LVDS. I layed the whole board out with Vcco = 3.3v, as the fpga went thru ppr without any errors. Later I had to change one signal to an I/O. Now the S/W informed me that LVDS has to be 2.5v. So, for a while, I was running a bank with LVCMOS2 and LVDS that was physically connected to 3.3v...It worked just fine, and I was assured by this newsgroup that I would not dammage the virtexE chip. However, I later changed the one LVDS I/O to LVPECL and all the other logic in the bank back to LVTTL and I think thats a better fix. Dan "Rudolf Usselmann" <russelmann@hotmail.com> wrote in message news:d44097f5.0208011755.3ef7dac@posting.google.com... > Anybody ever successfully modified Vcco beyond the > recommended standards ? > > For example using 2.7V instead of 2.5V for LVCMOS2 IOs ? > > Thanks, > rudiArticle: 45739
yangyugang@263.sina.com (yanggg) writes: >I have a idea that I can design a chip which can recive the ethenet >data from >switcher.After get the frames,I can get the payload.Then encapsulate >the payload in E1 format.Then trans them in telephone lines.In the >remote ,there is a same divice.It can recived the data and change into >ethenet frames and trans to the switcher.If the chip is duplex,the >connection between two nets is established. The scope of ethenet can >be greatly enlarged. This is usually done using a router to keep the local traffic local, though it could be done with a bridge. Next is the CSU/DSU to interface between the serial data stream and the E1 (T1 in USA) line. Most likely the two functions should stay separate. The CSU/DSU has some strange voltage requirements which don't fit on a chip very well, and there are readily available already. Using a router (preferred) or bridge keeps local traffic from going through the link, and buffers what does so that it can match the data rate. An IP router on a chip might still be a reasonable project. Probably with external memory for the buffer, though. Try the tcp-ip or ethernet newsgroup for more ideas. -- glenArticle: 45740
Hi, I get the following error while running modelsim 5.5e (from altera). # ** Warning: Only one of OutEnab or WE should be used! # Time: 0 ns Iteration: 0 Instance: /smg2000_vhd_tst/tb/we4_ram7/lpm_ram_io_component # ** Fatal: Index 8 is out of range 7 downto 0. # Time: 0 ns Iteration: 0 Instance: /smg2000_vhd_tst/tb/we4_ram7/lpm_ram_io_component # Fatal error at Quartus2.0(C:/Modeltech_ae/win32aloem/../altera/Vhdl/src/220model/220model.vhd) line 2925 # It also tries to open a source file and gives the following error in the source file window. Cannot find Quartus2.0 (C:/Modeltech_ae/win32aloem/../altera/Vhdl/src/220model/220model.vhd)Source unavailable. Earlier before this error, my code ran without any problems. Unfortunately my system crashed and henceforth I have been getting this error. Does anyone have any clues as to what may be wrong here. Thanks, PrashantArticle: 45741
.
***********************************************************************
* CALL FOR PARTICIPATION *
* 15th Annual IEEE International ASIC/SOC Conference *
* September 25-28, 2002 *
* RIT Inn and Conference Center, Rochester, New York *
***********************************************************************
Driven by the rapid growth of the Internet, communication technologies,
pervasive computing, and wireless and portable consumer electronics, Sys-
tems-on-Chip (SoC) have become a dominant issue in today's ASIC industry.
The transition from traditional Application-Specific-Integrated-Circuits
(ASIC) to SoCs has created new challenges in Design Methods, Design Tools,
Design Automation, Manufacturing, Technology and Test. The ASIC/SoC Confer-
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applications. The 2002 Conference will offer three days of technical papers
and a full day of technical workshops. The IEEE Circuits and Systems Soci-
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GENERAL INFORMATION
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tions will be available for $79.00 a night at the RIT Inn. Rochester, the
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KEYNOTE SPEAKER
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PLENARY SPEAKER
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BANQUET SPEAKER
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Commercialization, "New Technologies That Can Support Human Exploration
of Space"
TECHNICAL SESSIONS
ASIC/SoC 2002 will cover 25 technical sessions comprised of 89 full-papers
on SOC DSP Techniques, Multimedia Audio, Memory and Processors, SOC Plan-
ning and Verification, Data Converters, DSP Power Modeling and Management,
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nects. 32 posters will be presented in the poster session.
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Please visit the Conference web site at http://asic.union.edu to review
the advanced program and register. Contact the ASIC/SoC Conference office
at 301-527-0900 x104 for additional conference information and corporate
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General Chair Technical Chair Technical Co-Chair
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Pubs/Publicity Chair Steering Committee Chair Workshop Chair
Richard Auletta Thomas Buchner Ram Krishnamurthy
LSI Logic IBM Boblingen Lab Intel Corporation
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Sponsored by the IEEE Circuits and Systems Society
************************************************************************
Article: 45742Falk Brunner wrote: > > The easiest way to this goal. Instanciate distributed RAM, use a simple > address mux to toggle between normal and "diagonal" address access and you > are done. > All other attemts to write a VHDL that will recognized by the compiler is > just academical playaround. I figured as much. > > Why not? You can only achieve good performance/density when you use the > special features of the target IC. You mean the people who write VHDL books don't actually create any targets? :-) Thanks, it's nice to hear that because that's what I figured when I started trying to learn this stuff. -- Mike Rosing www.beastrider.com BeastRider, LLC SHARC debug toolsArticle: 45743
David Wentzlaff <wentzlaf@catfish.lcs.mit.edu> wrote: : Hi Comp.Arch.FPGAers, : I am working on my master's thesis and in it I am trying to : compare modern architectures, Raw (What my group does and I built part : of), FPGAs and ASICs for some applications. To properly do this : comparison I need to get some area numbers for Xilinx FPGAs. I have : scoured pretty heavily and surprisingly I have had a hard time figuring : out even the total die size of any current Virtex II FPGA. This surprised : me because the overall die size doesn't tell anything secret, or at least : info I couldn't get from simply disassembling a Virtex II part. : Anyways I was wondering if anybody has area numbers for the die : size of a Virtex II part(Any one will do because I will normalize it)? : Ultimately what I really want is the area in mm^2 of a Slice/CLB on this : architecture. I am most interested in those numbers because I want to try What about X-Raying the packaged chip, perhaps at a friendly dentist? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 45744
Hi, Model checking is used a lot and it's best to combine it with standard verification methods (random and directed tests using simulation). Some cases, for example: `is there a combination of inputs that leads to deadlock?', can be verified using model checking in the easiest way. Cadence SMV is a kind of model checker used for that purpose. regards, Domagoj Babic domagoj (et) engineer.com "ehml" <ehml@pacific.net.sg> wrote in message news:3D4AAC45.FFC52B16@pacific.net.sg... > Hi Stan, > > You might not aware that equivalent checker is just one type of formal > verification. > > Formal verification simply means to proof something formally, or using > mathematics. > > One type of formal verification is "formal model checker". You define a certain > properties, and some constraints, and then you proof it using "formal model > checker". An example is that every request must be acknowledge within 5 cycles. > > Another type of formal verification is "clock domain checker". You can prove > that all clock domain crossing following a pre-determined synchroniser etc etc. > > Assertion checker from the company 0-in has a "semi-formal" checker... Many new > inventions of the use of formal technique are coming out from the EDA start-up. > > Regards, > Eng Han > www.eda-utilities.com > > Stan wrote: > > > > Also, formal verification of hardware is much easier than of software > > > because hardware is simpler in its nature. > > > > The only formal verification for hardware simply tests equivalence between > > two representations of the same design, it does not prove any kind of > > correctness; don't let the vendors tell you any different! In the software > > world, it would be analagous to a tool that verifies that an executable does > > exactly what the source does, that is, the compiler does not have bugs. > > > > -Stan >Article: 45745
Ray Andraka wrote: > It sounds like Leo is producing the correct construction then. Floorplanning will get it to just about > 200 MHz in the -4. Unfortunately, that's about all you'll get out of the carry chain logic in V-2. If > the numbers offered for Stratix turn out to be true, I think it may be faster than the V-2 for arithmetic. > Ray, Do you have any quantitative idea of the in-the-fabric multiplier slow-down caused by the slower V-2 carry chain logic ? i.e. if it were as fast as the V-E what speed would you get ? [I think the V-2 -4 speed grade is supposed to be ~equivalent to the V-E -7]. I strikes me that the problem may be the move in the V-2 to "fully buffered" routing which IIRC was designed so that the ``push the big green button'' merchants could get reasonable results without all that messing about with Floorplanning and RPMs. IMHO Xilinx really should do something about this otherwise they're in danger of losing one of their major historic advantages over Brand-A parts.Article: 45746
I faced a similar problem: I wanted to interface a Spartan II to a part that operated using non-standard "LVCMOS" 1.8 V logic levels. I solved the problem by dedicating an IO register bank to the oddball part, defined it to be GTLP, put pull-ups to 1.8V on the FPGA outputs, and used a quick-'n-dirty 1.2V source based on a resistor divider & op-amp buffer to supply the slice voltage for the input IOs. It worked like a champ. I'd suspect that for your application you could just boost the IO ring supply to 2.75V and you'd be stylin'. However, if you are really nervous, you could use my approach of pull-ups & slice voltage source. That gives you the max control over your logic levels. Finally, I suspect that you would learn a lot -- and feel a little more secure -- by doing a little SPICE modeling of the IOs. I'm sure that you can get IO models from Xilinx. Stuart Rudolf Usselmann <russelmann@hotmail.com> wrote: : Hi ! : I'm trying to interface a device with 2.75V IO to an : Xilinx Virtex/Spartan 2e device. The specific characteristics : of this device are: : Min Max : VOH 2.2 2.75 : VOL 0 0.6 : VIH 1.93 2.75 : VIL 0 0.5 : The FPGAs offer a LVCMOS2 IO standard that comes VERY close. : Specifically the Spartan2E data sheet says: : Min Max : VOH 1.9 : VOL 0.4 : VIH 1.7 2.7 : VIL 0.5 0.7 : Cross referencing these two tables results in only two : slight mismatches: : Xilinx VOH Max is 1.9V - My Device VIH Min is 1.93V : and : Xilinx VIH Max is 2.7V - Device VOH Max is 2.75V : As subtle as these differences are, I must make find a : solution around that problem that will guarantee that : the equipment we are building works ! : The first thing that came to my mind was to rise the : IO Ring Voltage (Vcco) from 2.5V nominal to 2.7V nominal. : Any suggestions/recommendation/real life stories ? : Thanks a million ! : rudiArticle: 45747
"Sylvain Yon" <sylvain.yon@sbcglobal.net> schrieb im Newsbeitrag news:TZA29.3$f52.2@newssvr19.news.prodigy.com... > IIRC spartans don't have inverting buffers for clk inputs, but I'm not so > sure, you should check the doc...Anyway, your problem may be that onr Spartan-II has local clock inversion capability for BRAM and every Slice. > part of the design is clocked on rising edge, and the other on falling > edge. No, this should not cause this warnig. > The 'good way to implement this is through a clkdll, and the use of both > CLK0 and CLK180 outputs, each routed to a specific BUFG No, why using (wasing) two BUFGs when one is sufficient. This is only neccessary for REAL high speed designs with Double-datarate stuff. (300MHz++) -- MfG FalkArticle: 45748
Since replicating the specific processor, http://www.ubicom.com/pdfs/products/sx/processor/SX-DDS-SX2028AC-16.pdf would be a daunting task for any design course, I'd recommend not pursuing a replacement of the MCU with the FPGA but instead interfacing the FPGA to the MCU where you can trade off between the software - which you should be able to get from Carnegie Mellon University once the students start returning in droves in a month or so - and the added functionality of the FPGA. The XC2S50 simply might not be able to replace the Ubicom MCU but it might do some nice things as a supplement. Good luck. dross wrote: > Helle all: > > In CMUcam Vision Sensor(http://www-2.cs.cmu.edu/~cmucam/),there is a > fast MCU runing at 75M. I want to know if can i use a FPGA replace that MCU? > Because I want to make a project use a FPGA (XC2S50 xilinx) in our > design course ,and i think this is a good idea. > > By the way,who can give me CMUcam's firmware source.Just mail to > zjuzhou@yahoo.com.cn > (I write a email to them,but there is no reply) > > Thank you.@_@Article: 45749
Lasse Langwadt Christensen wrote: > hmm... just for fun I tried a very simple example; > [snip - example] I did the same, except the language used was VHDL, and got the very same result. > looking in the fpga editor it does use the blockrams buildin clk inversion > ... and this is the good news :-) Well, I think I'll just have to bear with an ugly warning. -- :wq
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