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Hi gurus, Would you tell me the subtle defference between "flip flop" and "register"? Best Regards, DarylArticle: 45976
I have solved the problem in Translating. But there is another question When I continue to map.ISE informs me that :" ERROR:MapLib:292 - I pin of ORCY symbol "and_chainx1/orcy_inst" (output signal=carry<1>) must be driven by constant 0 or another ORCY. ERROR:MapLib:294 - CI pin of ORCY symbol "and_chainx1/orcy_inst" (output signal=carry<1>) must be driven by MUXCY." But I have checked my source code,and I pin and ci pin both match the term that ISE informs me. What's wrong? Thanks. "Rick Filipkiewicz" <rick@algor.co.uk> wrote in message news:3D579896.2FEB5CC@algor.co.uk... > > > Yx Jiang wrote: > > > > > <snip> > > > > > What's wrong with the design? > > > > Thanks, > > Yx Jiang > > You need to find out where ``AND_CHAIN'' is coming from. Its either: > > (1) A `primitive' being generated by your synthesiser and output into an EDIF > file. > > (2) A `black box' module of your own for which NGDBUILD cannot find an EDIF or > .nmc file. > > In case #1 the reason is most likely that you are synthesising to the wrong > device, or no device at all. > > If that doesn't help then post the source code for the combined mighty > intellects of the NG to examine. > >Article: 45977
I'm not quite understanding the difficulty of using an FPGA for unloading this ADC. The ADC's two 8-bit buses with a forwarded clock at 500 MHz aren't too much different from the physical layer specs of some of the new I/O standards like RapidIO or HyperTransport. There are several of these cores implemented in FPGAs from more than one FPGA vendor, so it's got to be at least do-able. I can't speak to the ease/difficulty of implementing this in a Xilinx device, but it's pretty straight-forward in any Altera device since the Apex 20KE. Each data line comes into the FPGA at, say, 500 MHz and goes into it's own SerDes. The SerDes output is 8-bits wide at 62.5 MHz, essentially making a 64-bit word when you line then all up. Since the data sample values are now spread out across the eight 8-bit words, you'll need to shuffle the bits around to put bits 0,8,16,24,32,40,48,56 together for one sample, 1,9,17,25,33,41,49,57 for the next, etc. However, since you're working at 62.5 MHz at this point, the shuffling isn't rocket-science. -Pete- Ray Andraka <ray@andraka.com> wrote in message news:3D557628.59972223@andraka.com... > The LVDS specs on some of the faster chips will handle that, but the > internal design just to get the data reliably onto the chip is not > trivial, and involves treating the data as DDR data. VirtexII would make > this easier for you, but still a major PITA to pull it off. We did a > similar design earlier this year with an Atmel 8 bit 1GS/sec converter > plus a sister chip (also Atmel) that packed 4 samples into one 32 bit > word and transferred that at a much more manageble 240 MHz into a virtexE > over LVDS lines. That was a lot easier than trying to run at the hairy > edge using interface specs that were not directly compatible.Article: 45978
I'm a (soon graduating!) student at Georgia Tech studying computer engineering. GT uses altera products for several classes, so I've used those plenty....but I've seen very little of how FPGAs are really used in industry. Also I've had no experience with non-altera FPGAs because I believe my school has some sort of deal with altera..... Can someone point me to a text, or website that contains information about real world applications of FPGAs? Thanks, --buddy -- -----BEGIN GEEK CODE BLOCK----- Version: 3.12 GE d- s:- a-- C+++ UL P++++ L+++ E- W+ N++ o-- K- w-- O---- M- V- PS-- PE Y+ PGP t+ 5 X R tv+ b DI++++ D G e h r++ y- ------END GEEK CODE BLOCK------Article: 45979
> Would you tell me the subtle defference between "flip flop" and "register"? Flip-flop is the generic term which describes all storage elements whose output changes for a specific change at its inputs. A register is a specific type of flip-flop whose output takes on the value of its data input when there is a appropriate transition on it's clock input. The register is a subset of the type flip-flop. eg: D type flip-flop - output takes on input when clocked - a (single element) register. Toggle type flip-flop - output changes state when clocked _and_ it's 'toggle' input is active. I've still to decide whether an unclocked storage element (a transparent or set-reset latch) is a member of the flip-flop type :-) It's also in usage, if I wanted to clean up the timing of a signal or delay it I would say I was registering it, if I wanted to perform a logical task which required a couple of storage elements, I probably call them flip-flops. HTH -- fredArticle: 45980
Check out http://www.amphion.com/e-d.html Amphion's AES solutions are all generic, extremely highperformance and can be targetted at any technology. We also have an Export license for the product. Contact info@amphion.com for more information and pricing. Regards, Iain Adam Elbirt <aelbirt@nac.net> wrote in message news:<3D53C62A.9050008@nac.net>... > Andrew, > > Is it correct to say that those throughputs are for ECB/Counter modes? > Do you have anything that runs in CFB or the newest AES mode of operation? > > Adam > > Andrew wrote: > > >Krishna, > > > >I have written a Rijndael encryption/decryption core which supports VirtexE > >parts. The core can operate in pipelined and semi-pipelined modes, (giving > >different performance/area gains). The pipelined version can give a > >throughput of over 6 GBits/sec on a VirtexE-6, and the semi-pipelined > >version runs at 776 MBits/sec but is a fraction of the size. The core comes > >with wrappers to help integrate it into your design. > > > >If you need any more info, give me a shout. > > > >best regards > >Andrew Dunlop > >Design Engineer > >Celoxica Ltd. > >andrew.dunlop@celoxica.com > >www.celoxica.com > > > > > >"kkps" <kkps@rapid5.com> wrote in message > >news:c6efc5c9.0208050742.187cb4de@posting.google.com... > > > >>Hi all, > >> > >>I need to choose an AES (rijndael) IP core to use in Xilinx VirtexE. > >>There is a wide perplexing selection of core providers on the > >>internet. Does anybody have any recommendation regarding who is the > >>best (performance & cost)? > >> > >>Also, I would highly appreciate it if anybody who has used an AES core > >>from some core provider can share their experience on: > >> > >>1. Did it work? > >>2. Was it easy to use? > >>3. How was the technical support? > >>4. Do you recommend it? > >> > >>Any information will be highly appreciated, > >>Krishna > >> > > > > > > > --Article: 45981
Hi, So basically u r saying is that , it is not possible to implement two applications without downloading them seperately one after the other, that basically means , it is kind of impossible to reconfigure dynamically to switch to other application at run time. Thanks, Ram. "reply in the newsgroup" <deepfry.a.spammer.today@abuse.org> wrote in message news:<aj9mtc$beh$1@slb6.atl.mindspring.net>... > Then you'll need a separate simulation for each configuation. > I was assuming that you were using only one configuration, > but not initializing all the sections in tests that weren't using > them. > > "Ramakrishnan" <rxv20@po.cwru.edu> wrote in message > news:15cf85fc.0208121403.b469915@posting.google.com... > > Hi, > > I really didn't understand what you meant in your post. Actually > > the number of memories for each and every application varies in my > > architecture, for example bandpass filter implementation required 12 > > memories of 4 elememts whereas cosine filter needed only 10 memories. > > > > So every time a new application is to be implemented, the whole > > architecture would have to some how be reset to reflect the exact > > number of memories. > > > > Thanks, > > > > Ram. > > > > "reply in the newsgroup" <deepfry.a.spammer.today@abuse.org> wrote in > message news:<aj8mlp$i87$1@slb7.atl.mindspring.net>... > > > "Ramakrishnan" <rxv20@po.cwru.edu> wrote in message > > > news:15cf85fc.0208120735.1884e326@posting.google.com... > > > > Hi, > > > > I have a few questions with regard to Xilinx 4000 series FPGA. > > > > > [deleted] > > > > The problem i think would like in the fact that some of the > > > > applications that i choose to implement would use fewer memories in my > > > > VHDL architecture than others. So how would i be able to overcome this > > > > problem. > > > > > > > Then why not create a file for each memory not used in all the tests, > that > > > loads this memory with random data, and use the resulting files to load > any > > > memory not used in the current test so that all the memories end up > > > loaded?Article: 45982
The previous poster was dead on about the costs of an ASIC and I wish to add one more thing that is an issue. Much of the FPGA IP people buy from Xilinx is already compiled and in bitstream form and relatively cheap! The thing is, Xilinx did not intend you to take this stuff to ASIC behind their backs. If you check your license agreements, I believe that it mentions something about that. So be carefull if you are using an Asian conversion company to reverse engineer that Xilinx IP to standard cell logic gates in order to save a buck. Digital signatures can still be implanted into the IP and if your ASIC is very profitable, someone might do some reverse engineering on your product and then want royalties on it which might not make it so profitable anymore. I am not trying to scare anyone and I am not employed or connected with Xilinx in any way, just read your license agreement and keep everthing legal. The FPGA industry does a LOT of subsidizing to get you your cheap tools and stuff, but when you go to make an ASIC, all bets are off and the price can skyrocket. And you don't want to do anything illegal in chip design realm because it always seems like the legal "Hammer of God" can come out of nowhere when you least expect it. (Just look at the money spent in lawsuits between the EDA companies and even the FPGA companies over disputes!) The good news is that many of the FPGA companies can help out in some areas of turning big projects into an ASIC through partners such as Xilinx/IBM for the Power PC embeded stuff. Sam On Tue, 13 Aug 2002 06:36:47 GMT, spam_hater_7@email.com (Spam Hater) wrote: >Reala, > >For the library, you have to contact the fabrication house and find >out which ones they have certified. > >For example, with TSMC or UMC, you can use Artisan or Virtual Silicon. >There are dozens of FAB houses, and dozens of library makers. > >For synthesis, you can use Synplicity, Synopsys, or Ambit. There's >probably more; those are the ones I have used. Just make sure the >library has support. > >It's a 3-piece puzzle, that involves substantial time to solve. This >is a non-trivial task. It takes work. No sane person is going to do >this much work for free; serious money is usually involved. > >And you're probably unaware of the costs involved. I can put together >a decent FPGA development station for $1,300.00 - that includes the >prototype board and all the software. (Actually, you can build a >Cypress development station, including HDL, for under $500.) > >The last ASIC I did, we used $2,000,000.00 worth of layout software, >simulators, and synthesizers. And the 1st chip run cost $250,000.00 > >The FPGA maker makes their money on the chips; they practically give >the software away. > >Yes, there are cheaper ways to do it. Take a class in ASIC design at >a local university, and see how they do student runs. > >SH7 > >On Tue, 13 Aug 2002 14:11:55 +0800, "Reala" ><manfield.chow@scoreconcept.com> wrote: > >>Hi SH7, >> >>Thank you for your reply. >>Yes, the questions are similar. >>I ask this question again because I find that the free systhesis tools >>always target to FPGA. >>If I design the chip by FPGA, then I change it to ASIC. I can find some >>vender to help me for conversion. >>However, if I want to design the chip directly. I guess that it is something >>difficult. >>(eg. what systhesis tools i can you? As the target is not a FPGA, what >>library used for systhesis?) >> >>Reala >> >> >>"Spam Hater" <spam_hater_7@email.com> wrote in message >>news:3d57e652.6164760@64.164.98.7... >>> >>> Hi, >>> >>> You asked this same question on 07/22/2002 >>> >>> What's wrong with the answers you got then? >>> >>> SH7 >>> >>> >>> >>> On Mon, 12 Aug 2002 11:32:31 +0800, "Reala" >>> <manfield.chow@scoreconcept.com> wrote: >>> >>> >Hi, >>> > >>> >I wrote a verilog code. Then, I ran Modelsim to verify the design. >>> >If I implement the design by Altera, I can use LeonardaSpectrum for >>> >synthesis. >>> >However, i want to implement the design by ASIC. What >>> >information/software/library needed for this approach? Thank you. >>> > >>> >Reala >>> > >>> > >>> > >>> > >>> > >>> >> >> >> >> >Article: 45983
There is no better place to look for real world FPGA applications than the vendor's websites themselves, i.e. try Xilinx under "success stories" at http://www.xilinx.com/company/success/index.htm In the "old days" (more than 10 or 15 years ago especially), custom digital logic was implemented with large numbers of TTL or CMOS ICs (gates, registers, counters, etc). Nowadays, either ASICs (custom ICs) or FPGAs are used to reduce the package count down to just a few very dense packages. ASICS cost less in large volumes but commit you to a fixed implementation which had better be right, but FPGAs are more practical for smaller volume jobs and allow changes to the design even in the field. Buddy Smith wrote: > I'm a (soon graduating!) student at Georgia Tech studying computer > engineering. GT uses altera products for several classes, so I've used > those plenty....but I've seen very little of how FPGAs are really used in > industry. Also I've had no experience with non-altera FPGAs because I > believe my school has some sort of deal with altera..... > > Can someone point me to a text, or website that contains information about > real world applications of FPGAs? > > Thanks, > > --buddy > >Article: 45984
The output standards are based on the "standard loads" as specified in the Xilinx data sheets. In order to determine a different value, an estimation can be made based on the data sheet values for output loading change in ns/pF but the best way to determine the real delay is to run the interface through an IBIS simulator to extract the actual times versus the "standard load" conditions. Anjan wrote: > Hi > > can anybody tell me what is the assumption that xilinx trce makes wrt > to the external capacitance when giving the pad to pad delay. > AnjanArticle: 45985
"Kolja Sulimma" <kolja@bnl.gov> schrieb im Newsbeitrag news:25c81abf.0208130156.679ce799@posting.google.com... > Hi! > > For a SOC I use both ROMs made of Block-RAMs and dual-ported > Block-RAMs that are preloaded at reset. > Currently I use CoreGen to generate these building blocks. > > I use Xilinx Foundation 4.1i XST and would much prefer to use inferred > Block-RAMs. I know the Language Assistant VHDL examples for inferring > Block-RAM, but they do not show how to preinitialize the RAMs. To initialize them for simulation, you must use the INIT generics. To provide these init values to the P&R tools, you must use the INIT attributes. -- MfG FalkArticle: 45986
Last time I checked, an RBT file was 1 bit per byte. It was an ASCII "0" or "1". I wouldn't call the BIT file "compressed", just a better encoding. You can do better still if you do real compression. I've always assumed the main advantage of the RBT file format is that you didn't have to worry about which end of the byte the first bit was stored in. If you are writing your own code to wiggle the configuration signals, just read the RBT file with a preprocessing program to make whatever internal format you like. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 45987
I have a circuit with an Altera Max7128 CPLD. On the same board there is a programming circuit using a 74HC244 (exactly as per ALTERA byteblaster specs). The whole thing connects to a parallel port on the PC, which is running the latest MAX IDE. The problem is, when trying to program the device (EPM7128SLC84-15), the IDE returns with various errors such as "device not in socket", "wrong version of MAX PLUS". However, when I place my finger on some of the (unconnected) I/O pins (he ones nothing to do with programming), the programmer actually starts and runs. It works sometimes, but other times it gives verify errors. i.e. some of the locations were not programmed. This of course is driving me nuts, I can imagine the programmer is not reading the data out correctly hence the misinterpreted IDE messages. But why do I need to put my finger on the unconnected I/O pins?, how can this affect the programming? BTW, exactly the same circuit, when programming a 7064SLC44-10 works perfectly OK. I have also tried the 1k resistors to gnd and to +5 described in the Altera JTAG programming documentation, to no effect!!! Any ideas anybody??? Thanks in advanceArticle: 45988
Nicholas C. Weaver wrote: > Thanks. Although this is what we are already doing, the CEs are being > added/inferred by symplify's mapping process. That may be because the primitive logic elements have clock enables. Consider letting the synth handle the unused inputs rather than forcing attributes or editing the netlist. -- Mike TreselerArticle: 45989
This is a multi-part message in MIME format. --------------0EAAC1B1418A467ED11B9511 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Vikram Ensure that you have added the vcd nets and run the simulation long enough to take into account the average frequency over the whole simualation. If you still think that it is a bug then please contact the hotline with a testcase showing the issue and we can fix it. John Vikram Chandrasekhar wrote: > Hello John, > Thank you for replying :) > Glad that there is someone who is trying to answer my query!! > I still have my issues though!! > Well, XPower does not seem to have the following good traits: > > a). It cannot recompute the node transition frequencies (that it has > procured from a .vcd file) when I change the clocking frequency in the > Xpowwr fields. > > b). It does not seem to have the capability of computing the activity > factor of a gated clock. The gated clock is assigned the same toggle > frequency as that of the input clock !! > > I have started manually computing the power dissipation based on the load > capacitances reported by it. > > Thanks > VikramArticle: 45990
This is a multi-part message in MIME format. --------------B8615538F672B44DE2085F1C Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Hi Vikram I did not make clear that you can enter any frequency you like into the XPower GUI. I.e., You do not have to rely on the simulation. Just find the input signal to the FPGA. John Vikram Chandrasekhar wrote: > Hi everyone, > I am employing clock-gating on a Virtex-II FPGA using the BUFGMUX unit, > in order to turn off idle functional units, for reducing dynamic power > dissipation in my design. > > However, when I use XPower (the power estimator tool offered by Xilinx) to > estimate the power dissipation, it does not report the correct activity > rate for the gated clock. Infact, the switching frequency reported by it > is the same as the global ungated clock. Does it mean that it does not > take the activity rate of a clock into account? Is there any way that I > can make Xpower understand the clock being gated?? > > Any help would be greatly appreciated. > Thank you > Vikram Chandrasekhar.Article: 45991
Kolja Sulimma wrote: > For a SOC I use both ROMs made of Block-RAMs and dual-ported > Block-RAMs that are preloaded at reset. > Currently I use CoreGen to generate these building blocks. > > I use Xilinx Foundation 4.1i XST and would much prefer to use inferred > Block-RAMs. I agree. > I know the Language Assistant VHDL examples for inferring > Block-RAM, but they do not show how to preinitialize the RAMs. Consider inferring separate rom and ram devices. You might want to recall your defaults without doing a reset. -- Mike TreselerArticle: 45992
My design is:
--xc18v04(2nd)--xc18v04(1st)--fpga-
|
-----------------------------------
And the daisy chain is Jtag & Master
Serial.Jtag mode can work well.But
some wrong with Master Serial Mode:
1,promgen generates two split file
demo000.mcs&demo001.mcs. and which file match the 1st Prom.
2,whichever method(jtag|Master) I use for config.but fpga can't work well.
3,Please Email me for your convenience!Thanks muck!
Article: 45993Have a look at Xilinx's Xcell Journal issue 41, page 78, "Giga-Sample DSP Board" for a MAX104 based design. This is on the Xilinx web site if you don't get their journal. Also see: http://dustbunny.physics.indiana.edu/~paul/hallDrd I'm using an SPT7721 with an XC2S50. Paul Smith In article <gkqalukcqfln3qo9b699jebbifmnj1kh25@4ax.com>, John Larkin wrote: >Hi, > >I'm thinking about grabbing a bunch of samples of a burst analog event >that will last maybe 100 ns or so. Maxim makes an ADC, the MAX104, >that samples up to 1 GSPS and outputs alternate samples on two 8-bit >PECL ports. So, is there any chance that the ADC data could be stuffed >directly into an FPGA at, say, a sample rate of 800-1000 MHz, implying >two 8-bit data ports running at 400-500 Ms/s each? We prefer the >Xilinx parts, but would be curious if any of them, or somebody else's >parts, can input data this fast. > >The application here would be sampling the time profile of a laser >pulse and applying an algorithm (maybe in the FPGA itself) to optimize >something the customer cares about. > >Thanks, > >John > >Article: 45994
"Daryl" <e-engineer@eastday.com> wrote in message news:ajap1v$19jj2j$1@ID-155928.news.dfncis.de... > Hi gurus, > > Would you tell me the subtle defference between "flip flop" and "register"? > > > Best Regards, > > Daryl Daryl, You have asked a very good and astute question. No doubt you will get several answers, but here's my take. "A flip flop is a memory device which can assume one of two stable output states, which has a pair of complementary outputs, and which has one or more inputs that can cuase the output state to change." I am directly quoting my Electrical Engineering 301 text, Fundamentals of Logic Design, Second Edition, 1979, by Charles H. Roth, Jr. of the University of Texas at Austin. Note that the text defines a flip flop as a binary (two state) memory element, thus the term "flip flop." In theory and practice there have been trinary memory elements, but they were so unwieldy that the technology was never pursued until recently. I would not categorize a trinary memory element as a flip flop, since the name "flip flop" was obviously and originally invented to describe two states. The text does not define a register. I will define a register as one or more memory elements. In other words, a register can be comprised of one or more flip flops. For example, it is common practice to have a microprocessor write or read a register in an FPGA. That register typically contains the same number of bits as the data bus that is connected to it. I commonly define control and status registers in FPGAs, and these registers have multiple data. So a register can be one flip flop or multiple flip flops. When it is only one flip flop, it can become confusing, because it can be referred as either one. Remember: this is only one source of data. Others may have different and better ideas on this subject. To introduce even more confusion, flip flops are now commonly called flops. This new term somewhat takes away from the binary nature of the original device. The good news is that I have yet to meet someone who has confused it, in context, with "floating point operations!" Simon Ramirez, Consultant Synchronous Design, Inc. Oviedo, FL USAArticle: 45995
Hi John, Thanks for the help. I think that it is a XPower bug. I have taken a simple BUFGMUX design which instantiates a gated clock and run a long timing simulation, had the command "vcd add -r /*" in the .udo file to dump all internal transitions. The results seem to conclusively indicate that XPower cannot handle toggle frequencies of gated clocks. VikramArticle: 45996
I have Reed-Solomon decoder with polynom 391 (Intelsat standard), whether probably to transform a signal encoded with polynom 285 (DVB standard), and decode it by this decoder ?Article: 45997
Hello, I was wondering if anyone has tried the Xilinx System generator blockset and can provide assistance in building a divider block. It doesn't have one and I could use it. I know that a divider is basically a shift and a subtraction and I am trying to put one together. Let me know if there is one already. Thank You MikeArticle: 45998
The thing is, the boards are already in-house so we have to deal with them. The switching all depends on the hysteresis of the LVPECL in buffers. Both pins are directly tied to a ground plane so I expect the differential noise to be very small. What to expect as hysteresis on those differential receivers ? I guess there is virtually no hysteresis if this is really implemented as a diff amp. I am about to modify a load so to be able to test that in the lab and get some feeling about that implementation. Any solutions ??? YanickArticle: 45999
I think the syntax is the same for fpga express and xilinx XST here is an example of a spartan2 fpga express bram (as rom) initialisation: -- braminst example start architecture braminst_arch of braminst is -- dualported ram component declaration, each port has 4bit width component RAMB4_S4_S4 port ( WEA,WEB,ENA,ENB,RSTA,RSTB,CLKA,CLKB: in std_logic ; DIA: in std_logic_vector(3 downto 0) ; ADDRA: in std_logic_vector(9 downto 0) ; DOA: out std_logic_vector(3 downto 0) ; DIB: in std_logic_vector(3 downto 0) ; ADDRB: in std_logic_vector(9 downto 0) ; DOB: out std_logic_vector(3 downto 0) ) ; end component; attribute INIT: string ; attribute INIT_00: string; attribute INIT_01: string; attribute INIT_02: string; attribute INIT_03: string; attribute INIT_04: string; attribute INIT_05: string; attribute INIT_06: string; attribute INIT_07: string; attribute INIT_08: string; attribute INIT_09: string; attribute INIT_0a: string; attribute INIT_0b: string; attribute INIT_0c: string; attribute INIT_0d: string; attribute INIT_0e: string; attribute INIT_0f: string; -- first bram attribute INIT_00 of DP_VRM0: label is "d56c13e08101012c1180688012282170ee1ff30f811760000000000000000000"; attribute INIT_01 of DP_VRM0: label is "3d25291f27101f1d7861d06261105ea2d3aa2d3daa2d3d050959232b81351200"; attribute INIT_02 of DP_VRM0: label is "0fd00cacaa41c5d43caaa53dc5aaa9281d0c5dcaa41dcaad1e2aaa1d0c5d0d1d"; attribute INIT_03 of DP_VRM0: label is "daa105940b2c113424140402313261599f0a31213211710d23435883d4af2219"; attribute INIT_04 of DP_VRM0: label is "302313261599f0f31213211710d23435883d4af22190c222113a43da83d54883"; attribute INIT_05 of DP_VRM0: label is "fe8a016015442435392fedc1ba98074831211109910446c1131215211910d234"; attribute INIT_06 of DP_VRM0: label is "a4dd1140db03b8543732f0438c96fedc9d801b42e64138072627604f8b62904f"; attribute INIT_07 of DP_VRM0: label is "08515a1a2c3e38d89cd912d8ba508cdb03c183150dc7d1d06cdd0140cc1c13cd"; attribute INIT_08 of DP_VRM0: label is "41605f6c5d6654893448230d0d8092c007170f43fd402c12841d27404d818888"; attribute INIT_09 of DP_VRM0: label is "3f410608354610235121d1f02150410b14220d41bc66ffdb211f00504455656d"; attribute INIT_0a of DP_VRM0: label is "222d44f125140122c435175afd973636f594271e430631111188b303d6533709"; attribute INIT_0b of DP_VRM0: label is "0201020101f60da6010342d2df66d21b6b111007221c24606065b61537c87535"; attribute INIT_0c of DP_VRM0: label is "a98ae10fd300100052547704fbb010fd5d05010c010c0101f62ea70103511101"; attribute INIT_0d of DP_VRM0: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0e of DP_VRM0: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0f of DP_VRM0: label is "0000000000000000000000000000000000000000000000000000000000000000"; -- second bram attribute INIT_00 of DP_VRM1: label is "1f14f5f4ff5f7fff01aa4d0cf5047f0411d110c1014ffafdddddddddddddddd0"; attribute INIT_01 of DP_VRM1: label is "a5a0c0c0c2c1051a414d6d5c7c0195e0949e08499e0249018bbc4504ff7fffdd"; attribute INIT_02 of DP_VRM1: label is "a32c0b7b470cb070cb44704eb05671c0c4ab07b4704eb755a2c640c4ab04a6a7"; attribute INIT_03 of DP_VRM1: label is "bba00bc4d40801b3b3b3b3aaaa0c0c1aa49ea1a11ca11ca90cdf1aa4a00fa04f"; attribute INIT_04 of DP_VRM1: label is "faaaa0c0c1aa493a1a11ca11ca90cdf1aa4a22fa04fa60c2c44944994491abb4"; attribute INIT_05 of DP_VRM1: label is "fff4d939f3f304304f3000030000330101010108e4898a801b1b10cb10cb90cd"; attribute INIT_06 of DP_VRM1: label is "05b148430b30412465504111f71d11111004d04d04d14d2f9504764f24f9fe45"; attribute INIT_07 of DP_VRM1: label is "1c1111b115714104047e51011115047043c1114ea01c11140470b01f11114147"; attribute INIT_08 of DP_VRM1: label is "0c0414a710abbb0404a6a046aff1f14d011101114a4104111e78070b18b8bb91"; attribute INIT_09 of DP_VRM1: label is "4da101150cd04150cd1621411baba911c0c6100c0c24045245524504babab1a0"; attribute INIT_0a of DP_VRM1: label is "4162d1411abab9dbd041d0004524045a2404504d11d8df7f5f040cd18a0c1151"; attribute INIT_0b of DP_VRM1: label is "702120313c48a40411114121142ad04def01112da0404aa0a019811d04dc04d0"; attribute INIT_0c of DP_VRM1: label is "fff754248209190fc0beecf1fab2144ee0d171712121313c48a4041111411171"; attribute INIT_0d of DP_VRM1: label is "0000000000000000000000000000000000000000000000000000000000000777"; attribute INIT_0e of DP_VRM1: label is "0000000000000000000000000000000000000000000000000000000000000000"; attribute INIT_0f of DP_VRM1: label is "0000000000000000000000000000000000000000000000000000000000000000"; etc.... begin -- bram instatiation example DP_VRM0:RAMB4_S4_S4 port map ( WEA => LS, WEB => LS, ENA => HS, ENB => HS, RSTA => LS, RSTB => LS, CLKA => m49, CLKB => m49, DIA => up_di0(3 downto 0), ADDRA => up_ada, DOA => up_do0(3 downto 0), DIB => vr_di0(3 downto 0), ADDRB => pcjmp(9 downto 0), DOB => vr_do0(3 downto 0) ) ; DP_VRM1:RAMB4_S4_S4 port map ( WEA => LS, WEB => LS, ENA => HS, ENB => HS, RSTA => LS, RSTB => LS, CLKA => m49, CLKB => m49, DIA => up_di0(7 downto 4), ADDRA => up_ada, DOA => up_do0(7 downto 4), DIB => vr_di0(7 downto 4), ADDRB => pcjmp(9 downto 0), DOB => vr_do0(7 downto 4) ) ; etc.... end braminst_arch; MIKE "Kolja Sulimma" <kolja@bnl.gov> schrieb im Newsbeitrag news:25c81abf.0208130156.679ce799@posting.google.com... > Hi! > > For a SOC I use both ROMs made of Block-RAMs and dual-ported > Block-RAMs that are preloaded at reset. > Currently I use CoreGen to generate these building blocks. > > I use Xilinx Foundation 4.1i XST and would much prefer to use inferred > Block-RAMs. I know the Language Assistant VHDL examples for inferring > Block-RAM, but they do not show how to preinitialize the RAMs. > > Any ideas? > > Kolja Sulimma
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