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Correct me if I'm wrong, but the Xilinx and Atmel parts have a different
pinout, at least for the XC18V01 PLCC 20 parts I've been looking at. Atmel
have two pinouts for this part, one which is Xilinx compatible (AT17LV010)
and another for Altera parts ("A" suffix). Neither pinout matches the
Xilinx part.
Mark,
--
Nachiket Kapre <nachikap@yahoo.com> wrote in message
news:eadce17c.0212040215.133c1745@posting.google.com...
> I wholeheartedly agree with Mikhail on the suggestion of using an
> XC18v series of ISP PROMs which allow you infinite in-system
> reprogrammability thru a simple JTAG "Parallel Cable 3" interface (and
> a daisy chain). 18v can save you a lot of headache and the return on
> the initial up-front high cost of the 18v compared to a 17v cannot be
> measured in terms of money alone.
>
> Okay, and about Atmel, you are absolutely right regarding the
> compatibility of that part with the Xilinx part. We did consider Atmel
> substitue parts in our deisgn but eventually , paradoxically due to
> unaviability of Atmel parts we went in with a Xilinx 18v series.
>
> regards,
> Nachiket Kapre
> Design Engineer.
> Paxonet Communications.
>
Article: 50176What connectors do you use on your board with programmable logic/ memory and JTAG devices? What pin-out do you use for that connector? I know of at least the 10 pin 2.54mm IDC connector for Altera and the linear 6(7) pin arragement on Xilinx experimental boards. Bye -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 50177
This is a multi-part message in MIME format. ------=_NextPart_000_001C_01C29B9E.5B482CF0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Simplest solution is a spi interface also known as microwire invented by = motorola. It's a master slave interface with full duplex capability usable with = any data rate. See serial dac/adc datasheets from nsc/maxim/ti/linear or motorola uC = for example protocols. MIKE "Mark Lew" <markylew@earthlink.net> schrieb im Newsbeitrag = news:ee7aba6.-1@WebX.sUN8CHnE... I am looking for suggestions on a low speed serial bus (~30 Mbs) while = minimizing IO. I will probably be interfacing between an FPGA and a = couple of CPLDs. Any help would be much appreciated. MarkArticle: 50178
Hi all, I have a problem with modelsim XE II v5.6a with Windows XP and NTFS Filesystem (with FAT32 everything is alright). Using Modelsim with Administrator privilegs everthing works correctly, but if I want to use it as user with restricted privilegs I have license problems. The License Wizard starts with the message: unable to open hkey local software. I changed the permissions in the registry: HKEY_LOCAL_MACHINE/SOFTWARE/MODELSIM, but the behaviour will remain unaffected. Wolfgang Brandt email: w.brandt@tuhh.deArticle: 50179
Symon wrote: > > Hi, > When I did this, I used vga.pdf from the page below on XESS's > website. Hardware is basically a few resistors. Piece of cake! The > worst part was entering the character generator ROM for the format I > wanted. I used 7*5 sized chars (stolen from and old Epsom LCD > controller manual) in a 9*6 space. This let me do crude graphics by > defining 64 chars to represent the combinations of six 3*3 blocks > being on and off in the 9*6 space, just like teletext. To do 'proper' > graphics you'd need loads of memory, so your plan of driving an old > VGA controller would work fine. > HTH, Symsx. > > http://www.xess.com/ho03000.html#Tutorials > I know this vga.pdf and it works fine with a resistor network, but more than 64 colors would be fine. I hoped to get some documentation about what goes over the ISA bus to bring a graphic onto the screen. is all the memory for the display located on the vga card or does the card use any memory from outside? up to now my I have not been able to get any useful paper on that :( ThomasArticle: 50180
Hi all, using a Xilinx Spartan-IIE 300 device I would like to have an EDIF block of a design I did once. 65% of the chip re- sources are being used from this EDIF design. Now is it possible to optimize the placement of this design and to 'preserve' this placement of this EDIF block in further variations of the whole design containing more than just this block. The EDIF block is a custom communication IP having tight timing requirements I don't like to work on the timing for every new 'incarnation' of it. This is kind of a soft- core with fixed placement (and maybe rounting) of the design... Any idea suggestion is welcome markusArticle: 50181
I'm trying to implement a digital filter (Gaussian) on an FPGA to perform digital pulse shaping on a puesdo random square wave signal. Has anyone done this in the past? If so, do you have any VHDL code to complete this task? I am really struggling! I have only just started to learn the language. Thank you. TomArticle: 50182
The vga card has all the memory for the display,. http://web.inter.nl.net/hcc/S.Weijgers/FreeVGA/home.htm "Thomas Buerner" <buerner@lrs.eei.uni-erlangen.de> wrote in message news:3DEE025D.4A17B1D7@lrs.eei.uni-erlangen.de... > Symon wrote: > > > > Hi, > > When I did this, I used vga.pdf from the page below on XESS's > > website. Hardware is basically a few resistors. Piece of cake! The > > worst part was entering the character generator ROM for the format I > > wanted. I used 7*5 sized chars (stolen from and old Epsom LCD > > controller manual) in a 9*6 space. This let me do crude graphics by > > defining 64 chars to represent the combinations of six 3*3 blocks > > being on and off in the 9*6 space, just like teletext. To do 'proper' > > graphics you'd need loads of memory, so your plan of driving an old > > VGA controller would work fine. > > HTH, Symsx. > > > > http://www.xess.com/ho03000.html#Tutorials > > > > I know this vga.pdf and it works fine with a resistor network, > but more than 64 colors would be fine. > I hoped to get some documentation about what goes over the ISA bus > to bring a graphic onto the screen. > is all the memory for the display located on the vga card > or does the card use any memory from outside? > up to now my I have not been able to get any useful paper on that :( > > ThomasArticle: 50183
Hello all! I need some advice about Nios SW execution. To evaluate the performance (speed) of a Nios SW application, I used an internal timer to count the clock cycles of a SW algorithm execution (written in C). The actual results were compared to external counter for accuracy and the results were equivalent. Afterwards, for comparison, I tried to evaluate the speed in SW: I disassembled the object file with objdump utility and applied manual post-analisys of the file - instruction after instruction (asm). The results were quite unexpected: the HW method and the SW method were far apart (in some cases up to 50%). For instance, in a simple for-loop (writen in C) with a large number of iterations, the HW result is 33M clock cycles and the manual disassembly result is 20M cycles. In disassembly method, I actually manually counted the number of instructions executed (worst case), since Nios uses 5 stage RISC architecture (1 clock cycle per instruction, generally speaking). At branching points, the delay slots were included in the calculation as well as the pipeline flushing after a branch (5 additional clock cycles). The SW algorithm was implemented in a Nios Development Board - in on-board 0-wait state SRAM, used as both data and instruction memory (each access needs only one clock cycle). Whatever I do in the calculation, the disassembly method doesn't get even close to the actual HW evaluated results. So, I'm wondering where's the problem? Is it in the pipeline execution? Does anyone know how does the Nios pipeline handle the branches (pipeline flushing) and the instructions, which use the result from previous instruction that hasn't been calculated yet (still in the pipeline)? Hope for some useful advice... Regards, MatjazArticle: 50184
Markus, Two ways. 1. Create RPM out of this EDIF file will get the placement preserved for future usage. (easy way) See Xilinx App Note 422 on how this can be accomplished. http://support.xilinx.com/xapp/xapp422.pdf If routing resources need to be preserved as well, try throwing FPGA Editor's directed routing constraints into the RPM's NCF file as well. Do note that directed routing is a feature that is still under quite a bit of development. 2. Create Hard Macro out of this EDIF's implementation. (hard way) http://support.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountryID=1&getPagePath=10901 -Wei Markus Meng wrote: > Hi all, > > using a Xilinx Spartan-IIE 300 device I would like to have > an EDIF block of a design I did once. 65% of the chip re- > sources are being used from this EDIF design. Now is it > possible to optimize the placement of this design and to > 'preserve' this placement of this EDIF block in further > variations of the whole design containing more than just > this block. > > The EDIF block is a custom communication IP having tight > timing requirements I don't like to work on the timing > for every new 'incarnation' of it. This is kind of a soft- > core with fixed placement (and maybe rounting) of the > design... > > Any idea suggestion is welcome > > markusArticle: 50185
Francisco, It's a little hard to figure out your hierarchy view, but I'll take a guess here. Have you assign the RPMs in D to a SET? (U_SET/HU_SET) or are you relying on MAP to automatically pick up the H_SET for you? MAP will not generate H_SET if there is only 1 component in that perticular hierarchy. You may also want to file a case at support.xilinx.com or by calling the Xilinx support hotline. -Wei Francisco Rodriguez wrote: > Hello all > > I'm having a hard time trying to get a correct RPM working with Xilinx ISE > 5.1sp2 tools. > > The following ASCII shows the design hierarchy. > > I ---+--- H -------------------------+ > J ---+ | > | > A ---+--- E ---+--- G ---+--- K ---+--- L > B ---| | | > C ---| | | > D ---+ | | > | | > A ---+--- F ---+ | > B ---| | > D ---+ | > | > A ------------------------+ > > At the bottom level, four different entities A, B, C, and D are used, based > on LUTs, DFEs, SRLs and so on. One of the simplest (D) uses a single LUT and > a single DFE. > If I synthesize up to entity K, everything is fine. The RPM (more than 2000 > slices) appears > well organized in Floorplaner. > > However, if I synthesize entity L, map produces a lot of warnings about > component D, like this one: > "INFO:Map:91 - dsr_f6muxor symbol "u0/u0/u8/u4/f" has an RLOC attribute > and will > be ignored since it is on a hierarchical block not directly recognized by > map. This may be caused by an error in the Xilinx library expansion for > the > symbol or by a third-party vendor incorrectly expanding the symbol." > The result, as shown by Floorplanner, is that K is only partially RPMed with > elements > of D spread around. > > I can not imagine why all D components (dsr_f6muxor is the actual entity > name) are > not recognized by map(that is, D's belonging to E and F), > as it is correctly processed when the top-level entity is K. > And the problem affects D only, not A, B or C (all at the same level than > D). > > Have any of you experienced a similar problem? Any clues? > I've searched Xilinx answer database but found nothing. > > Regards > Francisco Rodriguez > ==================================================== > Francisco Rodriguez Ballester (prodrig@disca.upv.es) > Dept. DISCA, EUI - Univ. Politecnica de Valencia > c/Camino de Vera s/n, E-46022, VALENCIA (SPAIN) > tlf: +(34) 96 387 75 77 - fax: +(34) 96 387 75 79 > ====================================================Article: 50186
Hi Talal, > used and if the time needed to transfere all the data in the page is 3 > times bigger than the time needed to send one refresh cycle. The refresh period of a SDRAM is usually abt. 64 millisecs, that should suffice to transfer a single page. It's usually no problem to wait 60 millisecs and send all outstanding autorefresh commands in a burst (e.g. 4096 autorefresh commands, if the SDRAM has 4096 rows.) (See Tref in the data sheet of your SDRAM) You shouldn't have to terminate a burst transfer. HTH, AndyArticle: 50187
No need to use a FIFO, your clock domains in this case are synchronous, the problem is
that the skew is not controlled tightly enough to go from one to another on the
supposedly aligned edges. You can use a negative edge flip-flop to catch the 1x clock
in the 2x domain, and then use that signal to create a facimile of the 1x clock in the
2x domain to use as a clock enable. Once that is done, then it is a simple matter of
using that clock enable to capture data away from the edge where it is switching.
You can also just use the neg edge of one of the clocks at the sync but you might find
it makes timing tight if you are running the clock hard, which is why we use the above
method.
louis wrote:
> That's why I asked this question.
> Since I am not familiar with the characteristic of DLL,
> I'd like to know what kind of mechanism I have to design to
> overcome the clock difference of DLL...
> Should it be asynchronous FIFO, or double buffer or
> different clock edge sampling, or something...
>
> Of course, I knew the asynchronous FIFO is safest, but the
> size is also largest.
>
> "Nachiket Kapre" <nachikap@yahoo.com>
> > why dont you try synchroniser across the two domains since that will
> > make your deisgn safer and independent of jitter which as ray
> > mentioned is suscptibel to rpocess vaiations and other physical
> > factors like temeperature..
> >
> > Nachiket Kapre
> > Design Engineer
> > Paxonet Communications
> >
> >
> > "louis" <n2684172@ms17.hinet.net> wrote in message
> news:<arcgqh$3og@netnews.hinet.net>...
> > > There's a external clock input (20MHz) on my system, and I multiply
> > > it to 2X (40MHz) by DLL as the working clock.
> > > However, I have to exchange data in several
> > > modules between these two clock domains. I don't know if it safe to sample data
> > > on both positive edges of these two clocks?
> > > Will the clock jitter cause the metastability? Or I have to generate data
> > > on positive edge and retrieve data on negative edge instead?
> > > The target chip is SpartanIIE. Any comment and suggestion will be very
> > > appreciated.
> > >
> > > louis
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50189Thomas Buerner wrote: > I know this vga.pdf and it works fine with a resistor network, > but more than 64 colors would be fine. Then you're in troubles. It is VERY hard to find any of the old CLUTs like INMOS or AD did, so you have to find some nice replacements for the D/A converter.Article: 50190
Thomas Buerner wrote: > Symon wrote: > >>Hi, >> When I did this, I used vga.pdf from the page below on XESS's >>website. Hardware is basically a few resistors. Piece of cake! The >>worst part was entering the character generator ROM for the format I >>wanted. I used 7*5 sized chars (stolen from and old Epsom LCD >>controller manual) in a 9*6 space. This let me do crude graphics by >>defining 64 chars to represent the combinations of six 3*3 blocks >>being on and off in the 9*6 space, just like teletext. To do 'proper' >>graphics you'd need loads of memory, so your plan of driving an old >>VGA controller would work fine. >> HTH, Symsx. >> >>http://www.xess.com/ho03000.html#Tutorials >> > > > I know this vga.pdf and it works fine with a resistor network, > but more than 64 colors would be fine. > I hoped to get some documentation about what goes over the ISA bus > to bring a graphic onto the screen. > is all the memory for the display located on the vga card > or does the card use any memory from outside? > up to now my I have not been able to get any useful paper on that :( > > Thomas The highest color depth in VGA is the 256-LUT mode which generates 6 bits per colour. So a 64-level resistor network per colour is sufficient for VGA and what is called HighColour in more modern cards. Look up "R2R network" for more bits D/A conversion. Implementing the functionality in the FPGA is probably a lot more fun then programing the VGA card. The bit plane concept perpetrated in VGA cards is a real pain. IwoArticle: 50191
May be easier to just make your own. The timing is not critical and if you don't need a ton of colors, the interface is pretty simple. For character gen I dumped the font from the BIOS in the machine I was using. Unrelated- I spent 2 weeks in your nice town (Erlangen) a few years back helping Siemens with a piece of x-ray equipment (had a Xilinx 4010 in it). Regards, President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- Thomas Buerner <buerner@lrs.eei.uni-erlangen.de> wrote in message news:<3DEC8941.656A9A4B@lrs.eei.uni-erlangen.de>... > Hi > > is it possible to use an old isa vga card connected to an FPGA > for video output? what must be sent over the bus to get it working? > > or is there another - easier - way to get a monitor connected to > my FPGA. > all hints welcome > > ThomasArticle: 50192
Don't terminate the burst- the uS timeframe refresh isn't critical. The important thing is that every row gets its refresh on the mS timeframe. One way to solve your problem is to do your full page access, then do 3 (or more) refresh cycles sequentially. You can que up your refreshes as long as you don't blow the X mS time frame for any one row. Regards President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- m.bonny@tu-bs.de (Talal) wrote in message news:<74512307.0212040304.423bca63@posting.google.com>... > Hello Everyone, > > anyone knows how to send refresh cycle to the SDRAM if the Full-Page > mode is > used and if the time needed to transfere all the data in the page is 3 > times bigger than the time needed to send one refresh cycle. > > I think that i need to use burst terminate command, but how can i > continue > transfering the data from the cutting point after terminating it to > send the > refresh? > > ThanksArticle: 50193
Question: Do the guts of your Spartans/System-bus run at 33MHz but then you're going to the 4X clock to time multiplex to save RAM chips? President, Quadrature Peripherals Altera, Xilinx and Digital Design Consulting email: kayrock66@yahoo.com http://fpga.tripod.com ----------------------------------------------------------------------------- bwickman@QUACKQUACKSPAMumich.edu wrote in message news:<asiims$caf$1@news2.engin.umich.edu>... > I've seen discussions here about clock distribution over circuit boards but > my application is slightly different than those previously mentioned. I am > building a multi-FPGA system based on the XC2S200E part from Xilinx, whereby > each device and its corresponding SRAMs are socketed via a PCI-like cardedge > connector. The FPGAs are to talk to each other via a bus protocol similar > to that used in Intel-based SMPs. In order to do this, each FPGA needs to > be using the same clock to handle proper timeslicing. > > Now, my application requires very speedy access to the on-circuit SRAM chips > and so I was anticipating using 4X the FPGA clock to "quad-pump" memory I/O. > The SRAM devices are 7ns, so I was figuring using a 33Mhz mainboard clock, > distributing it to each device and having the FPGA's memory controller > run on a 4X clock. The Spartan, if I recall correctly, can only do 2X > multiplication. > > How can I overcome this problem? Do I simply distribute a 66Mhz clock and > use the 2X multiplier? It is likely there will only be one or two runs of > the board and everything will be hand-soldered, so I'm wondering if junction > capacitance will be too high to allow a clean 66Mhz clock. > > The target bus will be 4-8 cards, each with one XC2S200E device and four > high-speed SRAMs. > > Thanks.Article: 50194
Hi, I want to measure the actual power in a FPGA Board. Any Ideas on how to do it. KolinArticle: 50195
Thomas Buerner wrote:
> Hi
>
> is it possible to use an old isa vga card connected to an FPGA
> for video output? what must be sent over the bus to get it working?
>
> or is there another - easier - way to get a monitor connected to
> my FPGA.
> all hints welcome
>
> Thomas
Hi,
I did this long time ago, with a 82C450 VGA chip and a
Tseng Labs ET4000 (remember them ?).
The first thing to know is that the VGA registers are a
complete mess (!), with bits from some registers overflowing
into others (for backward compatibility). Also, all chips
have a proprietary way to "unlock" their specific features.
I started with a datasheet containing a register table, but
many details were not properly covered, and I failed.
----
I then took a "brute force" approach, looking at all the
values the BIOS ROM sends to the VGA card while initialising
a video mode.
I ended up with a list of IO Address / Data pairs that, when
replayed, initialised the requested video mode properly.
But there were two problems:
- How do you set breakpoints in a BIOS ROM ?
- How to you do a software trace, when the software is in the
process of initialising the video card ?
To solve the first problem, I used an enhanced "VESA" driver
that loaded itself (including a copy of the BIOS) in RAM.
Thanks to old games afficionados, you can still find such
utilities for most current chipsets.
For the second one, I used a plain DOS machine, with it's console
keyboard/display redirected to the RS232 port using DOS command
CTTY COM1 and a terminal software on the second machine.
Using DOS's Debug software, I wrote and executed this :
mov ax,0x4F02 { Set VESA video mode }
mov bx, { required video mode }
int 10
The video mode I used was 0x103 (800x600 - 256 Colors - 75 Hz)
I then executed it in single step mode, writing down the address
& data for every out DX,AL / out DX,AX instruction encountered.
Obviously, I had to fast forward some parts of it (RAMDAC tables
fills / Display RAM test / zeroing), but within a few hours, I had
a working list of all the registers that needed to be initialised
and the proper values to do so.
I tried my list on the PC, and everything was fine.
I then used the list on my target M68000 processor board and it did
not work at all ...
I went back to the PC and single-stepped the VGA BIOS boot.
The first thing it did was to write seemingly meaningless values
at unusual IO adresses (in the 0x8000 range).
I added these to the list and the board fired up showing an
"artistic" pattern of colors (uninitialised display DRAM).
Once you get there, altering the values for other modes using
the register map is quite easy.
---
Once the video mode is properly initialised, the next step is to
write the GetPixel (x,y) and PutPixel (x,y,Color) functions and
any software guy will be able to figure out higher level functions.
Using old paged VGA controllers, the routines were pretty slow,
but it should not be an issue with current chipsed that have a flat
memory model for the bitmap.
---
A Picoblaze processor could easily do the initialisation (possibly
using parameters stored in an external serial EEPROM) and the low
level functions with adequate speed.
The same EEPROM can also hold bitmaps for the character fonts to add
virtual text modes also controlled by the Picoblaze.
An interresting point is that by doing the VGA card init. inside he
FPGA, the main microcontroller/processor can be held in reset until
the VGA board is ready, and it can then take advantage of the cheap
and abundant VGA ram for it's own non display related RAM needs,
treating it as regular RAM.
If the already mentionned EEPROM also holds the application software,
the processor can even rely on the VGA ram to hold it's software, thus
making the whole design very cost effective ...
Hope this helps.
Eric
PS : For unobfuscated email, remove "not" and "me"
Article: 50196Jon Elson wrote: > > Gregory C. Read wrote: > > >One simple question occurs to me. Are you connected to a powered PC parallel > >port with your system unpowered? > > > > > Yes, this can happen, but the board draws VERY little power, so the Vcc > just floats > up to near the voltage of the highest pin. I have left it in this state > for hours, and > it does not seem to be the cause of trouble. Almost all cases can be > traced to > unplugging and plugging the parallel port connector. Ideally GND connections are made first, but that's not always the case, and if the systems have enough ground differential, then injection currents result as they are forced toward equal values. What is the FPGA-end powered from ? Double insulated plug-packs can cause problems ( no gnd lead ), and different models have different mains-output leakage capacitances. The best use an earthed faraday shield, but that increases price, so is not common. - jgArticle: 50197
Gregory C. Read wrote: >One simple question occurs to me. Are you connected to a powered PC parallel >port with your system unpowered? > > Yes, this can happen, but the board draws VERY little power, so the Vcc just floats up to near the voltage of the highest pin. I have left it in this state for hours, and it does not seem to be the cause of trouble. Almost all cases can be traced to unplugging and plugging the parallel port connector. Thanks, JonArticle: 50198
Jim Granville wrote: >Jon Elson wrote: > > >>Gregory C. Read wrote: >> >> >> >>>One simple question occurs to me. Are you connected to a powered PC parallel >>>port with your system unpowered? >>> >>> >>> >>> >>Yes, this can happen, but the board draws VERY little power, so the Vcc >>just floats >>up to near the voltage of the highest pin. I have left it in this state >>for hours, and >>it does not seem to be the cause of trouble. Almost all cases can be >>traced to >>unplugging and plugging the parallel port connector. >> >> > >Ideally GND connections are made first, but that's not always the case, >and if the systems have enough ground differential, then injection >currents result as they are forced toward equal values. > >What is the FPGA-end powered from ? > > One device is powered from a multi-voltage, grounded power supply. The smaller device is powered from a plug pack. For cost reasons, I think that has to stay that way. >Double insulated plug-packs can cause problems ( no gnd lead ), >and different models have different mains-output leakage capacitances. > >The best use an earthed faraday shield, but that increases price, so >is not common. > > The "smaller device" is a $200 circuit board with a $30 XCS30-3TQ144C, 2 CMOS chips, a serial PROM, and optocouplers. I really can't add much to this board without having to raise the price. Arranging grounding to the 25-pin D-connector shell might accomplish sequential connection, with the ground making contact first. Definitely something to try - thanks for the idea! JonArticle: 50199
Kolin Paul wrote: > Hi, > > I want to measure the actual power in a FPGA Board. > Any Ideas on how to do it. You want to measure power consumption of a single chip, or the whole board? Measuring the power draw of a single chip in an operating system is tricky, as you need to break all the power connections between the chip and the rest of the board, and funnel it through a sensing resistor or hall effect probe. Measuring total system power consumption should be easier. A DVM with a current shunt can be used, just put it in series with each power source coming into the board. Multiply each current times the voltage to get power, add power for all voltages together to get total power. Without descibing the board in more detail, it is hard to get more specific. Jon
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