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C'mon. Just because the Brits don't know how to spell liters correctly, like the rest of the world does... The Bard definitely preferred pints etc, maybe because the "litre" was not yet invented. :-) Peter Alfke Tim wrote: > Ray Andraka wrote > > > It makes no more sense measuring FPGA > > design size in gates than it does measuring distance in > > Liters. > > Or even Litres. What has happened to the language of > Shakespeare :-)Article: 50251
This is a multi-part message in MIME format. --------------ED32B94B0BAED3894DDAB8F2 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: 8bit Chip, If you are using the 2V1000, then beware of the 'Stepping Level'. In the 2V1000 there are two multiplier designs, one faster than the other. To change the Stepping use this: CONFIG STEPPING = 1 or 0. By default it will be 0 for the 2V1000 (which means old Multiplier design). The default changes depending on what family member you target, eg: the 2V500 only has the newer design, so the default is 1. In the -6 2V1000 for a 16x16 fully RPM'd and INFF and OUTFF stages, you can get to 246MHz. In the -5 Stepping = 0 you will get 139MHz compared with 215MHz with Stepping = 1; In the Virtex2Pro -7 you can get to >285MHz with the same design (16x16) Check out : http://www.xilinx.com/xapp/xapp636.pdf Dave Chip wrote: > Hello all, > > Could someone please explain the following statement taken directly > from www.xilinx.com. The sentance came from a description of the new > system generator. > > >Designers can use 285MHz multipliers to easily develop higher > performance, >lower cost DSP systems. > > I've haven't been successful in finding any information that explains > this statement. When I look at the virtex-II datasheet I only find > the following information about the performance of the built in > multiplier blocks: > > Multiplier 18x18 (with Block RAM inputs) XC2V1000 –5 88 MHz > Multiplier 18x18 (with Register inputs) XC2V1000 –5 105 MHz > > When I use coregen and implement a fully pipelined multiplier with > registered inputs and outputs I get results similar to what the > datasheet says. > > If anyone knows how to achieve this performance using the Virtex-II > built in multipliers your advice would be greatly appreciated! > > Thanks, > > Chip LukesArticle: 50253
Hi Austin,
thanks for your answer, but you didn't really answer my questions. In my design
I have 6 DCMs using and generating internal and external clocks in different
combinations. One of the DCMs drives three other DCM:s. I think one or two of
them should be system synchronous and the rest should be source synchronous. But
I'm not sure because I can't find any description of *exactly* how the deskewing
works.
For instance, the compensation delay you mention, is it *always* inserted in
system synchronous mode or only if the DCM is used in a certain configuration
such as CLKIN comes from an external clock, CLKFB comes from an external clock
or it drives an external clock?
What about chained DCMs where the first generates an internal clock driving
three other DCMs by multiplying (2X) an external clock (internal feedback, no
deskew of extrenal clock) and the three following DCMs are replicating this
clock with different phase shifts (NONE, FIXED with external feedback and
VARIABLE controlled by logic sampling a receive clock? Below is a simplified
scematic of the system (most BUFGs have been left out):
+-------------+ +------------+
| _________ | | ________ |
+-| FB 0|-+ +-|FB 0|-+------> int_clk2x_0
ext_clk -|>----+-----| IN 2x|---+-----|IN 90|--------> int_clk2x_90
BUFG | | | | | |
v | (1) | | | (2) |
int_clk | | | |SHIFT |
| | | |NONE |
--------- | --------
|
+---> int_clk2x
| ________
ext_clk2x_fb -------------------< | >---|FB 0|--------> ext_clk2x
+-----|IN |
| | |
| | (3) |
| |SHIFT |
| |FIXED |
| --------
|
|
| +------------+
| | ________ |
| +-|FB 0|-+------> int_clk2x_vs_0
+-----|IN 90|--------> int_clk2x_vs90
| |
ext_rec_clk--(ctrl_logic)---------------|PS* (4) |
|SHIFT |
|VARIABLE|
--------
How should DESKEW_ADJUST for these be set for DCM 1, 2, 3 and 4?
Is there any way to see in the timing analysis or somewhere else how these
compensation offsets affects the DCM?
Best Regards,
Magnus
Austin Lesea wrote:
> Magnus,
>
> For system synchronous, we need to compensate for the worst possible PVT internal
> delays to guarantee timing. Thus we insert a delay that is settable by the
> bitstream, and was characterized for each device over all process corners.
>
> This does throw away some timing (obviously) and adds more variability in and of
> itself, as the delay is also affected by PVT, and adding it makes things less
> accurate.
>
> Hence the reason why system synchronous is harder to make work at higher frequencies
> (generally true for everyone....not just us).
>
> For source synchronous, we can set this delay to zero (or nearly so) as the DCM has
> the phase shift feature, which allows for placing the sample clock in the center of
> the data cell. In such a setup, the "data sample window" or variation for
> guaranteed proper sampling of the data by the clock is reduced, and higher clock
> speeds are supported with an even larger "eye margin."
>
> Source synchronous is the solution to trying to run busses at these higher clock
> rates (also generally true for everyone).
>
> Austin
>
>
> Magnus Jacobsson wrote:
>
>
>>Hi,
>>
>>can anybody explain exactly *when* setting the DESKEW_ADJUST =
>>SOURCE_SYNCHRONOUS for a DCM has any effect on a DCM, exactly *how* it affects
>>the DCM and if Trace should report any different timing than if the default mode
>>was used (because it doesn't for me).
>>
>>I have already looked at Answer Records # 14743 and # 15350 and searched the
>>Xilinx documentation but I can't find the info I need.
>>
>>Can someone also explain how the default mode (SYSTEM_SYNCHRONOUS) works,
>>especially how the "secret" compensation offset between CLKIN and CLKFB is
>>determined in different situations? In Answer Record # 13024 the Tdcmclkinoffset
>>is described in the follwing way:
>>
>>Tdcmclkinoffset = A compensation offset fixed to account for other circuit
>>anomalies.*
>>
>>* This number is dependent upon circuit conditions and low-level speed file
>>parameters.
>>
>>How *exactly* is it calculated?
>>
>>Best Regards,
>>Magnus Jacobsson
>>
>
--
Magnus Jacobsson Net Insight AB
Phone: +46-8-685 0415 Box 42093, SE-126 14 Stockholm, Sweden
Fax: +46-8-685 0420 Visiting address: Västberga Allé 9
Mobile: +46-70-269 1487 http://www.netinsight.net
Article: 50254Hello Pierre-Oliver, You can use directed routing constraints to constrain routing. The best way to do this is to open your routed .ncd in FPGA Editor, then select Tools -> Directed Routing Cst... and use the dialogue to constrain your nets as you wish. Check out the help files for more information on directed routing constraints. Cheers, Ryan Pierre-Olivier Laprise wrote: > This thread brings to mind an issue that's been bugging me recently. > Could anyone tell me why you can't 'freeze' routing (or is there a > way? I'm using ISE 5.1), or reserve certain routing resources? It would > seem to me to be a useful addition, am I missing something? > > Pierre-Olivier > > On Fri, 6 Dec 2002, Chen Wei Tseng wrote: > > >>Muthu, >> >>The warning should not prevent you from creating the NCF file. Just make sure you have all the slice >>logic comp placed and you'll be fine. If you have all slice logic comps placed and still sees the >>warning; then it's likely a bug that you may want to report to the hotline. >> >>As for IOB DFFs, if you don't specify it, MAP by ISE default should try to pack them into IOBs. >> >>Thanks, Wei >> >>Muthu wrote: >> >> >>>Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3DEF8C58.E458668E@xilinx.com>... >>> >>>>Muthu, >>>> >>>>Usually, when you create a RPM, you would want to RLOC everything. This warning message tells you >>>>that you still have components (LUTS/DFF/ etc...) not placed when you are trying to create the RPM. >>>>This will results in the unplaced logic not bound to the RPM shape. >>>> >>>>Possible cause of this. >>>> >>>>1. Using replace all with placement - And you have DFF packed into the IOB. Since Floorplanner >>>>doesn't show components in the IOB, you'll have to manually place the DFF components or leave them >>>>out of the RPM shape. >>>> >>>>2. When you're manually placing the components, you didn't place all the components other than the >>>>IOBs. >>>> >>>>Regards, Wei >>> >>>Hi wei, >>> >>>Yeah i agree, some components are not place in the Floor-planner. >>>Thats why this warning came. >>> >>>But i am sure that it is not due to IOB FFs. Becasue, My input .edf >>>file is generted with out inserting the IOB while synthesis. >>> >>>Best regards, >>>Muthu >> >> >Article: 50255
Hi Talal, You have 2^13 rows, with 13 row address bits. You only have to AVERAGE one refresh cycle every 781 clock cycles. You could do something like have a pending refresh counter that increments every 512 (nice round number) clocks, if the SDRAM controller state machine is not busy doing anything else (idle), then it starts doing refresh cycles until the pending refresh counter gets back to zero. So in the case of a 2048 bytes page access, the counter would count up to around 4 or 5, and when the page access had completely finished, the state machine would then go fire off 4 or 5 refresh cycles. ---------------------------------------------------------------------- From e-mail sent to me... Hello Sir, The timeframe refresh is critical for me, because i am using SDRAM which has 13 rows, that means i have to send 8192 refresh commands within 64 ms. I am working with 100 MHz Clock Frequency (10 ns). by making simple calculations, you will find that i need to send one refresh cycle in every 781 clock cycle. My SDRAM has 11 colums. that means the Full-Page mode has 2048 byte. Now, how can i send 2048 byte data in more than 2048 clock cycle although i need to send one refresh command in every 781 clock cycle ? Thanks Regards TalalArticle: 50256
The best way to answer this question is run some FPGA tools and see what you get. You don't have to have any hardware bought or built to do this. The synthesis result will get you pretty close on size, and the post place & route timing will give you expected your speed. The eval versions of the tools will let you get these answers. If you want to take a worst case approach, you can say that one ASIC gate = one FPGA LUT. Using these numbers a Xilinx V2 6000 which is marketed as having 6M "system gates" has about 60k asic gates. This would hold 3-4 instantiations of your USB core. Regards "Steve Casselman" <sc@vcc.com> wrote in message news:<eLOH9.3209$ti7.77237430@newssvr13.news.prodigy.com>... > I think aoubt it this way: A regular "logic gate" is usually thought of as 2 > input nand gate. Since you can make anything out of nand gates anything you > can make can be expressed in the number of nand gates it would take to build > the design. The total "System Gates" number is the maximum "potential > gates" on the chip. By that I mean if had a design used every feature then > you would need that many nand gates to build the design. > > Steve > > PS if you want to know what kind a area your design will take in a certain > part you need to look at how many LUTs and Flops for a worst case number. > > "Steve" <steve1@mecca.com> wrote in message news:ee7ac4c.-1@WebX.sUN8CHnE... > I have a pre-made USB interface design which claims to use 16K-20K gates, > and I'm looking for an appropriate FPGA for implementing this. It seems that > most FPGA's (I've checked several of the Virtex and Spartan series) report > "system gates", and sometimes include "logic gates" as well. > What is the difference between these two? For example, the SpartanXL XCS50XL > says it has 13K-40K system gates and 20K max. logic gates. Where do the rest > of the system gates go? Are they all for RAM? > Also, what would the USB's gate count be referring to.. system gates or > logic gates? > Thanks! > -SteveArticle: 50257
Hi, I have a very simple piece of code pasted below. This code has hold time violations in it when I synthesize it in Quartus II 2.0. I understand why the code shows the violations but can't see a way to fix it. Any help would be appreciated. ------------------------------------------------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.all; use IEEE.STD_LOGIC_UNSIGNED.ALL; use ieee.std_logic_arith.all; entity sync_we32_ram_18_wrap is port ( address : IN STD_LOGIC_VECTOR (3 DOWNTO 0); we : IN STD_LOGIC := '1'; inclock : IN STD_LOGIC ; outclock : IN STD_LOGIC ; data : IN SIGNED (17 DOWNTO 0); s_q_signed : OUT SIGNED (17 DOWNTO 0) ); end sync_we32_ram_18_wrap; architecture RTL of sync_we32_ram_18_wrap is component sync_we32_ram_18 PORT ( address : IN STD_LOGIC_VECTOR (3 DOWNTO 0); we : IN STD_LOGIC := '1'; inclock : IN STD_LOGIC ; outclock : IN STD_LOGIC := '1'; data : IN STD_LOGIC_VECTOR (17 downto 0); q : OUT STD_LOGIC_VECTOR (17 downto 0) ); END component; signal s_data : std_logic_vector(17 downto 0); signal s_q : std_logic_vector(17 downto 0); begin sync_ram_18 : sync_we32_ram_18 port map (address, we, inclock, outclock, s_data, s_q); process (inclock) begin if inclock'EVENT and inclock = '1' then s_data <= CONV_STD_LOGIC_VECTOR((CONV_INTEGER(s_q)),18); s_q_signed <= CONV_SIGNED((CONV_INTEGER(s_q)),18); end if; end process; end RTL; ------------------------------------------------------------------------------- The ram instantiated in the design is created automatically using the Megawizard (create lpm_ram_dq) in Quartus II 2.0. Thanks, PrashantArticle: 50258
thanks for your comments, I am using single ended LVTTL. The traces are 5 mil in width.I do not know the characteristic impedance yet. I do NOT know the impedance of either the SCSI cable OR the SCSI connector. Infact, this connector is from COMMCON and the tech-support at COMMCON says that they have not measured the impedance of these connectors. The value of "33 ohms" is based purely on a recommendation by technical support at the company from whom we (my research group) purchased 16 boards with Xilinx XCV600E's on them. These boards have a high density I/O connector (68 pins = 34 signal + 34 ground) SCSI interface similar to the one we are using . That is single ended. And they have used 33 ohms series termination for all I/O's. Moreover, what I have been told is that this value of 33 ohms has been used simply to match the characteristic trace impedance and that the cable and connector impedances have NOT been considered. Further, I am assuming that their trace impedance (fan-out from BG560 ) is the same as my trace impedance (fan-out from FG1156). Also, we have been able to communicate at 33 Mhz point-to-point using two of their boards on two PC's. Now, we are trying to build a "crossbar switch" using a Xilinx Virtex 2000-E part which will interface to these 16 boards.Total of 544 I/O will be involved, 34 for each of 16 ports coming from these 16 boards. These 16 boards are fitted into the PCI slots of 16 PC's.Ultimately, we are building a Beowulf type cluster. Half of these 544 I/O's will be driving signals and the other half will be receiving signals and hence I will need to series terminate 544/2= 272 of these 544 I/O's. Also, according to the xilinx board routability guidelines, XAPP 157 ,we will need a 10 layer board. I am already concerned about how I'll be able fit so many resistors on the board. ( unfortunately I don't think we can move to VIRTEX-II with DCI because we are already in possession of the VIRTEX-E chip). So, I want to be sure,at least,of the value of these resistors before going ahead with the board design and eventually fabrication. Please do reply with your suggestions, they are a tremendous help ! thanks and regards Anand PS: web address of the cable part... External SCSI III Cable with Thumbscrews - 3 feet http://catalog.belkin.com/IWCatProductPage.process?Merchant_Id=1&Product_Id=15951 hmurray@suespammers.org (Hal Murray) wrote in message news:<uuvkhhtn5lcu85@corp.supernews.com>... > >(A)FPGA-pin--"R"-------T------connector--cable--connector------T-----FPGA-pin(B) > > >The termination resistor value is 33 ohms. > >The cable is a 3 feet long SCSI cable. > >The connectors are 68-pin SCSI female,high density connectors. > > Are you running single ended or differential? > > What's the impedance of the SCSI cable? What's the impedance > of your traces at each end and/or how long are they? > > Traces are usually close to 50 ohms. Depends on layer spacing. > > I think differential SCSI cables are >100 ohms. That will probably > be close enough if you use it differentially. If you ground one side > of the pair and use it single ended you might get a big reflection at > the transition between trace and cable.Article: 50259
Hi Wei
Thanks for your tip about the H_SET attribute.
I was manually assigning U_SET along with RLOC,
following the techxclusive article on silinx support website.
I've finally solved the problem simplifiyng the hierarchy and eliminating
all U_SETs. That is, once I modified the hierarchy to avoid the HSET
problem,
I got the thing working.
I'm still confused, however. Floorplanner shows everything into the right
location, but some flip-flops are still out of the hset RPM.
But as those flip-flops are in the expected locations (as per the RLOCs),
I imagine they are inside the RPM (for the map program at least).
They could not follow the relative placement constraint otherwise.
Maybe floorplanner is cheating me. Don't know really.
Regards
Francisco Rodriguez
"Chen Wei Tseng" <chenwei.tseng@xilinx.com> escribió en el mensaje
news:3DEE219C.4F53D005@xilinx.com...
> Francisco,
>
> It's a little hard to figure out your hierarchy view, but I'll take a
guess
> here. Have you assign the RPMs in D to a SET? (U_SET/HU_SET) or are you
relying
> on MAP to automatically pick up the H_SET for you?
>
> MAP will not generate H_SET if there is only 1 component in that
perticular
> hierarchy.
>
> You may also want to file a case at support.xilinx.com or by calling the
Xilinx
> support hotline.
>
> -Wei
>
> Francisco Rodriguez wrote:
>
> > Hello all
> >
> > I'm having a hard time trying to get a correct RPM working with Xilinx
ISE
> > 5.1sp2 tools.
> >
> > The following ASCII shows the design hierarchy.
> >
> > I ---+--- H -------------------------+
> > J ---+ |
> > |
> > A ---+--- E ---+--- G ---+--- K ---+--- L
> > B ---| | |
> > C ---| | |
> > D ---+ | |
> > | |
> > A ---+--- F ---+ |
> > B ---| |
> > D ---+ |
> > |
> > A ------------------------+
> >
> > At the bottom level, four different entities A, B, C, and D are used,
based
> > on LUTs, DFEs, SRLs and so on. One of the simplest (D) uses a single LUT
and
> > a single DFE.
> > If I synthesize up to entity K, everything is fine. The RPM (more than
2000
> > slices) appears
> > well organized in Floorplaner.
> >
> > However, if I synthesize entity L, map produces a lot of warnings about
> > component D, like this one:
> > "INFO:Map:91 - dsr_f6muxor symbol "u0/u0/u8/u4/f" has an RLOC
attribute
> > and will
> > be ignored since it is on a hierarchical block not directly
recognized by
> > map. This may be caused by an error in the Xilinx library expansion
for
> > the
> > symbol or by a third-party vendor incorrectly expanding the symbol."
> > The result, as shown by Floorplanner, is that K is only partially RPMed
with
> > elements
> > of D spread around.
> >
> > I can not imagine why all D components (dsr_f6muxor is the actual entity
> > name) are
> > not recognized by map(that is, D's belonging to E and F),
> > as it is correctly processed when the top-level entity is K.
> > And the problem affects D only, not A, B or C (all at the same level
than
> > D).
> >
> > Have any of you experienced a similar problem? Any clues?
> > I've searched Xilinx answer database but found nothing.
> >
> > Regards
> > Francisco Rodriguez
> > ====================================================
> > Francisco Rodriguez Ballester (prodrig@disca.upv.es)
> > Dept. DISCA, EUI - Univ. Politecnica de Valencia
> > c/Camino de Vera s/n, E-46022, VALENCIA (SPAIN)
> > tlf: +(34) 96 387 75 77 - fax: +(34) 96 387 75 79
> > ====================================================
>
Article: 50260"Uwe Bonnes" <bon@elektron.ikp.physik.tu-darmstadt.de> wrote in message news:asq4ei$53a$1@news.tu-darmstadt.de... > glen herrmannsfeldt <gah@ugcs.caltech.edu> wrote: > > : "Steve Casselman" <sc@vcc.com> wrote in message > : news:eLOH9.3209$ti7.77237430@newssvr13.news.prodigy.com... > :> I think aoubt it this way: A regular "logic gate" is usually thought of as > : 2 > :> input nand gate. Since you can make anything out of nand gates anything > : you > :> can make can be expressed in the number of nand gates it would take to > : build > :> the design. The total "System Gates" number is the maximum "potential > :> gates" on the chip. By that I mean if had a design used every feature then > :> you would need that many nand gates to build the design. > > : The one that I usually use says that the number of gates is the number of > : transistors used divided by the number in a two input NAND gate. > : That is four in CMOS. This rules makes sense for ASIC design but not > : much sense for FPGA design. > > : As to the original question, yes, they count built in RAM in the gate > : count, as it would under the transistors definition. Though you wouldn't > : really build RAM out of NAND gates. > > Lies, damned lies and FPGA Gate Count :-) Just like the problem of determining processor speed, there is no easy answer. The only way that I could think of that would make sense would be to take some designs, compile them as ASICs and as FPGAs and see how many gates the ASIC took. Without a scalable design, this is very hard to do and have it make sense. Another problem is that a design might barely fit, using poor routing resources, run very slow, and so be useless for its desired purpose. So more than just gates, you could have a gates * clock frequency metric. Maybe with the larger FPGAs now one could find a reasonable scalable design. Take a reasonably simple processor design, but make the word size adjustable. For each target FPGA device find the largest word size that will fit, or find the size that maximizes word size * clock frequency. There should probably be some different desings representing the variety of uses for FPGA's. -- glenArticle: 50261
The recommendation made by an earlier post to experiment with the resistance value is best. You rsignal fidelity is going to be most dependent on the SCSI cable impedance which I'd expect to be about 100 ohms. As for the resistors, if you have good automated assembly available, the 4-pack resistors in 0805 packages (that's 4 Rs in the one teenie tiny footprint) are a good bet and pretty inexpensive, too. You can look at today's motherboard designs - particularly the DDR memory interface - and see dozens of these things scattered around. They're a bit of a mess to hand assemble, though. Lots of resistors, no problem. Since you're on the LVTTL interface, another option is to play with the drive current. If the idea behind a series impedance is to deliver half the voltage until a reflection comes back, picking a drive current with about that bias point would better match your needs. This approach is sloppier but could save a huge number of resistors without significantly affecting performance. You can find the drive characteristics in the IBIS models. "Anand" <anand287@lycos.com> wrote in message news:a6908954.0212061108.4c4e0de1@posting.google.com... > thanks for your comments, > > I am using single ended LVTTL. > > The traces are 5 mil in width.I do not know the characteristic > impedance yet. > > I do NOT know the impedance of either the SCSI cable OR the SCSI > connector. > > Infact, this connector is from COMMCON and the tech-support at > COMMCON says that they have not measured the impedance of these > connectors. > > The value of "33 ohms" is based purely on a recommendation by > technical support at the company from whom we (my research group) > purchased 16 boards with Xilinx XCV600E's on them. > > These boards have a high density I/O connector (68 pins = 34 signal + > 34 ground) SCSI interface similar to the one we are using . > That is single ended. > > And they have used 33 ohms series termination for all I/O's. > > > Moreover, what I have been told is that this value of 33 ohms has been > used simply to match the characteristic trace impedance and that the > cable and connector impedances have NOT been considered. > > Further, I am assuming that their trace impedance (fan-out from BG560 > ) is the same as my trace impedance (fan-out from FG1156). > > Also, we have been able to communicate at 33 Mhz point-to-point using > two of their boards on two PC's. > > > Now, we are trying to build a "crossbar switch" using a Xilinx Virtex > 2000-E part which will interface to these 16 boards.Total of 544 I/O > will be involved, 34 for each of 16 ports coming from these 16 boards. > > These 16 boards are fitted into the PCI slots of 16 PC's.Ultimately, > we are building a Beowulf type cluster. > > Half of these 544 I/O's will be driving signals and the other half > will be receiving signals and hence I will need to series terminate > 544/2= 272 of these 544 I/O's. > > Also, according to the xilinx board routability guidelines, XAPP 157 > ,we will need a 10 layer board. > > I am already concerned about how I'll be able fit so many resistors on > the board. ( unfortunately I don't think we can move to VIRTEX-II with > DCI because we are already in possession of the VIRTEX-E chip). > > So, I want to be sure,at least,of the value of these resistors before > going ahead with the board design and eventually fabrication. > > Please do reply with your suggestions, > they are a tremendous help ! > > thanks and regards > > Anand > > PS: web address of the cable part... > External SCSI III Cable with Thumbscrews - 3 feet > http://catalog.belkin.com/IWCatProductPage.process?Merchant_Id=1&Product_Id= 15951 > > > > > hmurray@suespammers.org (Hal Murray) wrote in message news:<uuvkhhtn5lcu85@corp.supernews.com>... > > >(A)FPGA-pin--"R"-------T------connector--cable--connector------T-----FPGA-p in(B) > > > > >The termination resistor value is 33 ohms. > > >The cable is a 3 feet long SCSI cable. > > >The connectors are 68-pin SCSI female,high density connectors. > > > > Are you running single ended or differential? > > > > What's the impedance of the SCSI cable? What's the impedance > > of your traces at each end and/or how long are they? > > > > Traces are usually close to 50 ohms. Depends on layer spacing. > > > > I think differential SCSI cables are >100 ohms. That will probably > > be close enough if you use it differentially. If you ground one side > > of the pair and use it single ended you might get a big reflection at > > the transition between trace and cable.Article: 50262
Brendan Cullen <bcullen@xilinx.com> wrote in message news:<3DE265EC.F7FE6A23@xilinx.com>... > Hi John, > > > I'm about to use a Xilinx CoolRunner CPLD (running at ~30uA) and am > > wondering what the best way is to measure the power consumption. I'm > > looking for something relatively simple, which doesn't need to be > > extremely accurate. Can I just measure the current draw across all the > > VCC inputs and multiply those by VCC? What is the easiest circuit to > > do this, since the currents will be so low - a BJT current amplifier? > > Thanks! > > In particular, which CPLD device ? > > Brendan The XCR3256XL-TQ144. -JohnArticle: 50263
Routed Hard Macro tends to cause PAR to crash with Fatal_Error. Directed Routing, as Ryan has indicated, is the best solution now although there are few bugs that needs to be hammered out. Mainly the Xilinx's physical and user's Logical name mismatch. As far as "freezing" existing routings in the design, the answer is yes. The use of Incremental Design will do the trick for you provided the signal names don't change. Regards, Wei Pierre-Olivier Laprise wrote: > This thread brings to mind an issue that's been bugging me recently. > Could anyone tell me why you can't 'freeze' routing (or is there a > way? I'm using ISE 5.1), or reserve certain routing resources? It would > seem to me to be a useful addition, am I missing something? > > Pierre-Olivier > > On Fri, 6 Dec 2002, Chen Wei Tseng wrote: > > > Muthu, > > > > The warning should not prevent you from creating the NCF file. Just make sure you have all the slice > > logic comp placed and you'll be fine. If you have all slice logic comps placed and still sees the > > warning; then it's likely a bug that you may want to report to the hotline. > > > > As for IOB DFFs, if you don't specify it, MAP by ISE default should try to pack them into IOBs. > > > > Thanks, Wei > > > > Muthu wrote: > > > > > Chen Wei Tseng <chenwei.tseng@xilinx.com> wrote in message news:<3DEF8C58.E458668E@xilinx.com>... > > > > Muthu, > > > > > > > > Usually, when you create a RPM, you would want to RLOC everything. This warning message tells you > > > > that you still have components (LUTS/DFF/ etc...) not placed when you are trying to create the RPM. > > > > This will results in the unplaced logic not bound to the RPM shape. > > > > > > > > Possible cause of this. > > > > > > > > 1. Using replace all with placement - And you have DFF packed into the IOB. Since Floorplanner > > > > doesn't show components in the IOB, you'll have to manually place the DFF components or leave them > > > > out of the RPM shape. > > > > > > > > 2. When you're manually placing the components, you didn't place all the components other than the > > > > IOBs. > > > > > > > > Regards, Wei > > > > > > Hi wei, > > > > > > Yeah i agree, some components are not place in the Floor-planner. > > > Thats why this warning came. > > > > > > But i am sure that it is not due to IOB FFs. Becasue, My input .edf > > > file is generted with out inserting the IOB while synthesis. > > > > > > Best regards, > > > Muthu > > > >Article: 50264
Hi, I have a 120MHz clock being fed into a global clock pin and would like to be able to send this clock to an ADC on my board using the DLL for more clocking options. I've read the datasheet but am a bit confused, should I use one of the 4 DLL's as the output to the ADC clock input? So for my package pin75 is one of the DLL's so would I connect this pin to the clock input of the ADC? Xilinx datasheets ie. (Spartan-IIE 1.8V FPGA Family: Functional Description) are quite sparse on specific details! cheers, Jamie MorkenArticle: 50265
>I have a 120MHz clock being fed into a global clock pin and would like to be >able to send this clock to an ADC on my board using the DLL for more >clocking options. I think you want to consider that carefully. DLLs add jitter. That's generally bad when ADCs are involved. There was a lot of discussion about this here a while ago. Google-groups might be interesting. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50266
"Jamie Morken" <jmorken@shaw.ca> wrote in news:3PaI9.112724$ea.1983872@news2.calgary.shaw.ca: > Hi, > > I have a 120MHz clock being fed into a global clock pin and would like > to be able to send this clock to an ADC on my board using the DLL for > more clocking options. I've read the datasheet but am a bit confused, > should I use one of the 4 DLL's as the output to the ADC clock input? > So for my package pin75 is one of the DLL's so would I connect this > pin to the clock input of the ADC? > Xilinx datasheets ie. (Spartan-IIE 1.8V FPGA Family: Functional > Description) are quite sparse on specific details! > > cheers, > Jamie Morken > > > Jamie, You can route the output of a DLL to any pin you want, but before you use that, I suggest you to reconsider your design: There is no way you can use a DLL output to clock an ADC in that frequency domain, because of the induced jitter ( which typically 100ps on a SPIIe ). See for instance AD application note AN-501 for more details hth SylvainArticle: 50267
>The value of "33 ohms" is based purely on a recommendation by >technical support at the company from whom we (my research group) >purchased 16 boards with Xilinx XCV600E's on them. > >These boards have a high density I/O connector (68 pins = 34 signal + >34 ground) SCSI interface similar to the one we are using . >That is single ended. Get out your scope and take a look. > I do NOT know the impedance of either the SCSI cable OR the SCSI > connector. The SCSI spec describes the impedance the cable must have. I think it's over 100 ohms. Up to 130? > Infact, this connector is from COMMCON and the tech-support at > COMMCON says that they have not measured the impedance of these > connectors. I'm assuming this is a normal SCSI connector. It is small relative to the rise/fall times used by SCSI so the impedance of the connector doesn't matter much. It will probably work OK for you unless you are using very fast edge rates. Your reflections (from the connector) will be less of a problem with slower edge rates, so try things like lower drive current. "Try" means look at the receive end with a scope. -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.Article: 50268
Hi, > > I have a 120MHz clock being fed into a global clock pin and would like > You can route the output of a DLL to any pin you want, but before you use > that, I suggest you to reconsider your design: There is no way you can use > a DLL output to clock an ADC in that frequency domain, because of the > induced jitter ( which typically 100ps on a SPIIe ). See for instance AD > application note AN-501 for more details Ok, would it be ok to route the global clock 120MHz signal into an I/O pin and drive the ADC with that? cheers, JamieArticle: 50269
No, don't do it. You'll get lousy noise performance because of the jitter
introduced by the DLL (clock jitter at the ADC creates a sampling jitter, which
in turn translates to noise if your signal input changes from sample to
sample). Instead, run the clock directly to the ADC and to the FPGA. At 120
MHz you may have problems with driving both the ADC and the FPGA. Low skew
buffers can sometimes help, but you need to watch the jitter specs on those too
because many are PLL based. If you select an ADC with a Data Ready output that
transitions (DDR style) on each valid sample, you can use that as the clock into
the FPGA assuming your ADC is always running, and that should drive the DLL in
the FPGA via a clock pin.
Jamie Morken wrote:
> Hi,
>
> I have a 120MHz clock being fed into a global clock pin and would like to be
> able to send this clock to an ADC on my board using the DLL for more
> clocking options. I've read the datasheet but am a bit confused, should I
> use one of the 4 DLL's as the output to the ADC clock input? So for my
> package pin75 is one of the DLL's so would I connect this pin to the clock
> input of the ADC?
> Xilinx datasheets ie. (Spartan-IIE 1.8V FPGA Family: Functional Description)
> are quite sparse on specific details!
>
> cheers,
> Jamie Morken
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50270Kevin Brace wrote: > > I thought Icarus Verilog was only a simulator. > How good is the synthesis tool, and what devices are supported? > The XC4K family of parts can be targeted by the "-txnf" code generator. This code generator uses an older synthesizer and is pretty darn picky about what it can synthesize. The netlist format is XNF. The coming 0.7 release (and the recent snapshots) adds a new synthesizer that is used by the "-tfpga" code generator. This new synthesizer is much better, but currently the -tfpga only has practical support for Xilinx Virtex family parts, which includes Spartan II. The prerelease of version 0.7 includes a sqrt-virtext.v example that is heavily commented to step you through generating code for a Spartan II. The -tfpga code generator is better structured then the -txnf code generator, and should be easier to extend to support more part families, from a variety of vendors. Icarus Verilog synthesis is still under development -- black box support is missing, for example -- but is getting there. -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, steve at picturel.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep."Article: 50271
An additional note. If this were for some other application that was not sensitive
to jitter, then you would do well to refer to the app note on DLLs. I think it is
XAPP132, although I believe there are several now that say pretty much the same
thing. Do a search for "clock DLL" restricted to app notes on the xilinx web site
search page.
At 120 Mhz, the DLL jitter of will limit you to about 6 bits of equivalent ADC for
a full scale signal because of the effect on the noise floor. If your input signal
is much slower, then it is not as much of a problem. I do understand the motivation
for using a DLL (the clocking flexibility), but it is important to recognize the
cost. If the clock flexibility is a must, I would use a PLL with dividers in a
package by itself (you don't want other stuff switching), and be very careful about
circuit layout and bypassing. Keep the PLL well away from anything digital. PLLs
have an advantage of reducing jitter when compared to DLLs, but only if there is no
noise in the loop. No noise is difficult enough on a carefully designed borad, and
nearly impossible if done in the same device as a bunch of digital logic (what I am
saying is that you don't want to drive your ADC from an Altera part either, even
though it uses PLLs instead of DLLs).
Ray Andraka wrote:
> No, don't do it. You'll get lousy noise performance because of the jitter
> introduced by the DLL (clock jitter at the ADC creates a sampling jitter, which
> in turn translates to noise if your signal input changes from sample to
> sample). Instead, run the clock directly to the ADC and to the FPGA. At 120
> MHz you may have problems with driving both the ADC and the FPGA. Low skew
> buffers can sometimes help, but you need to watch the jitter specs on those too
> because many are PLL based. If you select an ADC with a Data Ready output that
> transitions (DDR style) on each valid sample, you can use that as the clock into
> the FPGA assuming your ADC is always running, and that should drive the DLL in
> the FPGA via a clock pin.
>
> Jamie Morken wrote:
>
> > Hi,
> >
> > I have a 120MHz clock being fed into a global clock pin and would like to be
> > able to send this clock to an ADC on my board using the DLL for more
> > clocking options. I've read the datasheet but am a bit confused, should I
> > use one of the 4 DLL's as the output to the ADC clock input? So for my
> > package pin75 is one of the DLL's so would I connect this pin to the clock
> > input of the ADC?
> > Xilinx datasheets ie. (Spartan-IIE 1.8V FPGA Family: Functional Description)
> > are quite sparse on specific details!
> >
> > cheers,
> > Jamie Morken
>
> --
> --Ray Andraka, P.E.
> President, the Andraka Consulting Group, Inc.
> 401/884-7930 Fax 401/884-7950
> email ray@andraka.com
> http://www.andraka.com
>
> "They that give up essential liberty to obtain a little
> temporary safety deserve neither liberty nor safety."
> -Benjamin Franklin, 1759
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50272I'm trying to measure the power consumption of a Xilinx CoolRunner CPLD. It doesn't need to be extremely accurate. I've put a 1 ohm resistor between my +ve power supply and my board's VCC, and measured the voltage across that, which gave me 6.7 mV. This would imply that 6.7 mA of current is being drawn, although the CoolRunner should draw current in the range of uA. Is there anything wrong with this simple setup? Thanks, JohnArticle: 50273
"Jamie Morken" <jmorken@shaw.ca> wrote in news:pAbI9.169499$ka.3843005@news1.calgary.shaw.ca: > Hi, > >> > I have a 120MHz clock being fed into a global clock pin and would >> > like > >> You can route the output of a DLL to any pin you want, but before you >> use that, I suggest you to reconsider your design: There is no way >> you can use a DLL output to clock an ADC in that frequency domain, >> because of the induced jitter ( which typically 100ps on a SPIIe ). >> See for instance AD application note AN-501 for more details > > Ok, would it be ok to route the global clock 120MHz signal into an I/O > pin and > drive the ADC with that? > > cheers, > Jamie > > I wouldn't recommend it, either. Basically, an ADC sampling clock must be considered as an analog signal, and routing it through a digital chip is not a ood idea ( it will introduce noise ). As Ray explains in his comment, a better solution is an analog PLL with divider, in a separate component. Unless you are constrained by power issues, you can also feed the ADC with 120 MHz, and do a digital down conversion in the FPGA. hth Sylvain YonArticle: 50274
It looks OK. The uA are static current without load. So real power depends on flip flops toggleing and of course output driving. Maybe your 6.7mA are just the current required to drive your loaded outputs high. Regards Thomas John wrote: > I'm trying to measure the power consumption of a Xilinx CoolRunner > CPLD. It doesn't need to be extremely accurate. I've put a 1 ohm > resistor between my +ve power supply and my board's VCC, and measured > the voltage across that, which gave me 6.7 mV. This would imply that > 6.7 mA of current is being drawn, although the CoolRunner should draw > current in the range of uA. Is there anything wrong with this simple > setup? > > Thanks, > John
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