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Hal Murray wrote: > Are other people paranoid about this sort of thing? Yes. I'm mostly a Xilinx designer. For every design I write a UCF file with every ball/pin listed in sorted order, including unused pins (CONFIG PROHIBITED) and Power/ground/etc (as comments). This makes it easier to check, recheck and verify. And then we verify and check it. Paranoia can be a good thing. -- Phil HaysArticle: 50401
In article <erj4ta.s94.ln@miriam.mikron.de>, Bernd Paysan <bernd.paysan@gmx.de> wrote: > I made a tiny Forth processor to fit into a small FPGA, you can find it on > http://www.jwdt.com/~paysan/b16.html > There's also Gerber data for a demonstration board with an Altera > Flex 10K30E. Today, I suggest using the new Cyclones, because the > smallest one is very cheap, and the configuration devices are also > not that expensive anymore. The new Cyclones look like very interesting components, but they don't seem all that easy to get hold of; I can't find a manufacturer of an evaluation board [in fact, I'm having trouble finding information about evaluation boards for anything other than Xilinx chips]. Yes, the press releases say that they're very cheap, but precede that with "in quantity 250K". They're TSMC 0.13u devices, so I imagine there are enormous availability problems at the moment. Tom, rather tempted by a $200 Spartan2E board, and thinking that FPGAs are an odd but potentially entertaining way to start learning about electronic design. Or do I need to know a whole lot more than I do about passive components before I can do anything useful with an FPGA other than marvelling at the pretty blue smoke coming out of it.Article: 50402
This may be an incoherent request, but I'll go ahead. When I last played with electronics, resistors were little cylindrical things with long wire legs, and ICs had at most forty pins, which came out of the side at convenient 2.54mm spacing; you could design on bread-board. If you wanted to connect to a computer, you used the parallel port, or the four-channel analogue-digital converter on the BBC Micro joystick port. If you were really advanced, you might try to build a two-layer PCB with little metal fingers at the bottom to plug into an ISA slot on a PC. Nowadays, passive components are little flecks of ceramic with solder pads at each end, small ICs come in tiny flat-packs with centipede fringes of legs around, and the interesting ones come either in large flat-packs with centipede fringes, or in BGA form. And I presume the signal-integrity requirements are such that bread-board, and even the two-layer PCB, are Right Out. The BBC Micro and the ISA slot have gone the way of the dinosaur; the parallel port is dying out. So, what do people do to prototype now? As I read it, you do a lot in simulation and then, once you're happy with a design, you send a file to a boutiquie to get a PCB made and the components fitted to it. How much does it cost to get one two- or four-layer PCB made, how long does it take, and do you have to provide the company with all the components you want fitted, or will they have 1kohm surface-mount resistors and 555 oscillators in stock? How do you interface widgets to a computer nowadays? Are there chips which can convert USB or PCI to something easier to contemplate; is it practical for a hobbyist to connect things to the PCI bus? Which is the right group for me to be asking these questions in? TomArticle: 50403
> Are those Cyclone/Configuration parts really out in the wild? I heared from Altera rep. in Austria that they will be available Q2 2003. So we have to wait ;-| I really would like to build a board with one of them, perhaps I can get an engineering sample earlier? Martin -- JOP - a Java Optimized Processor for FPGAs. http://www.jopdesign.comArticle: 50404
> The new Cyclones look like very interesting components, but they don't > seem all that easy to get hold of; I can't find a manufacturer of an > evaluation board [in fact, I'm having trouble finding information > about evaluation boards for anything other than Xilinx chips]. Yes, As soon as I can get samples I will provide a board. It will be the same as one I built for ACEX 1K50 (which you can use in the mean time.). A little AD: http://www.jopdesign.com/board.html > the press releases say that they're very cheap, but precede that with > "in quantity 250K". prices I got: $15 for ep1c3 and $30 for ep1c6 in quantity of 500. Add 10% for smaller quantities. For ACEX 1K50 I paid EUR 22 for 10 pcs. > > smallest one is very cheap, and the configuration devices are also > > not that expensive anymore. I'm using normal Flash (512 KB) with a small PLD (MAX7032) for configuration. The rest of the Flash can be used to store application program and data. Since the Flash can be programmed from the FPGA I can change conifguration data even over the Internet :-) > electronic design. Or do I need to know a whole lot more than I do > about passive components before I can do anything useful with an FPGA > other than marvelling at the pretty blue smoke coming out of it. No! Have never smoked one. Even when configured with wrong VCCIO setting or short curcuit outputs it got only a little bit hotter than usual.... Martin -- JOP - a Java Optimized Processor for FPGAs. http://www.jopdesign.comArticle: 50405
Hi Tom, > So, what do people do to prototype now? As I read it, you do a lot in > simulation and then, once you're happy with a design, you send a file > to a boutiquie to get a PCB made and the components fitted to it. How > much does it cost to get one two- or four-layer PCB made, how long > does it take, and do you have to provide the company with all the > components you want fitted, or will they have 1kohm surface-mount > resistors and 555 oscillators in stock? In my case (as I do prototyping with FPGAs) I first design a PCB along with the pinout of the FPGA. It really helps in PCB routing when you can change the pinout of the FPGA. The first PCB get's produced at http://www.pcb-pool.com. They have reasonable pricing. Then I have to wait for a 'good day' to solder the parts. It is possible to hand solder 0.5 mm pitch even with an old 30 W solder iron (But I've also seen some destroyed PCBs/chips, so be careful). When everything is ok the complete PCB will be produced by someone else. They also buy the parts for you (and get better prices). But you have to be careful with your part list... The price is ok even for small quantitys like 20 pcs (second stage of prototyping), but the setup cost is about EUR 800. > How do you interface widgets to a computer nowadays? Ethernet with a simple (and cheap) CS8900. > Which is the right group for me to be asking these questions in? I think it's a little bit off topic, since most use ready made FPGA prototyping boards (like the famous ones from BurchED). comp.arch.embedded is a group where you can find a lot of 'hardware hackers'. Martin -- JOP - a Java Optimized Processor for FPGAs. http://www.jopdesign.comArticle: 50406
Even without the DLL, I would caution against doing the divider in the FPGA.
First, the FPGA can induce a fairly significant jitter even without the DLL
due to shifting input thresholds from changing I/O currents. Second, at 120
MHz, you virtually need to use the DLL in the FPGA to get reasonable control
of your I/O setup, hold and clock to Q times. Without the DLL, the prop delay
to get a signal off the chip and then back on can greater than the clock
period it the DLL is not used to compensate for the clock distribution. You
are better off using an external 40 MHz clock, feeding it to the ADC and the
FPGA and then multiplying it up inside the FPGA with the clkDLL. At 40 MHz, a
decent clock buffer chip will keep you at single source-single destination
distribution of the clock and the induced skews will not be a big problem. At
higher rates, I'd use an ADC with a DR output and use that to clock the fpga
as I mentioned before.
rickman wrote:
> Hal Murray wrote:
> >
> > >Is the downsampling filter a seperate chip, or is it just a core in the
> > >fpga?
> >
> > Classic downsampling in this sort of DSP/FPGA context is a neat trick
> > to get away with a less expensive analog filter. Suppose your signal
> > has a bandwidth of 1 MHz, so you need to sample at 2 MHz. But you also
> > need a filter that gets rid of everything over 1 MHz or it will get
> > aliased back to below 1 MHz. Brick wall filters are impossible to
> > expensive depending upon how close you get. If you build a reasonable
> > filter, it lets stuff through up to (say) 3 MHz. So you run your
> > A/D to 8 MHz, knowing that the filter has killed everything below
> > 4 HMz. Then you run a digital filter that throws away everything
> > below 1 MHz. Nyquist now tells you that you don't need that many
> > samples, so you can just throw away the ones you don't need.
> >
> > In the case that started this discussion, he wanted to make a 40 MHz
> > clock for the A/D, but he was starting with a 120 MHz clock. Seems
> > obvious that he could just throw away 2 out of 3 samples. There
> > may be something better to do, but I'm not smart enough to see it.
> > Might be something like you can get rid of some noise if you run
> > through a filter that throws away the bandwidth you don't need.
>
> Actually in this case downsampling is a poor alternative to running the
> ADC at the correct rate with an analog filter. It is *much* more
> difficult to run an ADC at 120 MHz than it is at 40 MHz. The ADC will
> use much more power at 120 MHz as well.
>
> The original question was about using a DLL to generate a 40 MHz clock
> from a 120 MHz clock. You don't need a DLL for that. You can just
> implement a divide by three. If you need a symetrical square wave to
> drive the ADC you can make a circuit that runs off of both phases of the
> clock without using the DLL. The digital circuitry should not add
> significant jitter to the clock.
>
> To answer Jamie's question about noise vs. sample rate, yes, typically
> faster ADC operation results in poorer performance in ADCs. Not
> necessarily due to clock issues, but just because the ADCs create more
> noise at higher rates. That is why the number of bits goes down as the
> sample rate goes up.
>
> --
>
> Rick "rickman" Collins
>
> rick.collins@XYarius.com
> Ignore the reply address. To email me use the above address with the XY
> removed.
>
> Arius - A Signal Processing Solutions Company
> Specializing in DSP and FPGA design URL http://www.arius.com
> 4 King Ave 301-682-7772 Voice
> Frederick, MD 21701-3110 301-682-7666 FAX
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50407Hi Javi, You have to remember one very important thing: ISE is for making -chips-. Not for simulating VHDL. Which means: "wait for" is not synthesizable. ISE (XST) won't do it. (Hence the "unsupported" message) Any signal that does not leave the chip is optimized out. None of your signals leave the chip, so they are -all- optimized out. SH7 On 10 Dec 2002 02:35:18 -0800, javodv@yahoo.es (javid) wrote: >Hello, > >I have made a simple VHDL program that have three VHDL modules >(WAVE_GEN, CONTROLLER, RAM512). I have in my WAVE_GEN code "wait for >40 ns;". The problem is that when I try to generate a symbol ISE tells >me " Wait for statement unsupported". I also have made a "TOP" VHDL >module that instantiate the three previous modules and interconnects >them with signals. This "TOP" module is for conecting the waves >generated by WAVE_GEN to the other VHDL modules. My problem here is >that when I simulate this TOP module I don't see any signal, etc. in >Modelsim window because this "TOP" module doesn't have ports. How can >I see the internal signals?? > >Thanks a lot and regards, > >JaviArticle: 50408
I am doubly paranoid about it. I use the .pad file output from the Xilinx
tool and compare that against the board.
Phil Hays wrote:
> Hal Murray wrote:
>
> > Are other people paranoid about this sort of thing?
>
> Yes.
>
> I'm mostly a Xilinx designer. For every design I write a UCF file with
> every ball/pin listed in sorted order, including unused pins (CONFIG
> PROHIBITED) and Power/ground/etc (as comments). This makes it easier to
> check, recheck and verify. And then we verify and check it.
>
> Paranoia can be a good thing.
>
> --
> Phil Hays
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50409
This is only an issue for the 10K and its derivatives. 20K, mercury and stratix have 3 flip-flops
per IOE, one for each direction and one for the tristate.
Kevin Brace wrote:
> From my experience dealing with PCI, avoid Altera devices
> because the lack of multiple FFs per IOE makes it hard to meet Tval
> (Tco), and their floorplanner is broken compared to Xilinx.
> The floorplanner issue of Altera makes it hard to meet Tsu.
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50410
Wait for is not a synthesizable construct. Think about it, how would you
build digital hardware that would 'wait for 40 ns'? They key do doing
good VHDL designs is to visualize the hardware you need to accomplish your
task, then write the VHDL to produce that hardware. Trying to start at a
program type description and putting the intelligence to make hardware out
of it on the synthesizer is at best going to give you poor results, or as
you found out produce something unsynthesizable.
javid wrote:
> Hello,
>
> I have made a simple VHDL program that have three VHDL modules
> (WAVE_GEN, CONTROLLER, RAM512). I have in my WAVE_GEN code "wait for
> 40 ns;". The problem is that when I try to generate a symbol ISE tells
> me " Wait for statement unsupported". I also have made a "TOP" VHDL
> module that instantiate the three previous modules and interconnects
> them with signals. This "TOP" module is for conecting the waves
> generated by WAVE_GEN to the other VHDL modules. My problem here is
> that when I simulate this TOP module I don't see any signal, etc. in
> Modelsim window because this "TOP" module doesn't have ports. How can
> I see the internal signals??
>
> Thanks a lot and regards,
>
> Javi
--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930 Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com
"They that give up essential liberty to obtain a little
temporary safety deserve neither liberty nor safety."
-Benjamin Franklin, 1759
Article: 50411hello, I want to know what is going on during FPGA startup or configuration: 1- will the clock be running through the chip? 2- when the chip reset pulse will be triggred? 3- what is the event that will flag the time for inputting the input data? My question might looks vague, but want to know how all those events are synchronised, especially with the DLL locking problem thanks -- Posted via Mailgate.ORG Server - http://www.Mailgate.ORGArticle: 50412
This is a multi-part message in MIME format. --------------388C1674730A7E65BB711BE1 Content-Type: multipart/alternative; boundary="------------0381037C12B5032E5C7B5C12" --------------0381037C12B5032E5C7B5C12 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit John, Your setup sounds OK. Just ensure your voltmeter can measure about 20uV reliably and accurately. I say 20uV because, using a 1 ohm resistor, 20uA correlates to about the lowest current consumption I have seen on a CoolRunner XPLA3 CPLD. Also ensure that the 1 ohm resistor is in series with the CPLD _only_, so that no other devices contribute to the power consumption through the resistor. All CoolRunner CPLDs are guaranteed to consume <100uA at quiescent, which means no logic or I/Os are toggling. Once logic or I/Os start toggling, the device will consume more power. Also, any capacitive or resistive loads on the I/O pins will cause more power consumption by the CPLD since the I/O must drive these loads and the current to do so is realized from the Power/GND pins. I/O loads include other device's capacitive/resistive inputs, bus terminations, trace capacitance, etc. 6.7mA does not seem unusual if your design had I/Os and logic toggling. For example, if you look at the xcr3256xl data sheet figure1/table1 show current consumption for the device loaded with 16 bit binary up/down counters. According to the data sheet, a 10MHz clock to the CPLD will cause the device to draw 9.69mA. I have also used a high precision ammeter, but that requires that you put it in series with the power source which, I'm sure, would be intrusive to your board. Hope this helps! John Hubbard John wrote: > I'm trying to measure the power consumption of a Xilinx CoolRunner > CPLD. It doesn't need to be extremely accurate. I've put a 1 ohm > resistor between my +ve power supply and my board's VCC, and measured > the voltage across that, which gave me 6.7 mV. This would imply that > 6.7 mA of current is being drawn, although the CoolRunner should draw > current in the range of uA. Is there anything wrong with this simple > setup? > > Thanks, > JohnArticle: 50413
> But that's the problem only with DK1, I wonder it's working correctly with DK1.1 The fast simulator, introduced in DK1.1 does not check for incorrect rom/ram/wom accesses. In the interrests of simulation speed, the fast simulator implements the rom as an array. If you switch to the netlist simulator in DK1.1, your program will fail in the same manner as it would have done when simulated with DK1. To fix your program, you need to remove the "rom" keyword from your definition of Sub. > > Does DK1.1 supports multiple access to ROM in a single clock cycle? No versions of DK or Handel-C support accesses of a rom at multiple indices during the same clock cycle.Article: 50414
"Martin Schoeberl" <martin.schoeberl@chello.at> wrote: >>It seems like a stack based machine would be more suitable for this kind >>of application because the instruction size is smaller, allowing more >>compact > Thats perfectly rigth. Things are a lot easier with a stack architecture > (but also slower since you need more cycles for basic operations than on a > RISC CPU). Why would that be? The simulation I built as a college project was faster than any of my classmates', so I'm a bit sceptical. > The advantage of Java over Forth is (in my opinion) that the language is > widle used and you get a rich toolset for free. No doubt. The advantage of Forth is that it's well-suited as-is for running hardware, and once you have it running Java can be implemented on top. I would rather use Forth as a machine language than Java bytecodes. > I don't know if Forth is > still used for real world applications. Would like to hear about it. If > there is a new wave in the Forth direction I have to change my CPU :-) I doubt the existance of any New Wave in Forth, but it's used -- Open Firmware, for example, is Forth, and is used in all PowerMacs and Suns. > Martin -BillyArticle: 50415
Synplify supports a number of ways of treating hierarchy in synthesis. The default operation is that Synplify looks at each level of hierarchy and decides automatically whether it can get a better result by preserving or dissolving the level of hierarchy. Later in the flow it will perform boundary optimizations which may shift the exact positions of the boundaries. If you want to control this behaviour, look up the syn_hier attribute in the manual. You can force the dissolve or force hierarchy to be maintained and turn boundary optimization off. I would try the default behaviour first. It usually gets the best result. Stepping beyond this, in Synplify 7.2 we introduced some new capabilities for an incremental flow where you mark some levels of hierarchy as incremental compile points. This can speed up synthesis, but more importantly it creates a very clean flow through incremental place and route. You can look this up in the manual under the name "MultiPoint". - Ken McElvain CTO, Synplicity Inc. Tom Hawkins wrote: > Hi, > > Obviously hierarchy is essential when building and managing > any large design. But I'm curious how synthesis tools use > hierarchy during the optimization process? Just how critical > is hierarchical partitioning of a design for quality synthesis? > > I remember talking to a Mentor rep a few years ago. At > the time he said the major advantage of Leonardo over > Synplicity was Leo's use of design hierarchy > compared to Synplify which just optimizes a flattened design. > If this was true, is it still the case? > > Just in terms of synthesis, is hierarchy and partioning > important or not? Yes - but the tool can usually figure it out on its own. > > Thanks, > Tom >Article: 50416
Hi, Use the website below to get a free layout editing tool. It has user manuals which help you build your multiplier as well as many other features such as schematics. You can also build a schematic and then automatically generate a layout. I have used the tool and found it to be fairly decent for class projects. The best part is that the tool is absolutely FREE !! http://intrage.insa-tlse.fr/~etienne/Microwind/index.html bye, Prashant compresstransform2002@hotmail.com (transformer) wrote in message news:<4a96bae1.0212081216.60ca70bf@posting.google.com>... > Dear All, > I have completed my work on a radix-4 booth multiplier. Now I have to > complete its vlsi layout. Unfortunately, I have only some vhdl > knowledge and completely new to vlsi design. Which free or low-priced > vhdl design software is suitable for my needs. > ThanksArticle: 50417
I want to know what are the different events happening during FPGA startup and how they are synchronised? 1- will the clock be running during this period of time? (although that the DLL is not yet locked.? 2- when the reset pulse will be sent? 3- what is the event that will flag the input of data samples ? thanks sorry if this post has already appeared, i can't see it through my systemArticle: 50418
I'm currently working on an "FPU" like this (i.e. LNS computations).
The best way I know of computing a LOG is described in Prof. Koren
Computer arithmetic book in chapter 9 (if I recall correctly). It is also
fairly easy to implement if you don't mind a significant latency.
Good luck,
Normand
"Philip Freidin" <philip@fliptronics.com> a écrit dans le message de news:
9k8bvu8l7702pr83vaujljquuk3pp5uqjv@4ax.com...
>
> Some time back, a company called LogPoint was offering an
> alternative to floating point arithmetic, based on logarithms,
> and depended on a fairly efficient float to log conversion.
> (I had discussions with them, at least 5 years ago)
> I seem to remember that the LOG wizard was a guy by the name
> of Lester Pickett.
>
>
> http://www.mjourney.com/news/News_from_Greece/632.Log_Point.shtml
>
> unfortunately, this seems to be dead: www.logpoint.com
>
> Have a look at patent 5197024 at www.uspto.gov for all the details.
>
> Philip
>
>
>
> On Fri, 22 Nov 2002 12:51:19 -0000, "Tim Nicolson"
> <t.nicolson@signal.qinetiq.com> wrote:
> >hi all.
> >
> >I'm currently implementing an image processing algorithm in hardware.
> >
> > ......
> >
> >Unfortuately, adding extra terms to the poly increases the accuracy
slowly.
> >
> >So.... Does anyone know of a better way of computing the logarithm of a
base2 fp number?
> >
> >Thanks very much for your time.
> >
> >Tim
> >
> >
> >Tim Nicolson
> >Reseach Engineer
> >QinetiQ
> >Malvern
> >UK
>
> Philip Freidin
> Fliptronics
Article: 50419Your description is correct. The four I/O (DLL) pins can be used several ways, either to enhance the use of the DLL or to provide for differential signaling. The most significant is that they can be used as inputs to the DLLs without having to use one of the global clock inputs. These are primarily intended for the external feedback input needed when the DLL is used for board-level de-skew. As inputs to the DLL, they are standard single-ended inputs. These pins have a second function as the N side of a differential clock input, with the adjacent global clock input always being the P side. They can also be used as general-purpose I/O independent of the DLL and clock functions, and can be paired together to make a general-purpose differential I/O. The signal names indicate the pairing of the DLL pins for general-purpose differential I/O, and there is a separate table showing how they can be paired with the clock input for a differential clock signal. Markus Meng wrote: > hi all, > > reading the datasheet of the new Spartan-IIE devices, I find > four more DLL input pins, mainly used for differential input > signalling. > > What exactly is the enhancement? Is it now like that, that I > can use the four global clock inputs and at the very same time > the four DLL[0..3] named inputs for DLL feedback for example. > > This would be an enhancement compared to Spartan-II if the signals > are single ended. > > markus -- Marc Baker Xilinx ApplicationsArticle: 50420
"hristo" <hristostev@yahoo.com> schrieb im Newsbeitrag news:b0ab35d4.0212100914.5794e541@posting.google.com... > I want to know what are the different events happening during FPGA > startup and how they are synchronised? > > 1- will the clock be running during this period of time? (although > that the DLL is not yet locked.? > 2- when the reset pulse will be sent? > 3- what is the event that will flag the input of data samples ? > thanks At the end of the configuration, when all data bits have been shifted into the FPGA, there is something happen called startup sequence. They has 6 (8?) phases, during which various global signals will be switched. GSR (global set/rest for FlipFlops) will be released GTS (global tristate for IOs) will be released GWE (global write enable for FlipFlops /RAMS) will be released DONE goes active/tristate The order can be configured, also the sequence can wait for the DLL(s) to achieve lock. The clock for clocking the startup-sequence can be choosen between CCLK, JTAG clock (TCK) and a user clock. -- MfG FalkArticle: 50421
"William Tanksley Google" <wtanksley@bigfoot.com> wrote in message news:de3fc1ef.0212100859.e954eee@posting.google.com... > "Martin Schoeberl" <martin.schoeberl@chello.at> wrote: > >>It seems like a stack based machine would be more suitable for this kind > >>of application because the instruction size is smaller, allowing more > >>compact > > > Thats perfectly rigth. Things are a lot easier with a stack architecture > > (but also slower since you need more cycles for basic operations than on a > > RISC CPU). > > Why would that be? The simulation I built as a college project was faster > than any of my classmates', so I'm a bit sceptical. A stack machine will require more cycles per instruction. So by the cycles per interction metric they are slower. But perhaps a stack machine is simple enough that it can have a faster cycle time, or perhaps the instructions give a higher computation yeilld than risc instructions.Article: 50422
Martin Schoeberl wrote: > > > Are those Cyclone/Configuration parts really out in the wild? > > I heared from Altera rep. in Austria that they will be available Q2 2003. So > we have to wait ;-| > > I really would like to build a board with one of them, perhaps I can get an > engineering sample earlier? There is not much point in starting early with a part like this. You will need the tools and they can be in worse shape than the hardware with early releases. There are lots of other parts available from both Altera and Xilinx. At this point in time I would recommend the Spartan II parts from Xilinx. They are real, low cost and the latest announced members go up to 600K gates. I am sure you can find already designed boards with these parts. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50423
Thomas Buerner wrote: > > thanx for all the answers > > it seems that it is a lot more complicated than I hoped it would be. > we have dozens of old-fashioned isa vga cards here > so I thought it is a cheap way of getting a screen output > from an FPGA. > are there cheap RAMDACs that can be used for this purpose? > probably interfacing them is easier I can't remember company names, but RAMDACs were a dime a dozen at one point, and fast too! But I believe this function is integrated into the GPU chips now. But you might still be able to find some RAMDACs around. Look at your VGA boards and see what they are using. Then check those manufacturers web site. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAXArticle: 50424
Ray Andraka wrote: > > Even without the DLL, I would caution against doing the divider in the FPGA. > First, the FPGA can induce a fairly significant jitter even without the DLL > due to shifting input thresholds from changing I/O currents. Second, at 120 > MHz, you virtually need to use the DLL in the FPGA to get reasonable control > of your I/O setup, hold and clock to Q times. Without the DLL, the prop delay > to get a signal off the chip and then back on can greater than the clock > period it the DLL is not used to compensate for the clock distribution. You > are better off using an external 40 MHz clock, feeding it to the ADC and the > FPGA and then multiplying it up inside the FPGA with the clkDLL. At 40 MHz, a > decent clock buffer chip will keep you at single source-single destination > distribution of the clock and the induced skews will not be a big problem. At > higher rates, I'd use an ADC with a DR output and use that to clock the fpga > as I mentioned before. Maybe I am confused, but I don't remember anyone saying that the 120 MHz clock was being used to handle the data from the ADC. I had the impression that the OP simply wanted a 40 MHz clock for the ADC. I was not aware that the FPGA would add significant jitter to clocks passing through the chip. I guess if the jitter sensitivity of the ADC is that critical, then the clocking needs to have very special attention paid. But I can't remember seeing an existing ADC design around 40 MHz that was so carefully done. But then perhaps these were not good jobs. -- Rick "rickman" Collins rick.collins@XYarius.com Ignore the reply address. To email me use the above address with the XY removed. Arius - A Signal Processing Solutions Company Specializing in DSP and FPGA design URL http://www.arius.com 4 King Ave 301-682-7772 Voice Frederick, MD 21701-3110 301-682-7666 FAX
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