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Alfredo Rosado wrote: > Hi, > I am trying to build some kind of architecture to delay a signal > (typical delay ranging from 1 to 3 useconds). I have thought of doing > it > with chained flip-flops, but if I have a fast clock signal, it will You can build a virtual shift register in the synchronous RAM of the XC4000E or XC4000XL devices, which gives you 32 bits per CLB. Or you can use a presettable synchronous counter. There are lots of ways of doing this, depending on your constraints. You will never get close to microseconds by just concatenating logic delays of a few nanoseconds each. Peter Alfke, Xilinx ApplicationsArticle: 10476
CPUs in FPGAs are already being done at some schools. I did a project as an undergrad at the University of Winsconsin, that used Xilinx FPGAs to implement a full student-designed ISA, from start to finish. There are a lot of limitation with using FPGAs (as we found... and this was 3 years ago...). Perhaps the biggest was bus size... Our implementation used only 8 bit registers (it was a dual, threaded processor). The whole project (6 FPGAs, external SRAM, external UART) was wirewrapped (a wiring extravaganza!) and ended up running at about 8MHz. Quite a technical achievement. We were also responsible for developing a compiler/assembler and working applications (the wonder and amazement generated by Tetris running on a processor built by a group of college students is probably a whole lot more than any non-EE could realize:). I'm sure the class is still being taught since it was one of the most popular in the EE department. Regards, Shane -- >I think that is an excellent point. When I was in grad school, I wanted >to implement a simulation of a microcoded teaching CPU that they used >for a couple of classes. Until then it had only existed on paper. But >the simulation would not have allowed the students to modify or extend >the design easily. This would allow an EE student to play to his hearts >content, and he might actually learn something. ;-) > > >> * Satisfaction: Building a small computer from the gates up >> through the instruction set architecture up through the >> OS and compiler up to apps is a very satisfying exercise, >> akin to building one's own small sailboat. It can be a >> potent antidote to the shrink-wrapped proprietary HW and >> SW we generally must live with. >> >> --Mike > >This is certainly a good reason to do a project in your spare time. The >education you would receive is not trivial either. It appears that a lot >of people have done this with a Forth implementation in mind. Do you >think they are doing this because of the personal satisfaction >motivation or do you think they have commercial motivations in mind? >Article: 10477
In comp.arch.fpga Lardino@ibm.net <lardino@ibm.net> wrote: > CPUs in FPGAs are already being done at some schools. I > did a project as an undergrad at the University of Winsconsin, > that used Xilinx FPGAs to implement a full student-designed > ISA, from start to finish. There are a lot of limitation with using > FPGAs (as we found... and this was 3 years ago...). Perhaps > the biggest was bus size... Here at RMIT (Melbourne, Australia) we did something similar. We implemented the 6805 at the code-compatible level (not timing compatible), using XC3090A parts, including wirewrapping the thing up. This was the data path only, though; control logic was done by an external Am2901-based sequencer, with custom software on PCs to control it all. This was the core third year digital systems subject, and it was a lot of work at the time. Just FYI, Hamish -- Hamish Moffatt, StudIEAust hamish@debian.org, hamish@moffatt.nu Student, computer science & computer systems engineering. 4th year, RMIT. http://hamish.home.ml.org/ (PGP key here) CPOM: [****** ] 66% Nondeterminism means never having to say you are wrong.Article: 10478
Fitz wrote: > Mike, > > Please keep us informed on your progress. > > Thanks, > Fitz > > Mike Butts wrote: > > > In fact, a fine poster paper about a small FPGA-based processor > > was given at FCCM last month. I'm so inspired by it, and by the > > new availability of cheap FPGAs and tools, that I'm developing > > a little minimum-cost FPGA+SRAM board and a similar little > > processor design for it. I'm hoping to make it available by > > the end of the year. (This is strictly a personal hobby effort > > on my part, for fun, experimental and educational purposes.) I have a board already constructed with an Altera part (10K10) for USD$200 PC104 bus, 512KEPROM 32KSRAM, RS232 LCD Display and manual. There will be ADC/DAC board options as well, in the next rev. I have written a micro (actually several) for this. All public domain. Currently writing CAN controller, UART and FIR/FFT functions (public domain when complete) The software to compile for this part is free from Altera (www.altera.com) Steve.Article: 10479
> Just wondered if someone might be able to help before > I pull my last hair out -- I've a little bit of code > in ABEL which I'd like to use as a part of a design > going into one of the Xilinx Spartan things - an XCS30, > to be exact. All it's supposed to do is to generate > even parity over 36 signals. > > Anyway, it turns into a netlist OK; 'bit slow' thought > I, as about 30 minutes passed before the design was fitted. > 'Good Lord!' thought I, as the report showed it filling 87% > of my XCS30. What I'd think to be an equivalent drawn out > as a schematic behaves much more reasonably. Would you like me to try this implementation in an Altera CPLD? The EPF6016 will tackle this with no problems, and may cost you less than a comparable Spartan part. 100 up price EPF6016TC144-3 is USD$19.95 (equiv 650 CLB) TQFP144 Regards, Steve.Article: 10480
Yves, I have never heard about such a problem, so I think you are actually doing something else. Read the first paragraph of the desciption carefully: "...trailing edge of the logic AND of all those four pins, three of which are active Low." What happens in the very beginning, the 40-bit preamble? This is not protected by CRC and resulting Low on INIT. I assume you might have some "dirty" levels or spikes on one of the four control lines ( CS0, CS1, RS and WS ). Peter Alfke, Xilinx Applications Yves Vandervennet TFE wrote: > Hi ! > > We are using XC4000E FPGA's. According to the > Data Book, when configurating the FPGA's, the devices sample the data > on the rising edge of the logical product CS0n and WRn. A > configuration > problem (INITn went always done after the first set of datas) lead > us to observe the DOUT pin. We found out that the data going out on > this pin was the previous byte present on the data bus BEFORE the > microprocessor write operation. Does anybody have a solution for > us ? Do we make a mistake (The setup time of 60ns is respected) ? > > Thank you for your help, > > Have a nice day, > > Yves Vandervennet. > > E-Mail : yves@elmitel.ulb.ac.beArticle: 10481
In article <3564B6A2.51949200@ihug.co.nz>,
Steven Groom <steven.groom@arrow.co.nz> wrote:
>I have a board already constructed with an Altera part (10K10) for
>USD$200 PC104 bus, 512KEPROM 32KSRAM, RS232 LCD Display and manual.
>There will be ADC/DAC board options as well, in the next rev.
>I have written a micro (actually several) for this. All public domain.
>Currently writing CAN controller, UART and FIR/FFT functions (public
>domain when complete)
So what's it like? Where is it available?
--
/* jhallen@world.std.com (192.74.137.5) */ /* Joseph H. Allen */
int a[1817];main(z,p,q,r){for(p=80;q+p-80;p-=2*a[p])for(z=9;z--;)q=3&(r=time(0)
+r*57)/7,q=q?q-1?q-2?1-p%79?-1:0:p%79-77?1:0:p<1659?79:0:p>158?-79:0,q?!a[p+q*2
]?a[p+=a[p+=q]=q]=q:0:0;for(;q++-1817;)printf(q%79?"%c":"%c\n"," #"[!a[q-1]]);}
Article: 10482Hello everybody As a newbie on these newsgroups I decided to ask a question but only after I red them very carefully a few weeks. Now the question: Does anybody know where can I find a **REFERENCE** regarding the logic interchange format files (e.g. Berkeley .PLA files, .BLIF files) and the .JED files used for programming devices (not only PAL's but CPLD's too)? Thank youArticle: 10483
I am trying to implement a graphics processor in Vhdl,Are there any good sites which will highlight common architectures etc. and perhaps even a more detailed description of simple cores etc.Article: 10484
.........----------------==================----
..--==- Fri, 22 May 1998 11:20:03 +1200,
..--==- Steven Groom (SG) mentioned:
SG) Fitz wrote:
)) Mike,
))
)) Please keep us informed on your progress.
))
)) Thanks, Fitz
))
)) Mike Butts wrote:
))
)) > In fact, a fine poster paper about a small FPGA-based processor
)) > was given at FCCM last month. I'm so inspired by it, and by the
)) > new availability of cheap FPGAs and tools, that I'm developing >
)) a little minimum-cost FPGA+SRAM board and a similar little >
)) processor design for it. I'm hoping to make it available by > the
)) end of the year. (This is strictly a personal hobby effort > on
)) my part, for fun, experimental and educational purposes.)
SG) I have a board already constructed with an Altera part (10K10)
SG) for USD$200 PC104 bus, 512KEPROM 32KSRAM, RS232 LCD Display and
SG) manual.
SG) There will be ADC/DAC board options as well, in the next rev.
SG) I have written a micro (actually several) for this. All public
SG) domain. Currently writing CAN controller, UART and FIR/FFT
SG) functions (public domain when complete)
SG) The software to compile for this part is free from Altera
SG) (www.altera.com)
..
~~~~~~~~~================-------------......---
At Rensselaer last semester for a class project, I designed a small
8-bit register to register RISC processor with a stack and subroutines
and a healthy instruction set, and was able to test it on an XC4010E,
with 16 general purpose registers and a small LUT RAM and some
peripherals. Total resource count was about 331 of the 400 CLBs. It
seemed to be stable at a couple tens of MHz.
I had used the Cygnus GNU Win32 tools flex and bison to write an
assembler for it and wrote some bit manipulation to go directly from
assembler to the INIT= statements for the internal RAMS on the XC4010E
which Xilinx uses in its user constraint files.
--
Andrew Veliath
andrewtv@usa.net, veliaa@rpi.edu
Article: 10485Lardino@ibm.net wrote: > We were also responsible for developing a compiler/assembler > and working applications (the wonder and amazement generated > by Tetris running on a processor built by a group of college students > is probably a whole lot more than any non-EE could realize:). Tetris seems to be the standard application for this sort of experience. About a year ago, I was involved in a FPGA based CPU approach, and my part was compiler support (it was a Forth compiler, and I spent only a weekend to do it). But the application to test it was Tetris. -- Bernd Paysan "Late answers are wrong answers!" http://www.jwdt.com/~paysan/Article: 10486
Taken from EETimes SAN JOSE, Calif. — Xilinx Inc. has stopped development work on its XC6200 line of partially reconfigurable field-programmable gate arrays (FPGAs), and the founders of the the company's reconfigurable R&D group in Edinburgh, Scotland, John Gray and Tom Kean, have both left the company. The remaining engineering staff at Edinburgh has been reassigned to develop IP cores for use by Xilinx's customers within the company's FPGAs. However, Xilinx says it remains committed to the partial reconfigurability offered by the XC6200 devices and will offer many of the features of the XC6200 in its next-generation FPGA family, known as Virtex. "John Gray is still working for Xilinx as a consultant," said Roland Triffaux, manager of Xilinx Europe. "Tom Kean and another two engineers have left to start a company in California." That spin-off company, called Quicksilver, is believed to have some backing from Xilinx. Quicksilver is looking to apply reconfigurable logic to multiprotocol handsets for mobile communications, sources said. It is also believed to be working with systems companies on the application of reconfigurable logic. Gray said his departure from the company was amicable. "I am just looking to do something that's more fun again," he said. "It's time to kick back a bit." Meanwhile, Kean is reacquiring the name Algotronix from Xilinx. Kean and Gray led Algotronix Ltd. in the early 1990s before it was acquired by Xilinx in 1993, when it became the basis of the reconfigurable R&D group, and was named Xilinx Development Corp. Algotronix developed a reconfigurable FPGA architecture known as CAL (configurable array logic), which eventually became the XC6200. Kean said the new Algotronix would act as a consultancy and would advise users on the application of reconfigurable logic. Xilinx said the work of the R&D group was largely completed. "The goal of the reconfigurable group in Edinburgh has been achieved," Triffaux said. XC6200 devices would continue to be available for academic and commercial research groups, as they have been in the past. "We never really sold it," Triffaux said. Peter Cheung, a researcher in the department of electrical and electronic engineering at Imperial College of Science and Technology (London), has used XC6200 devices for reconfigurable hardware platforms. "We've heard they are not developing the XC6200," Cheung said. "Unless there is a real commitment to it we may have to look at other things. The tools for 6200 are primitive and not well done. "In many ways it [the XC6200] was a product ahead of its time," he said. "It was a beautifully conceived device but not sufficiently well supported." -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 10487
On the June issue of Discover Magazine, the cover story reports of two computer scientists, Inman Harvey and Adrian Thompson, applying evolution to program a Xilinx XC6216ES. One of the things they did was evolved the FGPA to distinguish a 1KHz input from a 10KHz input. This was done with using only 100 CLBs of the XC6216, and no clock input. After two weeks and 5000 generations, the chip evolved to work great --with one drawback, it's not robust. If programmed to different chips or if input/output pins were reassigned, it wouldn't work. Also, slightly temperature variations have big effects. Is there anybody that applied Thompson's method of programming a FPGA? More information can be found at http://www.discover.comArticle: 10489
For the XILINX student edition stuff cherck at http://www.associatedpro.com. We now carry both the boards and books. You can also get great deals on the Ful;l Foundation kits with the X84 FPGA board. That includes the LATEST XILINX FOUNDATION kits and support. Ewan D. Milne wrote: > Back in April, Peter Alfke wrote: > >Prentice Hall publishes and sells the "Xilinx Foundation Student > >Edition" which supports all XC9500 devices and all XC4000-type devices > >up to 8k gates today, 10k gates in the next upgrade. > >... > > The book and CD appear to be available from amazon.com and also > at Quantum Books in Cambridge, MA. I am considering purchasing > this book and software, but was wondering when the "next upgrade" > would be available and how one would be able to tell which version > of the software was included. I would like to have the capability > to target a design for the XC4010E device, but would be more inclined > to go ahead and purchase the current version if the next upgrade > will not take place within the next year. > > Can anyone (Peter?) shed any light on this subject? > > Thank you in advance for your replies. > > -Ewan -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 10490
The APS -X208 FPGA board is now available with example code which turns it into a 1/2 meg bit random pattern generator. Using the on board DDS the bit frequency is programmable to 30 Mhz. The example allows the board to load bits from a text file. A sync pulse is generated which can be offset to allow bit viewing at any offset easily on a standard scope. The program example can be used for Pseudo Noise sequence generation, bit stream simulation etc. The examples are done in VHDL (FPGAbehavior) ) and C (FPGA control) and will come free on the APS CD included with every APS board. The CD includes schematics and tons of VHDL Examples. The code will also be made available to current customers via the web upon request. The X208 board is available with Foundation VHDL software and can be seen at: http://www.associatedpro.com/x208/prod/x208_product.html Other free FPGA/VHDL examples and tips are available on the APS web including: APS VHDL Tutorial http://www.associatedpro.com/aps/x84lab/ APS Technical Solutions Page http://www.associatedpro.com/Tech_Solutions/aps_tech.html APS Support Page http://www.associatedpro.com/aps_sup.html -- __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ Richard Schwarz, President EDA & Engineering Tools Associated Professional Systems (APS) http://www.associatedpro.com 3003 Latrobe Court richard@associatedpro.com Abingdon, Maryland 21009 Phone: 410.569.5897 Fax:410.661.2760 __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/ __/Article: 10491
Does anybody can help me.. I try to implement on my 80186 based board simple video interface. I try with mc6845 core but I need more than 16 colors 320x200. Thanks :) DejanArticle: 10492
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Article: 10493In comp.arch Bernd Paysan <bernd.paysan@remove.muenchen.this.org.junk> wrote: : Lardino@ibm.net wrote: : > We were also responsible for developing a compiler/assembler : > and working applications (the wonder and amazement generated : > by Tetris running on a processor built by a group of college students : > is probably a whole lot more than any non-EE could realize:). Yep; we had that at the Computation open day at Oxford yesterday, though I think their Tetris was directly hardware-compiled rather than running on an implemented microprocessor - and the board used was RAMless, which was pretty impressive. I was more impressed by 60fps interactive 800x600 Life - which is non-trivial, and probably not even possible, on Standard Commercial Hardware (OK, you can use cell lists rather than an array, but the FPGA approach ran at constant speed independent of population). I think the 64k of SSRAM attached to the FPGA helped. TomArticle: 10494
Thomas Womack wrote: > > In comp.arch Bernd Paysan <bernd.paysan@remove.muenchen.this.org.junk> wrote: > : Lardino@ibm.net wrote: > : > We were also responsible for developing a compiler/assembler > : > and working applications (the wonder and amazement generated > : > by Tetris running on a processor built by a group of college students > : > is probably a whole lot more than any non-EE could realize:). > > Yep; we had that at the Computation open day at Oxford yesterday, though > I think their Tetris was directly hardware-compiled rather than running > on an implemented microprocessor - and the board used was RAMless, which > was pretty impressive. > > I was more impressed by 60fps interactive 800x600 Life - which is > non-trivial, and probably not even possible, on Standard Commercial > Hardware (OK, you can use cell lists rather than an array, but the > FPGA approach ran at constant speed independent of population). I > think the 64k of SSRAM attached to the FPGA helped. Mike Abrash used Conway's Game of Life as the target for his second 'Annual Code Optimization Challenge', a few years ago. The target machine was either a 486 or very early Pentium, i.e. current hardware is quite a bit faster: The two joint winners both achieved twice the performance of my entry, which is still capable of 400 fps in 320x200 resolution on a Pentium MMX. With linear scaling, this corresponds to 53 fps in 800x600, and more than 100 fps for the two winners. On a modern PII even my program would handle 60fps without breaking a sweat. :-) One of the winners, David Stafford, used a cell list to reduce the working set, while the other, a german guy (sorry, I don't remember his name), used logic operations on 32-bit registers to implement the Life counting logic directly. This also means that the german entry probably implemented very nearly the same algorithm as the FPGA setup above. :-) Terje -- - <Terje.Mathisen@hda.hydro.com> Using self-discipline, see http://www.eiffel.com/discipline "almost all programming can be viewed as an exercise in caching"Article: 10495
Our internal customer desires to use an emulation of our current ASIC design implemented in programmable logic. In order to keep the same hierarchy, assure fidelity, reduce engineering time, ... for the ASIC and the CPLD implementations, I wish perform partitioning of the design within the Max+Plus II tool. (We're using Synopsys (VHDL) and passing Max+Plus II hierachical EDIF.) I'm in contact with Altera design support, but I'd like independent verification that the partitioner is usable. Does anyone have any experience (good or bad) with the tool? Robert HamiltonArticle: 10496
FIRST CALL FOR PAPERS
1998 Military and Aerospace Applications of
Programmable Devices and Technologies Conference
The conference will address devices, technologies, usage, reliability,
fault tolerance, radiation susceptibility, and applications of
programmable devices and adaptive computing systems in military and
aerospace systems. The technical program will consist of oral
technical presentations as well as industrial exhibits. The conference
will be held at the NASA Goddard Space Flight Center in Greenbelt,
Maryland.
Presentations are being solicited in all aspects of the use of
programmable elements, devices, and applications for military and
aerospace applications. These include: PALs, FPGAs, PROMs, Programmable
Substrates, FPIC, Programmable Analog Circuits, adaptive computing
systems and related technologies. All presentations are expected to be
technical in nature. Each presenter will be given approximately 20
minutes with a five minute question and answer session immediately
following. Submitted abstracts should be approximately 100 words long
and are due by July 3, 1998. Please include your full correspondence
address including email and fax and a note on your preferred
presentation format.
Notification of acceptance will be posted by 10 July 1998. Conference
proceedings will published and distributed to all attendees. At least
one author must be registered for the conference. Electronic
submissions
are strongly encouraged.
Topics include (but are not limited to) the following:
- Programmable Technologies and State-of-the-Art Devices
A. COTS and MIL/AERO
B. New Technology Development
C. Adaptive Computing Systems
- Radiation Effects, Device Reliability and Element Characteristics
- Device Architecture, Performance, and Capabilities
- Applications and Novel Techniques for Military and Spaceflight
Circuits.
A. Signal Processing
B. High-Speed Designs
C. System Impact of State-of-the-Art Technologies
D. Reconfigurable Processing
E. Low Power Designs
F. Advanced Packaging
- Use of COTS Devices in the Military and Spaceflight Environment
A. PEMS
B. Shielding, Latchup Protection
C. SEE including SEFI and Destructive Effects
D. System Protection
- Testing and Analysis Techniques
- Performance Results
- Use of Programmables in Critical Systems
- Software Tools for Design/Analysis
A. Synthesis
B. Macro Generators
C. Timing Analysis and Simulation
D. Redundancy, Fault Tolerance, and SEU-Hardening
PRELIMINARY CONFERENCE SCHEDULE
September 14 NASA/GSFC Tours
Evening Registration, Happy Hour
September 15 Invited Talk by Janet Barth, Radiation Physics Office
Day 1 Technical Sessions and Industrial Exhibits
Dinner
September 16 Invited Talk (to be announced)
Day 2 Technical Sessions and Industrial Exhibits
September 17 NASA/GSFC Tours
Janet Barth will present: "An Overview of the Radiation
Environment for Spaceflight Electronics"
The conference is sponsored by (preliminary list): NASA/GSFC,
JHU/Applied Physics Laboratory, and the NASA Radiation
Effects Program.
For more information on the conference please see
http://rk.gsfc.nasa.gov/richcontent/Ksymposium/kSymposium.htm
Please Send Abstract Submissions to:
Martha O'Bryan
martha.obryan@gsfc.nasa.gov
Tel: (301) 286-1412
Fax: (301) 286-0220
Local Arrangements:
Janet Jew
janet.jew@gsfc.nasa.gov
Tel: (301) 286-5533
(301) 286-8884
Conference Chair:
Richard Katz
NASA Goddard Space Flight Center
rich.katz@gsfc.nasa.gov
Tel: (301) 286-9705
Conference Co-Chairs:
Alan W. Hunsberger
NSA
awhunsb@alpha.ncsc.mil
Tel: (301) 688-0292
Ann Darrin
Johns Hopkins University/Applied Physics Laboratory
ann.darrin@jhuapl.edu
Tel: (240) 228-4952
Article: 10497Robert L. Hamilton wrote: <snip> > and the CPLD implementations, I wish perform partitioning of the design > within the Max+Plus II tool. (We're using Synopsys (VHDL) and passing > Max+Plus II hierachical EDIF.) I'm in contact with Altera design > support, but I'd like independent verification that the partitioner is > usable. Does anyone have any experience (good or bad) with the tool? > > Robert Hamilton Hi Robert, some time ago, I tried the same thing... we wanted to have a prototype of our ASIC using 5 Altera 10K50. I think I was using Max+PLUS II V7.2 and 8.0, and in my opinion the partitioner inside these versions suc.. ehrrm, isn't very good. My problem: of course we had to design our PCBs for the 10K50's before we had the design ready, so the connections between the chips were fixed. I tried to find a way to tell the partitioner "these are the chips, these are the connections, go and do your job" - but I (as well as Altera support) couldn't find a way save one: to build the connec- tions between the chips with the graphic editor and to assign internal signals to the I/O-pins - and that's manual partitioning, no need for a partitioner any more. I don't know if the partitioner of the current version was improved, but I don't think so: the trend is to use huge FPGAs if necessary. And don't forget the penalty for leaving chip #1 and entering chip #2: unless you have a very moderate clock rate, you won't be able to have any logic on this line. Well, I wish you luck for your prototype - better luck than we had: we had to rework our VHDL, and to do manual partitioning, but finally we had it up and running (must have been 1-2 years ago). Just my 2c ... Georg -- All opinions expressed are mine, not my employers'. ###### # # # # ### Georg Diebel # # ## ## # # # Institute for Integrated Circuits # # # # # # # ## Technical University of Munich # # # # # # # g_diebel@lis.e-technik.tu-muenchen.de # #### # #### # ### Phone 0049-89-289-28578Article: 10498
Thomas Womack wrote:
>
> In article <35686FEA.6266@hda.hydro.com> you wrote:
>
> >I wrote
>
> : > I was more impressed by 60fps interactive 800x600 Life - which is
> : > non-trivial, and probably not even possible, on Standard Commercial
> : > Hardware (OK, you can use cell lists rather than an array, but the
> : > FPGA approach ran at constant speed independent of population). I
> : > think the 64k of SSRAM attached to the FPGA helped.
>
> : Mike Abrash used Conway's Game of Life as the target for his second
> : 'Annual Code Optimization Challenge', a few years ago.
>
> : The target machine was either a 486 or very early Pentium, i.e. current
> : hardware is quite a bit faster:
>
> : The two joint winners both achieved twice the performance of my entry,
> : which is still capable of 400 fps in 320x200 resolution on a Pentium
> : MMX.
>
> That seems very interesting; would it be worth putting you in touch with
> the appropriate bit of the Hardware Compilation Group?
Sure, no problem.
> Have you a better reference for this than chapters 17 and 18 of the
> Big Black Book from Abrash? He discusses Stafford's solution in detail,
> ignoring Peter Klerings' one altogether, which seems a pity since Klerings'
> one sounds much closer suited to the FPGA.
Klering's code was actually fairly straightforward, except for a set of
flags used to detect static areas.
Skipping that part would still (most probably) let it run at the
required 60 fps, the code is 'just' a parallel implementation of the
counting logic:
Alive next iteration = (alive now AND (count == 2 OR count == 3)) OR
(not alive AND count == 3),
which simplifies to just:
Alive next iteration = (count == 3) OR (alive AND count == 2).
By including the cell itself in the count, then it becomes easier to
reuse the counting logic for multiple rows:
alive = (iCount == 3) OR (alive AND iCount == 4)
You need 4 bits to count to 8 (or 9), so 4 registers for counting plus
one for the center cells leaves one or two registers for array
addressing on an x86.
Klering did a lot of work to simplify the logic as much as possible,
i.e. he didn't actually implement the full 'count-to-9' bitwise logic,
since it is possible to early-out many of the branches.
Implementing the same logic with MMX-style wide registers should make it
approximately twice as fast.
Terje
--
- <Terje.Mathisen@hda.hydro.com>
Using self-discipline, see http://www.eiffel.com/discipline
"almost all programming can be viewed as an exercise in caching"
Article: 10499
Hi All,
I encountered unexpected difficulty, when loading XILINX XC4005E
configuration from ATMEL AT89C52 (in serial slave mode).
I connected P1.5 pin to configuration clock CCLK pin of XILINX chip,
and connected P1.0 pin to DIN pin of XILINX chip.
XILINX configuration is loaded, but not with 100% probability -
sometimes (1 attempt of 5) it fails.
It looks like the problem is with 8051 signals rise time.
When I fed CCLK through 74HC14, everything works fine.
Maybe, somebody knows more about this problem.
How to avoid it?
Thanks,
Alex Sherstuk
Sherstuk@amsd.com
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