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I've worked with Xilinx over the last 5 years and in more than a few instances have seen cases of Xilinx 3K devices (Prom loaded, Master serial) smoke seriously on boot. I suspect a possible cause could be a misloaded serial bitstream, enabling all the tbuffs? Anybody else see this kind of behavior? The end result on a qfp package is a cracked case or crater in the molten plastic... Thanks, Kevin SteeleArticle: 9751
Hi, We're looking for SRAM based FPGA up to 8k gates...and of corse with low cost devices...what about Xilinx XC3000A serie or ATMEL xxx We also need VHDL synthesis. Any tips ? François. -- ------------------------------------------------------------- THIEBOLT Francois \ You think your computer run too slow ? UPS Toulouse III \ - Check nobody's asked for tea ! thiebolt@irit.fr \ "The Hitchikers Guide to the Galaxy" D.Adams -------------------------------------------------------------Article: 9752
Hello,
I wish to save the current status of a running desing on a XC6216 PCI Card,
so that I could restart it in the same state later.
This should be possible, but I couldn't get it to work.
Has somebody ever done this and could help me ?
Thanks,
Thorsten Kukuk
--
Thorsten Kukuk kukuk@vt.uni-paderborn.de
http://www-vt.uni-paderborn.de/~kukuk/
Linux is like a Vorlon. It is incredibly powerful, gives terse,
cryptic answers and has a lot of things going on in the background.
Article: 9753In article <3525ff61.85036355@news.netcomuk.co.uk>, Peter <z80@ds2.com> wrote: >versions. APR often could not fill more than about 60% of a 3064. This was not my experience, but that may be a factor of the types of designs you are doing. With my heavy use of serial ports, and NO busses of any kinds, we frequently used (and still do) APR to get 100% routing. I have several designs filling a 3042, and some very full ones, including 484/484 in a 3195. They take a while to place and route, and sometimes one has to cajole it, but it works, and I have a rather high opinion of APR - for those types of applications. Horses for courses... Arnim. -- Arnim Littek arnim@actrix.gen.nz Actrix Networks Ltd. fax +64-4-801-5335 uucp/PPP/SLIP/BBS accounts tel +64-4-801-5225Article: 9754
Xilinx have some pretty neat tools now (M1.3/ M1.4). I would suggest that you look at designing with their 4k family as this is more mature and has better routing capabilities. The VHDL Synthesis works very well and I am very impressed with their State Machine entry stuff. I can't comment on the Atmel stuff as I've not used them. ------------- Gareth Baron THIEBOLT Francois wrote: > Hi, > > We're looking for SRAM based FPGA up to 8k gates...and of corse > with low cost devices...what about Xilinx XC3000A serie or ATMEL xxx > We also need VHDL synthesis. > > Any tips ? > > François. > > -- > ------------------------------------------------------------- > THIEBOLT Francois \ You think your computer run too slow ? > UPS Toulouse III \ - Check nobody's asked for tea ! > thiebolt@irit.fr \ "The Hitchikers Guide to the Galaxy" D.Adams > -------------------------------------------------------------Article: 9755
In article <6g21od$j6i$1@newacme.west.net>, Kevin Steele <ksteele@silcom.com> writes >I've worked with Xilinx over the last 5 years and in more than a few >instances have seen cases of Xilinx 3K devices (Prom loaded, Master serial) >smoke seriously on boot. > >I suspect a possible cause could be a misloaded serial bitstream, enabling >all the tbuffs? > >Anybody else see this kind of behavior? The end result on a qfp package is a >cracked case or crater in the molten plastic... This sounds like "latchup". It used to be quite common with the older CMOS devices - the device behaves like an SCR, takes *lots* of current and self-destructs unless the power is switched off in time. Leon -- Leon Heller: leon@lfheller.demon.co.uk http://www.lfheller.demon.co.uk Amateur Radio Callsign G1HSM Tel: +44 (0) 118 947 1424 See http://www.lfheller.demon.co.uk/dds.htm for details of my AD9850 DDS system. See " "/diy_dsp.htm for a simple DIY DSP ADSP-2104 system.Article: 9756
THIEBOLT Francois wrote: > We're looking for SRAM based FPGA up to 8k gates...and of corse > with low cost devices...what about Xilinx XC3000A serie or ATMEL xxx > We also need VHDL synthesis. > > Any tips ? For 5-V designs, I recommend XC4000E and its lower-cost brothers in the Spartan series. And for 3.3 V, use XC4000XL and -starting this summer- its lower-cost Spartan XL brothers. On-chip RAM, better arithmetic, faster speed and more powerful software, as well as lower cost seems to be good set of arguments. Peter Alfke, Xilinx ApplicationsArticle: 9757
There are good reasons why a dongle is a better alternative. I have 5 ISA cards in my system which MUST be there for me to do my job. I have 2 PCI cards with a third slot reserved for a Fibre Channel interface to support a new product coming up. I do not have a place for a network card. It took me months to find a reliable motherboard with 5 ISA slots. In article <rggowSADk+I1MAqU@fpga.demon.co.uk>, David Pashley <david@fpga.demon.co.uk> wrote: > > In article <01bd5e54$fa2aba90$2df65ecf@drt3>, Austin Franklin > <d9arkroom@ix.netcom.com> writes > > > > > >The (greedy) EDA companies marketing have this perception that the hardware > >key actually does some good. If these gumps got a clue, they would use > >address node locks (hard coded usually in a ROM, or in the actual Ethernet > >controller chip), like Unix software does. So what if a PC doesn't have a > >NIC (network interface card) in it, just give them one (they only cost > >$10...that is LESS than the price of a hardware key from the (greedy) > >hardware key vendors!). > > I agree. However, it's not greed that delays the implementation of IP > address locking so much as the need for someone to provide > (commercially) such a scheme. When the dongle-free FlexLM floating > licence scheme became available on PC last year, forward thinking EDA > vendors like Viewlogic and Chronology implemented it. > > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 9758
SENIOR SOFTWARE ENGINEER POSITION Ricoh Silicon Valley is engaged in an innovative image computing project involving FPGAs. We have need for a Senior Software Engineer to join a small team of hardware and algorithm specialists in research in novel FPGA-based reconfigurable computing. The complete job description of duties and responsibilities can be viewed at our Web site at: http://www.crc.ricoh.com/jobs/ssejob.html To apply, please fax resumes to 650-854-8740, Attn: HR dept., or send e-mail to jobs@crc.ricoh.com. We will attend FCCM'98 in Napa Valley, CA April 15-17, and would be happy to meet applicants at that time. The California Research Center of Ricoh Silicon Valley, Inc. is a small lab focusing on information technologies for future office automation environments, such as image compression, uses of the world wide web and document technologies. The lab is very close to Stanford University and in easy driving distance to San Francisco, San Jose, and Santa Cruz, and many Bay Area natural and cultural attractions. Ricoh Silicon Valley is an equal opportunity employer and encourages qualified women and minorities to apply. Applications must already be qualified to work in the USA. Further information is available at: http://www.crc.ricoh.com.Article: 9759
Yes, APR did well on smaller devices. As they got bigger, it had more problems. On one 3090 design I did, it could not get past 60% and I had to purchase XACT6. Admittedly there was a lot of random logic there, and some buses. BTW, on your 3195 you had to be using PPR, not APR, because IIRC APR never supported the 31xx devices. Peter. Return address is invalid to help stop junk mail. E-mail replies to zX80@digiYserve.com but remove the X and the Y.Article: 9760
This subject comes up from time to time, much to Xilinx's annoyance.
Yes, it is easy to get a 3k device to misconfigure, with internal
shorts all over the place, and run quite hot. I have done it myself a
few times.
The problem is usually caused by noise on the serial data stream. The
devices are very fast, so the noise can be extremely fast, fast enough
to not show on my Tektronix 350MHz analog scope. OTOH one cannot slow
down the CCLK signal too much because its rise/fall times must not
exceed about 20ns. So it is a game, keeping the transitions
substantially faster than 20ns, but avoiding ground bounce etc.
The reason, IMHO, why 90+% of X3k users don't have a problem (as
Xilinx will be quick to point out) is that most FPGA applications use
only 1 or maybe 2 devices, so the config signals don't have to travel
far.
But when you do a design with e.g. 30 devices on a PCB (as I have done
a few times) then you have to pay very close attention indeed to clock
distribution, termination, etc, otherwise you can guarantee problems.
And one cannot just locally buffer the clock with e.g. HC buffers
because their transition time is just a bit too slow.
I recall a case where I had a 200pF variable cap between CCLK and GND,
and by twiddling it I could make the 32 devices load fine, or not, or
just some of them. And all the time I was doing this, the scope did
not show any abnormality which I would have *expected* to exceed logic
levels.
I cannot see why Xilinx did not put a simple crude Schmitt trigger on
their CCLK input - that alone would have easily solved most problems I
have seen.
The other problem is with non-monotonic Vcc rise. The data book says
it EITHER must be monotonic OR (if not) you must wait until Vcc is
stabilised (with RST HIGH) and *then* apply the reset pulse, RST LOW,
and *then* return RST to HIGH. I now do this as standard on every
board I do:
_____________
VCC _____/
/RST __________ ______
|___|
>I've worked with Xilinx over the last 5 years and in more than a few
>instances have seen cases of Xilinx 3K devices (Prom loaded, Master serial)
>smoke seriously on boot.
>
>I suspect a possible cause could be a misloaded serial bitstream, enabling
>all the tbuffs?
>
>Anybody else see this kind of behavior? The end result on a qfp package is a
>cracked case or crater in the molten plastic...
Peter.
Return address is invalid to help stop junk mail.
E-mail replies to zX80@digiYserve.com but
remove the X and the Y.
Article: 9761In article <3524936A.4744@irit.fr>, thiebolt@irit.fr wrote: > > Hi, > > We're looking for SRAM based FPGA up to 8k gates...and of corse > with low cost devices...what about Xilinx XC3000A serie or ATMEL xxx > We also need VHDL synthesis. SRAM FPGA devices with FreeRAM(tm) to 8K gates and beyond, free FPGA software including free FPGA synthesis tools (VHDL or Verilog) - limited time offer a $995 value...check out... http://www.atmel.com/fpga_software1.html Martin Mason Atmel Corp. > > Any tips ? > > François. > > -- > ------------------------------------------------------------- > THIEBOLT Francois \ You think your computer run too slow ? > UPS Toulouse III \ - Check nobody's asked for tea ! > thiebolt@irit.fr \ "The Hitchikers Guide to the Galaxy" D.Adams > ------------------------------------------------------------- > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 9762
THIEBOLT Francois <thiebolt@irit.fr> wrote in article <3524936A.4744@irit.fr>... > Hi, > > We're looking for SRAM based FPGA up to 8k gates...and of corse > with low cost devices...what about Xilinx XC3000A serie or ATMEL xxx > We also need VHDL synthesis. > > Any tips ? What will your max frequency be? Austin Franklin darkroom@ix.netcom.comArticle: 9763
Only better for you (and may be two other people on earth), which, would be about .00001% of the Viewlogic user population. You can always use another PC to either have your ISA slots or to run Viewlogic on, as they are really cheap comparatively (your salary, the price of the tools, etc.). So, you are saying 99.99% of us should suffer because you HAVE to use a machie stuffed with ISA cards? That's kinda funny. Austin Franklin darkroom@ix.netcom.com staylor@dspsystems.com wrote in article <6g3bn5$dh0$1@nnrp1.dejanews.com>... > There are good reasons why a dongle is a better alternative. I have 5 ISA > cards in my system which MUST be there for me to do my job. I have 2 PCI cards > with a third slot reserved for a Fibre Channel interface to support a new > product coming up. I do not have a place for a network card. It took me > months to find a reliable motherboard with 5 ISA slots. > > In article <rggowSADk+I1MAqU@fpga.demon.co.uk>, > David Pashley <david@fpga.demon.co.uk> wrote: > > > > In article <01bd5e54$fa2aba90$2df65ecf@drt3>, Austin Franklin > > <d9arkroom@ix.netcom.com> writes > > > > > > > > >The (greedy) EDA companies marketing have this perception that the hardware > > >key actually does some good. If these gumps got a clue, they would use > > >address node locks (hard coded usually in a ROM, or in the actual Ethernet > > >controller chip), like Unix software does. So what if a PC doesn't have a > > >NIC (network interface card) in it, just give them one (they only cost > > >$10...that is LESS than the price of a hardware key from the (greedy) > > >hardware key vendors!). > > > > I agree. However, it's not greed that delays the implementation of IP > > address locking so much as the need for someone to provide > > (commercially) such a scheme. When the dongle-free FlexLM floating > > licence scheme became available on PC last year, forward thinking EDA > > vendors like Viewlogic and Chronology implemented it. > > > > > > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- > http://www.dejanews.com/ Now offering spam-free web-based newsreading >Article: 9764
Howdy...
I have a design which generates a divided clock internally.
I had a few problems with this until I brought the clock out to
an external pin. The problems disappeared. (the routing of this
signal to the outside is all that changed in the HDL). I checked
the two designs using EPIC and found that the good design had
delays of < 10ns on that signal. The bad design had delays of
up to 17ns which are causing the trouble. The bad design routes
the signal all over the chip and doesn't really need to.
My question is, how can I setup the xilinx tools to optimize
this sort of thing. I can set constraints in Leonardo (my HDL
software), but they only optimize for logic. Likewise, I can
setup optimization in Xilinx's "map" program to optimize for
speed, but that only does logic. How can I make the Xilinx tools
realize they can route this thing better?
Cheers,
Jake
--
janovetz@uiuc.edu | Once you have flown, you will walk the earth with
University of Illinois | your eyes turned skyward, for there you have been,
| there you long to return. -- da Vinci
PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.html
Article: 9765In article <35225DB5.85BD5EDC@spoke.ece.utexas.edu> Zhiping <zpyao@spoke.ece.utexas.edu> writes: >I think your answer is good, but I have one more question: in the present >Dual port, one LUT's write address and read address are the same , the >other LUT's write address is the same as the first, but the read address >is dual port address, I think some time just make the two LUTs' write and >read address both seperated, that means, both the write address are the >same and both the read address are the same, this scheme can double the >RAM capacity, why not? Yes, you are right. The side effect of this would be 4 address busses ( for an example such as the XC4000E, 4 bits per address bus), that would need to have reasonable connectivity to the routing channels. This is twice as many CLB inputs as the LUTs currently have, and would primarilly only help for the dual port case, unless other logic was added to make alternative use of these signals. As I indicated in my previous message on this thread, the resources (in silicon) to implement CLB inputs is significant, and there were probably other (non-architectural) constraints on the design of the XC4000E. For a new architecture (and its new place and route software), these tradeoffs could be re-evaluated. While a clean slate is a fun place to define your next perfect architecture, the market forces surrounding a prior successful architecture often create annoying constraints. Try and imaging what it must be like as the architect of the 80186, 80286, 80386, 80486, Pentium(tm), PentiumPro(tm), Pentium-II(tm), all the while having to support such trully horrible things like the 8086 condition codes, the cascadeable prefix codes, and a memory "segmentation" scheme that couldn't have had more than 2 grams of thought put into it. Has to run flight simulator too :-) Philip Freidin.Article: 9766
I use removable hard drives for a similar purpose. Cheaper than a new computer. "Austin Franklin" <darkroo8m@ix.netcom.com> wrote: >Only better for you (and may be two other people on earth), which, would be >about .00001% of the Viewlogic user population. You can always use another >PC to either have your ISA slots or to run Viewlogic on, as they are really >cheap comparatively (your salary, the price of the tools, etc.). > >So, you are saying 99.99% of us should suffer because you HAVE to use a >machie stuffed with ISA cards? That's kinda funny. > >Austin Franklin >darkroom@ix.netcom.com > > >staylor@dspsystems.com wrote in article ><6g3bn5$dh0$1@nnrp1.dejanews.com>... >> There are good reasons why a dongle is a better alternative. I have 5 ISA >> cards in my system which MUST be there for me to do my job. I have 2 PCI >cards >> with a third slot reserved for a Fibre Channel interface to support a new >> product coming up. I do not have a place for a network card. It took me >> months to find a reliable motherboard with 5 ISA slots. >> >> In article <rggowSADk+I1MAqU@fpga.demon.co.uk>, >> David Pashley <david@fpga.demon.co.uk> wrote: >> > >> > In article <01bd5e54$fa2aba90$2df65ecf@drt3>, Austin Franklin >> > <d9arkroom@ix.netcom.com> writes >> > > >> > > >> > >The (greedy) EDA companies marketing have this perception that the >hardware >> > >key actually does some good. If these gumps got a clue, they would >use >> > >address node locks (hard coded usually in a ROM, or in the actual >Ethernet >> > >controller chip), like Unix software does. So what if a PC doesn't >have a >> > >NIC (network interface card) in it, just give them one (they only cost >> > >$10...that is LESS than the price of a hardware key from the (greedy) >> > >hardware key vendors!). >> > >> > I agree. However, it's not greed that delays the implementation of IP >> > address locking so much as the need for someone to provide >> > (commercially) such a scheme. When the dongle-free FlexLM floating >> > licence scheme became available on PC last year, forward thinking EDA >> > vendors like Viewlogic and Chronology implemented it. >> > >> > > >> >> -----== Posted via Deja News, The Leader in Internet Discussion ==----- >> http://www.dejanews.com/ Now offering spam-free web-based newsreading >> Opinions expressed herein are solely my own and may or may not reflect my opinion at this particular time or any other.Article: 9767
Xilinx supports a FROM : sync_point : TO : sync_point : max_time; constraint form that the tools will use to route the part. Thje constraints are entered into a text file called design_name.UCF, where design name is the name of the project. Check Xilinx web, "Constraints Expert Journal" for a nice tutorial on constraints. Constraints are also documented in Chap 12 of the Libraries guide. Nick "Faster chips exist for better video games" Jacob W Janovetz wrote: > Howdy... > > I have a design which generates a divided clock internally. > I had a few problems with this until I brought the clock out to > an external pin. The problems disappeared. (the routing of this > signal to the outside is all that changed in the HDL). I checked > the two designs using EPIC and found that the good design had > delays of < 10ns on that signal. The bad design had delays of > up to 17ns which are causing the trouble. The bad design routes > the signal all over the chip and doesn't really need to. > > My question is, how can I setup the xilinx tools to optimize > this sort of thing. I can set constraints in Leonardo (my HDL > software), but they only optimize for logic. Likewise, I can > setup optimization in Xilinx's "map" program to optimize for > speed, but that only does logic. How can I make the Xilinx tools > realize they can route this thing better? > > Cheers, > Jake > > -- > janovetz@uiuc.edu | Once you have flown, you will walk the earth with > University of Illinois | your eyes turned skyward, for there you have been, > | there you long to return. -- da Vinci > PP-ASEL | http://www.ews.uiuc.edu/~janovetz/index.htmlArticle: 9768
Maybe I am confused. You write that Spartan needs a config prom with clock generation on board. What do you mean? Surely you can't be saying that Spartan does not have an onboard clock for configuration purposes? Because if that is what you are saying I suggest you look at the data sheet where an onboard clock for configuation is specified. Have FUN!! Nick WTorger wrote: > First off, one time programmables can stay 1 technology generation behind and > still compete with the SRAM or Flash based solutions. The 32000 is a .6um > technology and your comparing against a .5um 10k40. > Second, from a performance perspective the SRAM based device cannot compete > with an anti-fuse. It's much slower. Additionally a anti-fuse based part can > use >95% of the logic and still route. This keeps a designer from buying more > gates than he really needs. > Third, Actel introducted a new product line last October that competes very > well with the 6K and the Spartan. The problem with the 6K family is that only > one member exists today. With Spartan, if you need a config prom, then you What?????? > have to buy the expensive version with clock generation on board. Add the > larger density, plus config prom, and Actel has a very attractive solution. > And it's only one chip. > Above and beyond that, we have a product called Silicon Explorer. This gives > you the capability of looking at any two nets internally in real time. If > those we not the nets causing the problem, within 5 seconds you can look at any > other two nets in real time. This is like cutting off the top of the case, and > being able to probe around the chip with a scope. There is no way this is not > a cool feature to any deigner whose had to wait for a place and route to > complete where he could look at nets he thinks are causing problems. Hope you > choose the correct nets, or have plenty of pins. > > Yes, from a density point of view, we don't (today) have large (> 36K gates) > density parts. > There are many reasons to use Actel for a design. > They are: > 1) Speed. If you need high performance, we can do it. > 2) Low power. Anti-fuses are passive components that disipate little power. > 3) Tight integration. The only single chip solution to compete with Altera and > Xilinx. > > Many, many more. > > Will Torgerson > Actel CorporationArticle: 9769
Why is having to have a network card, a special one more than likely, any better than having a dongle? Either way you have to add something to your system that will more than likely cause you a problem at some point. What do you do when Win98 changes and the card is no longer compatible? Give up your EDA software or don't upgrade the OS? A dongle that fits on a parallel port is platform independent. To each their own. I have been told many times I could network and use two or more computers to accomplish the same goal while being told how much more productive it would make me. I say that is slower and no where near as useful or productive. I point out that the other engineers do just that [network]. I then point out that I typically use 3-5 year old schematic capture and PCB layout tools running under Win31 on a system 1-2 generations old and turn out 2-3 times more finished deliverable products, typically with fewer errors, probably because I am not always having to learn new tools, than any other engineer I have ever worked with (15 years). The modern way is not always better. I do use the latest version of Maxplus2 though V8.2 is the last version to run under Win31, so that may change. In article <01bd5f49$90d63290$2df65ecf@drt3>, "Austin Franklin" <darkroo8m@ix.netcom.com> wrote: > > Only better for you (and may be two other people on earth), which, would be > about .00001% of the Viewlogic user population. You can always use another > PC to either have your ISA slots or to run Viewlogic on, as they are really > cheap comparatively (your salary, the price of the tools, etc.). > > So, you are saying 99.99% of us should suffer because you HAVE to use a > machie stuffed with ISA cards? That's kinda funny. > > Austin Franklin > darkroom@ix.netcom.com > > staylor@dspsystems.com wrote in article > <6g3bn5$dh0$1@nnrp1.dejanews.com>... > > There are good reasons why a dongle is a better alternative. I have 5 ISA > > cards in my system which MUST be there for me to do my job. I have 2 PCI > cards > > with a third slot reserved for a Fibre Channel interface to support a new > > product coming up. I do not have a place for a network card. It took me > > months to find a reliable motherboard with 5 ISA slots. > > -----== Posted via Deja News, The Leader in Internet Discussion ==----- http://www.dejanews.com/ Now offering spam-free web-based newsreadingArticle: 9770
In article <6g4kma$sin$1@nnrp1.dejanews.com>, staylor@dspsystems.com wrote: >Why is having to have a network card, a special one more than likely, any >better than having a dongle? Either way you have to add something to your >system that will more than likely cause you a problem at some point. What do >you do when Win98 changes and the card is no longer compatible? Give up your >EDA software or don't upgrade the OS? A dongle that fits on a parallel port is >platform independent. The point is that *none* of these should be necessary. Software licencing systems like nls or flexlm are working well nowadays, and are no more and no less difficult to crack than hardware dongles. These also allows for interesting things like site licenses. Hardware dongles are a thing of the past, and a terrible pain for the users who paid for the software. The most humorous is that pirated versions, being dongle-free, are probably much more usable. EDA software vendors will either see the light, or die. OG.Article: 9771
> I have a design which generates a divided clock internally. > I had a few problems with this until I brought the clock out to > an external pin. The problems disappeared. (the routing of this > signal to the outside is all that changed in the HDL). I checked > the two designs using EPIC and found that the good design had > delays of < 10ns on that signal. The bad design had delays of > up to 17ns which are causing the trouble. The bad design routes > the signal all over the chip and doesn't really need to. > > My question is, how can I setup the xilinx tools to optimize > this sort of thing. I can set constraints in Leonardo (my HDL > software), but they only optimize for logic. Likewise, I can > setup optimization in Xilinx's "map" program to optimize for > speed, but that only does logic. How can I make the Xilinx tools > realize they can route this thing better? Use a TIMESPEC file...or some HDLs may allow you to specify the timing constraints in the signal declaration...and if the tool(s) are any good, will continue that information thoughout the tool process. TIMESPEC is easy, no fuss, no muss.Article: 9772
In article +ADw-6g21od+ACQ-j6i+ACQ-1+AEA-newacme.west.net+AD4-, Kevin Steele +ADw-ksteele+AEA-silcom.com+AD4- writes +AD4-I've worked with Xilinx over the last 5 years and in more than a few +AD4-instances have seen cases of Xilinx 3K devices (Prom loaded, Master serial) +AD4-smoke seriously on boot. I've had latchup problems with the 3K series when the VCC rail was -0.3V prior to turnon of the VCC supply. It also occurred on a testbed with all I/O pins floating. The experiment was very repeatable. The small negative voltage was cause by leakage from an RS232 interface. The voltage did not cause any measureable current through the FPGA but it seemed to 'precharge' something inside the chip (substrate?). When the voltage was present for only a second, no latchup. With the voltage present for a minute, guaranteed latchup. A schottky diode across the supply (VCC became -0.2V) did not work. A 47 Ohm resistor did... I notified Xilinx on this problem some years ago, maybe they put it in an app note. Arie de MuynckArticle: 9773
> Why is having to have a network card, a special one more than likely, any > better than having a dongle? The network card does NOT have to be 'special'. > Either way you have to add something to your > system that will more than likely cause you a problem at some point. What do > you do when Win98 changes and the card is no longer compatible? Why would you think this? Network cards are much less trouble than parallel ports. Anyway, MOST PC who do CAE have a network card already. I believe NOT having a network card is the exception... > A dongle that fits on a parallel port is > platform independent. Again, more people have had problems with parallel ports.... > To each their own. I have been told many times I could network and use two or > more computers to accomplish the same goal while being told how much more > productive it would make me. I say that is slower and no where near as useful > or productive. I point out that the other engineers do just that [network]. I > then point out that I typically use 3-5 year old schematic capture and PCB > layout tools running under Win31 on a system 1-2 generations old and turn out > 2-3 times more finished deliverable products, typically with fewer errors, > probably because I am not always having to learn new tools, than any other > engineer I have ever worked with (15 years). The modern way is not always > better. I do use the latest version of Maxplus2 though V8.2 is the last > version to run under Win31, so that may change. I doubt you are 2-3 times more productive, and that you could even be near as productive using Windows 3.1, considering how unstable it is. I find your logic 'interesting' to say the least...so as you say, to each his own. Anyway, in Xilinx land (which is what we were talking about) the old tools do not support the new parts, so if all you use is old parts, then lucky you! Also, the Viewlogic tools (somehow I don't think you would use them...) don't require much of a learning curve from revision to revision, and have been pretty consistent even during the DOS to Windows transition. Some changes, yes, but the tools are just not that complicated that it should take you more than a few days or so to be productive with them. AustinArticle: 9774
Isabelle Gonthier wrote: > sylvain dery wrote: > > > > Hi all! > > > > I have to design a Reed-Solomon encoder in VHDL for > > a graduate university project. The semester is ending soon and > > I think I took a bigger bite than I can chew! > > So I'm looking for practical implementation of the Reed-Solomon > > algorithm. > > > > Can anyone give me a hint? > > > > Thanks in advance! > > SLY > I have seen in the Xilinx Cores Solutions databook that there is a 3rd > party that has developed a Reed-Soloman encoder. You might want to > check that out. Yes but Sylvain is a student. I doubt he can afford a soft core for $100k (or is it free?). Sam Falaki
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