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Threads Starting Jul 2007
121302: 07/07/01: <darrick>: Question about xilinx programmer
121303: 07/07/01: Matthew Hicks: Re: Question about xilinx programmer
121305: 07/07/02: <darrick>: Re: Question about xilinx programmer
121308: 07/07/02: Alex Gibson: s3a kit - Use sma as signal output ?
121324: 07/07/02: Eric Crabill: Re: s3a kit - Use sma as signal output ?
121326: 07/07/02: austin: Re: s3a kit - Use sma as signal output ?
121506: 07/07/06: Alex Gibson: Re: s3a kit - Use sma as signal output ?
121309: 07/07/02: LilacSkin: 32bit multiplication in a PowerPC405 of a VirtexIIPro
121310: 07/07/02: Sylvain Munaut: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
121311: 07/07/02: John McCaskill: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
121313: 07/07/02: Sylvain Munaut: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
121330: 07/07/02: Peter Ryser: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
121314: 07/07/02: John McCaskill: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
121329: 07/07/02: Peter Ryser: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
121341: 07/07/02: Ben Jackson: Re: 32bit multiplication in a PowerPC405 of a VirtexIIPro
121315: 07/07/02: <pbFJKD@ludd.invalid>: Xilinx ISE + Multi CPU setup?
121317: 07/07/02: <pbFJKD@ludd.invalid>: Re: Xilinx ISE + Multi CPU setup?
121334: 07/07/03: Matthieu: Re: Xilinx ISE + Multi CPU setup?
121348: 07/07/03: Martin Thompson: Re: Xilinx ISE + Multi CPU setup?
121351: 07/07/03: <pbFJKD@ludd.invalid>: Re: Xilinx ISE + Multi CPU setup?
121376: 07/07/03: Martin Thompson: Re: Xilinx ISE + Multi CPU setup?
121316: 07/07/02: <darrick>: About the parallel port jtag programmer,
121318: 07/07/02: <cs_posting@hotmail.com>: Re: About the parallel port jtag programmer,
121328: 07/07/02: jjlindula@hotmail.com: Choosing the EPC16 or the EPCS64 for Stratix II
121342: 07/07/02: Ben Jackson: Re: Choosing the EPC16 or the EPCS64 for Stratix II
121449: 07/07/04: Rob: Re: Choosing the EPC16 or the EPCS64 for Stratix II
121542: 07/07/06: <sfielding@base2designs.com>: Re: Choosing the EPC16 or the EPCS64 for Stratix II
121544: 07/07/07: vasile: Re: Choosing the EPC16 or the EPCS64 for Stratix II
121567: 07/07/08: <sfielding@base2designs.com>: Re: Choosing the EPC16 or the EPCS64 for Stratix II
121582: 07/07/09: vasile: Re: Choosing the EPC16 or the EPCS64 for Stratix II
121604: 07/07/09: <sfielding@base2designs.com>: Re: Choosing the EPC16 or the EPCS64 for Stratix II
121331: 07/07/02: Eddie H: Can I use chipscoe to look at V5 GTPoutputs
121333: 07/07/02: motty: Re: Can I use chipscoe to look at V5 GTPoutputs
121336: 07/07/02: austin: Re: Can I use chipscoe to look at V5 GTPoutputs
121338: 07/07/02: ram: cosimulation
121383: 07/07/03: Mike Treseler: Re: cosimulation
121340: 07/07/02: AugustoEinsfeldt: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121343: 07/07/03: Jim Granville: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121347: 07/07/03: Jim Granville: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121352: 07/07/03: <pbFJKD@ludd.invalid>: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121344: 07/07/02: Peter Alfke: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121350: 07/07/03: Uwe Bonnes: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121354: 07/07/03: Jim Granville: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121356: 07/07/03: Uwe Bonnes: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121421: 07/07/04: Jim Granville: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121353: 07/07/03: <pbFJKD@ludd.invalid>: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121362: 07/07/03: comp.arch.fpga: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121364: 07/07/03: AugustoEinsfeldt: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121369: 07/07/03: <cs_posting@hotmail.com>: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121372: 07/07/03: comp.arch.fpga: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121382: 07/07/03: AugustoEinsfeldt: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121426: 07/07/03: AugustoEinsfeldt: Re: high voltage input on SPARTAN-3 FPGAs: MTBF reduction?
121349: 07/07/03: Francesco: Xilinx PCI Express solutions
121355: 07/07/03: John Adair: Re: Xilinx PCI Express solutions
121357: 07/07/03: <darrick>: question about xilinx jtag
121360: 07/07/03: <darrick>: Re: question about xilinx jtag
121361: 07/07/03: <hofmann.juergen@pc-future.de>: Microblaze and software interrupts?
121365: 07/07/03: Zara: Re: Microblaze and software interrupts?
121585: 07/07/09: Göran Bilski: Re: Microblaze and software interrupts?
121919: 07/07/15: Andreas Hofmann: Re: Microblaze and software interrupts?
121367: 07/07/03: morphiend: Re: Microblaze and software interrupts?
121368: 07/07/03: Hofjue: Re: Microblaze and software interrupts?
121465: 07/07/05: Hofjue: Re: Microblaze and software interrupts?
121787: 07/07/13: Hofjue: Re: Microblaze and software interrupts?
121994: 07/07/16: Hofjue: Re: Microblaze and software interrupts?
121363: 07/07/03: Jon Beniston: Metastability in very slow clock domains
121366: 07/07/03: Symon: Re: Metastability in very slow clock domains
121370: 07/07/03: Mike Treseler: Re: Metastability in very slow clock domains
121371: 07/07/03: John_H: Re: Metastability in very slow clock domains
121373: 07/07/03: Jon Beniston: Re: Metastability in very slow clock domains
121374: 07/07/03: Jon Beniston: Re: Metastability in very slow clock domains
121375: 07/07/03: Jon Beniston: Re: Metastability in very slow clock domains
121378: 07/07/03: motty: DIFF_TERM Question
121379: 07/07/03: motty: Re: DIFF_TERM Question
121380: 07/07/03: Bob: Re: DIFF_TERM Question
121413: 07/07/03: motty: Re: DIFF_TERM Question
121381: 07/07/03: <pladow@gmail.com>: Xilinx DCM Reset
121386: 07/07/03: austin: Re: Xilinx DCM Reset
121408: 07/07/03: austin: Re: Xilinx DCM Reset
121418: 07/07/03: austin: Re: Xilinx DCM Reset
121422: 07/07/03: austin: Re: Xilinx DCM Reset
121423: 07/07/03: austin: Re: Xilinx DCM Reset
121485: 07/07/05: austin: Re: Xilinx DCM Reset
121400: 07/07/03: PlayDough: Re: Xilinx DCM Reset
121416: 07/07/03: PlayDough: Re: Xilinx DCM Reset
121420: 07/07/03: PlayDough: Re: Xilinx DCM Reset
121484: 07/07/05: PlayDough: Re: Xilinx DCM Reset
121385: 07/07/03: <anandraj7k@gmail.com>: MPC 8321E DDR2 interface
121388: 07/07/03: John_H: Re: MPC 8321E DDR2 interface
121390: 07/07/03: Alan Nishioka: Spartan-3e JTAG no device id
121391: 07/07/03: Antti: Re: Spartan-3e JTAG no device id
121398: 07/07/03: austin: Re: Spartan-3e JTAG no device id
121399: 07/07/03: austin: Re: Spartan-3e JTAG no device id
121409: 07/07/03: austin: Re: Spartan-3e JTAG no device id
121406: 07/07/03: Tim (one of many): Re: Spartan-3e JTAG no device id
121410: 07/07/03: austin: Re: Spartan-3e JTAG no device id
121411: 07/07/03: austin: Re: Spartan-3e JTAG no device id
121417: 07/07/03: austin: Re: Spartan-3e JTAG no device id
121460: 07/07/04: austin: Re: Spartan-3e JTAG no device id
121414: 07/07/03: Tim (one of many): Re: Spartan-3e JTAG no device id
121396: 07/07/03: Alan Nishioka: Re: Spartan-3e JTAG no device id
121397: 07/07/03: Antti: Re: Spartan-3e JTAG no device id
121404: 07/07/03: Alan Nishioka: Re: Spartan-3e JTAG no device id
121405: 07/07/03: Alan Nishioka: Re: Spartan-3e JTAG no device id
121407: 07/07/03: Alan Nishioka: Re: Spartan-3e JTAG no device id
121425: 07/07/03: Alan Nishioka: Re: Spartan-3e JTAG no device id
121459: 07/07/04: Alan Nishioka: Re: Spartan-3e JTAG no device id
121466: 07/07/05: Antti: Re: Spartan-3e JTAG no device id
121488: 07/07/05: Alan Nishioka: SOLVED: Spartan-3e JTAG no device id
121491: 07/07/05: austin: Re: SOLVED: Spartan-3e JTAG no device id
121507: 07/07/06: Ulrich Bangert: Re: SOLVED: Spartan-3e JTAG no device id
121501: 07/07/05: Antti: Re: SOLVED: Spartan-3e JTAG no device id
121392: 07/07/03: <john.m.oyler@gmail.com>: Hobbyist trying to decide which device to start with...
121394: 07/07/03: MM: Re: Hobbyist trying to decide which device to start with...
121395: 07/07/03: Symon: Re: Hobbyist trying to decide which device to start with...
121402: 07/07/03: <john.m.oyler@gmail.com>: Re: Hobbyist trying to decide which device to start with...
121415: 07/07/03: Peter Alfke: Re: Hobbyist trying to decide which device to start with...
121428: 07/07/04: Mark McDougall: Re: Hobbyist trying to decide which device to start with...
121434: 07/07/03: John Adair: Re: Hobbyist trying to decide which device to start with...
121401: 07/07/03: Pinhas: USB full speed final project proposal
121427: 07/07/03: <prasad.naga@gmail.com>: Unable to use xmd or mb-gdb with microblaze cycle accurate simulator target
121432: 07/07/03: subint: Simulation problem
121444: 07/07/04: John_H: Re: Simulation problem
121476: 07/07/05: John_H: Re: Simulation problem
121471: 07/07/05: subint: Re: Simulation problem
121474: 07/07/05: vssumesh: Re: Simulation problem
121435: 07/07/04: Pablo: Add DMA support to a custom core?
121472: 07/07/05: Guru: Re: Add DMA support to a custom core?
121473: 07/07/05: Pablo: Re: Add DMA support to a custom core?
121581: 07/07/09: Guru: Re: Add DMA support to a custom core?
121584: 07/07/09: Pablo: Re: Add DMA support to a custom core?
121437: 07/07/04: <darrick>: Question about xilinx jtag programmer
121438: 07/07/04: Symon: Re: Question about xilinx jtag programmer
121439: 07/07/04: <darrick>: Re: Question about xilinx jtag programmer
121441: 07/07/04: Sebastian Goller: Rocket IO clocking
121442: 07/07/04: <adam.taylor@selex-sas.com>: Re: Rocket IO clocking
121443: 07/07/04: <adam.taylor@selex-sas.com>: Re: Rocket IO clocking
121446: 07/07/04: John_H: Re: Rocket IO clocking
121450: 07/07/04: austin: Re: Rocket IO clocking
121445: 07/07/04: <darrick>: Unbuffered jtag programmer?
121454: 07/07/04: Uwe Bonnes: Re: Unbuffered jtag programmer?
121447: 07/07/04: Markus Fras: Change PicoBlaze ROM Code on Spartan 3E Development Board
121451: 07/07/04: John_H: Re: Change PicoBlaze ROM Code on Spartan 3E Development Board
121448: 07/07/04: <rajivc53@gmail.com>: read/write in bram block
121457: 07/07/04: Matthew Hicks: Re: read/write in bram block
121458: 07/07/04: hurleybp: Re: read/write in bram block
121452: 07/07/04: Netoko Young: LVDS via Emulation
121453: 07/07/04: Netoko Young: Re: LVDS via Emulation
121455: 07/07/04: Andreas Hofmann: ICAP in V4 FX20 only working after Reset
121461: 07/07/05: stephen.craven@gmail.com: Re: ICAP in V4 FX20 only working after Reset
121467: 07/07/05: Andreas Hofmann: Re: ICAP in V4 FX20 only working after Reset
121482: 07/07/05: austin: Re: ICAP in V4 FX20 only working after Reset
121456: 07/07/04: General Schvantzkoph: Can't get Actel tools to run on SL4.4 (RHEL 4.4)
121462: 07/07/04: water9580@yahoo.com: Xilinx V4/V5 FPGA SATA GTP
121483: 07/07/05: austin: Re: Xilinx V4/V5 FPGA SATA GTP
121512: 07/07/06: water9580@yahoo.com: Re: Xilinx V4/V5 FPGA SATA GTP
121541: 07/07/07: <FPGADebug@gmail.com>: Re: Xilinx V4/V5 FPGA SATA GTP
121463: 07/07/04: Jarod2046@gmail.com: Power PC Reference Design timing failed
121580: 07/07/09: Guru: Re: Power PC Reference Design timing failed
121464: 07/07/05: PretzelX: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121470: 07/07/05: Jon Beniston: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121486: 07/07/05: austin: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121487: 07/07/05: Mike Treseler: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121490: 07/07/05: austin: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121526: 07/07/06: Nico Coesel: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121587: 07/07/09: Göran Bilski: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121601: 07/07/09: Nico Coesel: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121607: 07/07/10: Jim Granville: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121494: 07/07/05: Mike Treseler: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121706: 07/07/12: Jim Granville: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121707: 07/07/11: Mike Treseler: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121749: 07/07/12: Mike Treseler: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121758: 07/07/13: Jim Granville: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121766: 07/07/12: Mike Treseler: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121867: 07/07/14: Jim Granville: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121708: 07/07/12: John_H: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121969: 07/07/16: John_H: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121986: 07/07/16: John_H: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121971: 07/07/16: <steve.lass@xilinx.com>: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121983: 07/07/17: Jim Granville: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121988: 07/07/16: KJ: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121997: 07/07/17: Rainer Buchty: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
122070: 07/07/19: Jim Granville: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121489: 07/07/05: <cs_posting@hotmail.com>: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121495: 07/07/05: <cs_posting@hotmail.com>: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121694: 07/07/11: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121695: 07/07/11: Peter Alfke: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121696: 07/07/11: Jon Beniston: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121699: 07/07/11: <fpga_toys@yahoo.com>: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121702: 07/07/11: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121705: 07/07/11: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121709: 07/07/11: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121710: 07/07/11: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121711: 07/07/11: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121712: 07/07/11: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121754: 07/07/12: <ghelbig@lycos.com>: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121782: 07/07/12: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121841: 07/07/13: Duth: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121848: 07/07/13: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121925: 07/07/15: christophe ALEXANDRE: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121943: 07/07/15: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121944: 07/07/15: Peter Alfke: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121958: 07/07/16: <cs_posting@hotmail.com>: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121964: 07/07/16: Jarek Rozanski: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121965: 07/07/16: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121966: 07/07/16: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121976: 07/07/16: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121977: 07/07/16: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121978: 07/07/16: Totally_Lost: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121984: 07/07/16: Andy Peters: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
122032: 07/07/18: <ghelbig@lycos.com>: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
122051: 07/07/18: Torsten Landschoff: Re: Revisit: Altera vs Xilinx (NIOS II vs Microblaze)
121468: 07/07/05: <azzhang2007@hotmail.com>: Does synplify 8.8 can support xilinx virtex5?
121477: 07/07/05: John_H: Re: Does synplify 8.8 can support xilinx virtex5?
121504: 07/07/06: your_friendly_synplify_support: Re: Does synplify 8.8 can support xilinx virtex5?
121469: 07/07/05: <Jesper.Kristensen@tellabs.com>: Spartan-3A: 200A & 400A Image problems / variance...
121479: 07/07/05: John_H: Re: Spartan-3A: 200A & 400A Image problems / variance...
121493: 07/07/05: Gabor: Re: Spartan-3A: 200A & 400A Image problems / variance...
121475: 07/07/05: vssumesh: Doubt in Asynchronus Circuit design
121478: 07/07/05: Gabor: Re: Doubt in Asynchronus Circuit design
121498: 07/07/06: Sylvain Munaut: Re: Doubt in Asynchronus Circuit design
121505: 07/07/06: Jonathan Bromley: Re: Doubt in Asynchronus Circuit design
121510: 07/07/06: Jonathan Bromley: Re: Doubt in Asynchronus Circuit design
121519: 07/07/06: Symon: Re: Doubt in Asynchronus Circuit design
121570: 07/07/08: Jonathan Bromley: Re: Doubt in Asynchronus Circuit design
121497: 07/07/05: vssumesh: Re: Doubt in Asynchronus Circuit design
121500: 07/07/05: vssumesh: Re: Doubt in Asynchronus Circuit design
121508: 07/07/06: vssumesh: Re: Doubt in Asynchronus Circuit design
121516: 07/07/06: Gabor: Re: Doubt in Asynchronus Circuit design
121518: 07/07/06: Gabor: Re: Doubt in Asynchronus Circuit design
121565: 07/07/08: vssumesh: Re: Doubt in Asynchronus Circuit design
121569: 07/07/08: Peter Alfke: Re: Doubt in Asynchronus Circuit design
121481: 07/07/05: vt2001cpe: Multiple Core generator MAC FIR Filter 5.1 Cores
121492: 07/07/05: vt2001cpe: Re: Multiple Core generator MAC FIR Filter 5.1 Cores
121530: 07/07/06: vt2001cpe: Re: Multiple Core generator MAC FIR Filter 5.1 Cores
121536: 07/07/06: MM: Re: Multiple Core generator MAC FIR Filter 5.1 Cores
121575: 07/07/08: MM: Re: Multiple Core generator MAC FIR Filter 5.1 Cores
121554: 07/07/08: vt2001cpe: Re: Multiple Core generator MAC FIR Filter 5.1 Cores
121499: 07/07/05: <hobin0920@gmail.com>: USB analyzer evaluation
121561: 07/07/08: Antti: Re: USB analyzer evaluation
121502: 07/07/06: Franz Hollerer: Xilinx ISE, EDK and some ground roules in software development
121503: 07/07/05: Antti: Re: Xilinx ISE, EDK and some ground roules in software development
121509: 07/07/06: PFC: Re: Xilinx ISE, EDK and some ground roules in software development
121781: 07/07/13: Ken Ryan: Re: Xilinx ISE, EDK and some ground roules in software development
121513: 07/07/06: Laurent Pinchart: Re: Xilinx ISE, EDK and some ground roules in software development
121527: 07/07/06: <steve.lass@xilinx.com>: Re: Xilinx ISE, EDK and some ground roules in software development
121537: 07/07/06: Eric Smith: Re: Xilinx ISE, EDK and some ground roules in software development
121539: 07/07/07: Jim Granville: Re: Xilinx ISE, EDK and some ground roules in software development
121540: 07/07/06: MM: Re: Xilinx ISE, EDK and some ground roules in software development
121547: 07/07/07: <pbFJKD@ludd.invalid>: Re: Xilinx ISE, EDK and some ground roules in software development
121549: 07/07/07: Laurent Pinchart: Re: Xilinx ISE, EDK and some ground roules in software development
121515: 07/07/06: <pbFJKD@ludd.invalid>: Re: Xilinx ISE, EDK and some ground roules in software development
121520: 07/07/06: MK: Re: Xilinx ISE, EDK and some ground roules in software development
121522: 07/07/06: Franz Hollerer: Re: Xilinx ISE, EDK and some ground roules in software development
121525: 07/07/06: <pbFJKD@ludd.invalid>: Re: Xilinx ISE, EDK and some ground roules in software development
122192: 07/07/23: svenand: Re: Xilinx ISE, EDK and some ground roules in software development
121511: 07/07/06: Marco Albero: I need relocate my program outside bram...
121523: 07/07/06: radarman: Re: I need relocate my program outside bram...
121514: 07/07/06: <ryufrank@hotmail.com>: New with FGPAs
121517: 07/07/06: vssumesh: Re: New with FGPAs
121548: 07/07/07: N.V. Chandramouli: Re: New with FGPAs
122191: 07/07/23: svenand: Re: New with FGPAs
121521: 07/07/06: Callisto: ML501 Constraints file problems
122152: 07/07/20: Callisto: Re: ML501 Constraints file problems
121524: 07/07/06: water9580@yahoo.com: ML555 SATA GTP dosen't work
121532: 07/07/06: austin: Re: ML555 SATA GTP dosen't work
121533: 07/07/06: austin: Re: ML555 SATA GTP dosen't work
121529: 07/07/06: <e2point@yahoo.com>: or1200 uses more than 100% of resources. how to reduce?
122067: 07/07/18: Ralf Hildebrandt: Re: or1200 uses more than 100% of resources. how to reduce?
122074: 07/07/18: John_H: Re: or1200 uses more than 100% of resources. how to reduce?
122095: 07/07/19: RCIngham: Re: or1200 uses more than 100% of resources. how to reduce?
122446: 07/07/27: <e2point@yahoo.com>: Re: or1200 uses more than 100% of resources. how to reduce?
122449: 07/07/27: Peter Alfke: Re: or1200 uses more than 100% of resources. how to reduce?
122451: 07/07/27: mk: Re: or1200 uses more than 100% of resources. how to reduce?
122461: 07/07/27: Peter Alfke: Re: or1200 uses more than 100% of resources. how to reduce?
121534: 07/07/06: kislo: Debugging in EDK
121576: 07/07/09: John Williams: Re: Debugging in EDK
121583: 07/07/09: Brian Drummond: Re: Debugging in EDK
121538: 07/07/06: vballu: sdr woes
121543: 07/07/07: vasile: multiprocessor design-shared memory-howto
121545: 07/07/07: <e2point@yahoo.com>: or1k binutil source checkout problem
121546: 07/07/07: rajiv: verilog code for read write in Bram block
121550: 07/07/07: evilkidder@googlemail.com: Re: verilog code for read write in Bram block
121551: 07/07/08: JD Newcomb: XPS 8.2 "UPDATE Tcl procedures"?
121618: 07/07/10: JD Newcomb: Re: XPS 8.2 "UPDATE Tcl procedures"?
121553: 07/07/07: cwoodring: XilinxSystemGenerator and Simulink
121590: 07/07/09: <naude.jaco@gmail.com>: Re: XilinxSystemGenerator and Simulink
121658: 07/07/11: cwoodring: Re: XilinxSystemGenerator and Simulink
121665: 07/07/11: Jaco Naude: Re: XilinxSystemGenerator and Simulink
122157: 07/07/20: ashishshuklabs: Re: XilinxSystemGenerator and Simulink
121555: 07/07/07: water9580@yahoo.com: ML555 SFP module
121556: 07/07/07: water9580@yahoo.com: Re: ML555 SFP module
121660: 07/07/11: Mike Treseler: Re: ML555 SFP module
121652: 07/07/10: water9580@yahoo.com: Re: ML555 SFP module
121557: 07/07/08: rajiv: verilog code for read write in bram block
121558: 07/07/08: hurleybp: Re: verilog code for read write in bram block
121559: 07/07/08: bjzhangwn@gmail.com: fifo counter in virtex-4
121560: 07/07/08: Symon: Re: fifo counter in virtex-4
121563: 07/07/08: John_H: Re: fifo counter in virtex-4
121577: 07/07/09: John Retta: Re: fifo counter in virtex-4
121564: 07/07/08: Jason Whitwam: Question on Virtex2p DCMs usability
121568: 07/07/08: Peter Monta: Re: Question on Virtex2p DCMs usability
121572: 07/07/08: Jason Whitwam: Re: Question on Virtex2p DCMs usability
121574: 07/07/08: Mike Treseler: Re: Question on Virtex2p DCMs usability
121571: 07/07/08: John_H: Re: Question on Virtex2p DCMs usability
121573: 07/07/08: Jason Whitwam: Re: Question on Virtex2p DCMs usability
121566: 07/07/08: Jarek Rozanski: LiveDesign, Altium [opinion]
121598: 07/07/09: Nial Stewart: Re: LiveDesign, Altium [opinion]
121621: 07/07/10: Mark McDougall: Re: LiveDesign, Altium [opinion]
121605: 07/07/09: Jarek Rozanski: Re: LiveDesign, Altium [opinion]
121624: 07/07/09: <joel.pigdon@gmail.com>: Re: LiveDesign, Altium [opinion]
121724: 07/07/12: John Adair: Re: LiveDesign, Altium [opinion]
121579: 07/07/09: rajiv: Adding a bram block to a user defined bram controller
121586: 07/07/09: ZHI: The delay time of coregen Multiplier in Modelsim
121588: 07/07/09: Metin: Spartan3A : timing Constraints / DCM Outputs
121592: 07/07/09: Metin: Re: Spartan3A : timing Constraints / DCM Outputs
121594: 07/07/09: Mike Treseler: Re: Spartan3A : timing Constraints / DCM Outputs
121635: 07/07/10: Metin: Re: Spartan3A : timing Constraints / DCM Outputs
121589: 07/07/09: ekavirsrikanth@gmail.com: regarding post place and route timing simulation steps........
121593: 07/07/09: Mike Treseler: Re: regarding post place and route timing simulation steps........
121640: 07/07/10: Duth: Re: regarding post place and route timing simulation steps........
121649: 07/07/10: ekavirsrikanth@gmail.com: Re: regarding post place and route timing simulation steps........
121591: 07/07/09: <naude.jaco@gmail.com>: Error message in ModelSIM PE
121596: 07/07/09: RCIngham: Re: Error message in ModelSIM PE
121597: 07/07/09: Mike Treseler: Re: Error message in ModelSIM PE
121595: 07/07/09: Marco Albero: Problem usign xilfatfs...
121627: 07/07/10: Marco Albero: Re: Here you have the 'system.hms'
121647: 07/07/10: Siva Velusamy: Re: Here you have the 'system.hms'
121628: 07/07/10: Marco Albero: Re: And here the 'system.mss'
121599: 07/07/09: axr0284: A Way for a DSP to tell an FPGA to load itself from Flash
121600: 07/07/09: austin: Re: A Way for a DSP to tell an FPGA to load itself from Flash
121609: 07/07/09: austin: Re: A Way for a DSP to tell an FPGA to load itself from Flash
121614: 07/07/10: PFC: Re: A Way for a DSP to tell an FPGA to load itself from Flash
121608: 07/07/09: axr0284: Re: A Way for a DSP to tell an FPGA to load itself from Flash
121633: 07/07/10: axr0284: Re: A Way for a DSP to tell an FPGA to load itself from Flash
121611: 07/07/09: Matthew Hicks: Synplify Problem
121612: 07/07/09: Mike Treseler: Re: Synplify Problem
121622: 07/07/10: Matthew Hicks: Re: Synplify Problem
121613: 07/07/09: John_H: Re: Synplify Problem
121616: 07/07/09: Matthew Hicks: Re: Synplify Problem
121769: 07/07/12: Matthew Hicks: Re: Synplify Problem
121617: 07/07/09: Andy: Re: Synplify Problem
121623: 07/07/10: Matthew Hicks: Re: Synplify Problem
121619: 07/07/09: chakra: DDR SDRAM simulation model, ML300, Infineon
121620: 07/07/09: chakra: Re: DDR SDRAM simulation model, ML300, Infineon
121625: 07/07/10: Sean Durkin: Re: DDR SDRAM simulation model, ML300, Infineon
121631: 07/07/10: Jim Wu: Re: DDR SDRAM simulation model, ML300, Infineon
121636: 07/07/10: chakra: Re: DDR SDRAM simulation model, ML300, Infineon
121637: 07/07/10: Kevin Neilson: Re: DDR SDRAM simulation model, ML300, Infineon
122190: 07/07/23: svenand: Re: DDR SDRAM simulation model, ML300, Infineon
121626: 07/07/10: archana: configuring vertex4 FPGA
121634: 07/07/10: Matthew Hicks: Re: configuring vertex4 FPGA
121629: 07/07/10: archana: slave serial configuration of Vertex FPGA using a microcontroller
121630: 07/07/10: Symon: Re: slave serial configuration of Vertex FPGA using a microcontroller
121632: 07/07/10: Gabor: Re: slave serial configuration of Vertex FPGA using a microcontroller
121638: 07/07/10: Naveen: ISE 9.1i - Process Map Fail without any Error messages
121641: 07/07/10: John_H: Re: ISE 9.1i - Process Map Fail without any Error messages
121644: 07/07/10: Symon: Re: ISE 9.1i - Process Map Fail without any Error messages
121659: 07/07/11: Gabor: Re: ISE 9.1i - Process Map Fail without any Error messages
121642: 07/07/10: Fred: EDK and ecncrpted .bit, .nky, .mcs files
121646: 07/07/10: austin: Re: EDK and ecncrpted .bit, .nky, .mcs files
121643: 07/07/10: <drop669@gmail.com>: lpm_constant function in Altera Quartus 7.1
121645: 07/07/10: Mike Treseler: Re: lpm_constant function in Altera Quartus 7.1
121648: 07/07/10: Ace: SystemC in modeling HW/SW
121655: 07/07/11: HT-Lab: Re: SystemC in modeling HW/SW
121809: 07/07/13: Patrick Dubois: Re: SystemC in modeling HW/SW
121650: 07/07/10: Xilinx User: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121653: 07/07/11: Jim Granville: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121656: 07/07/11: Jon Beniston: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121657: 07/07/11: Jon Beniston: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121661: 07/07/11: Uncle Noah: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121666: 07/07/11: Sylvain Munaut: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121672: 07/07/11: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121677: 07/07/11: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121679: 07/07/11: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121681: 07/07/11: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121683: 07/07/11: Nico Coesel: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121687: 07/07/11: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121691: 07/07/11: Matthew Hicks: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121728: 07/07/12: Rainer Buchty: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121736: 07/07/12: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121739: 07/07/12: Jan Panteltje: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121752: 07/07/12: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121753: 07/07/12: Jan Panteltje: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121741: 07/07/12: Nico Coesel: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121765: 07/07/13: Jim Granville: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121768: 07/07/12: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121774: 07/07/13: Jim Granville: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,Leon)?
121777: 07/07/12: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,Leon)?
121730: 07/07/12: <anonymous@nowhere.you.know>: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121737: 07/07/12: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121788: 07/07/13: Colin Paul Gloster: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121663: 07/07/11: Jon Beniston: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121667: 07/07/11: Uncle Noah: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121668: 07/07/11: Jon Beniston: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121669: 07/07/11: Xilinx User: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121673: 07/07/11: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121676: 07/07/11: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121697: 07/07/12: Jim Granville: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121703: 07/07/11: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121738: 07/07/12: austin: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32,
121670: 07/07/11: Uncle Noah: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121674: 07/07/11: Antti: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121675: 07/07/11: Jon Beniston: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121678: 07/07/11: Antti: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121685: 07/07/11: jacko: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121688: 07/07/11: Jon Beniston: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121715: 07/07/11: Uncle Noah: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121742: 07/07/12: Sandro: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121743: 07/07/12: Uncle Noah: Re: Anyone really use those opensource CPUs (OR1K, Lattice Mico32, Leon)?
121651: 07/07/10: ujjwal: Type Conversion in VHDL
121654: 07/07/11: Symon: Re: Type Conversion in VHDL
121664: 07/07/11: Matthew Hicks: Re: Type Conversion in VHDL
121662: 07/07/11: Matthew Hicks: Re: Virtex-II Pro Flip-Flop Setup time
121671: 07/07/11: <miche>: Strange warning message from ise8.2i ?
121680: 07/07/11: John_H: Re: Strange warning message from ise8.2i ?
121689: 07/07/11: <miche>: Re: Strange warning message from ise8.2i ?
121693: 07/07/11: John_H: Re: Strange warning message from ise8.2i ?
121700: 07/07/11: <miche>: Re: Strange warning message from ise8.2i ?
121704: 07/07/11: John_H: Re: Strange warning message from ise8.2i ?
121682: 07/07/11: ML402: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
121684: 07/07/11: Jaco Naude: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
121686: 07/07/11: Jaco Naude: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
121690: 07/07/11: ML402: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
121692: 07/07/11: ML402: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
121746: 07/07/12: ML402: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
121751: 07/07/12: ML402: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
121844: 07/07/13: ML402: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
121850: 07/07/13: ML402: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic
121698: 07/07/12: Jim Granville: Re: Virtex-II Pro Flip-Flop Setup time
121713: 07/07/12: Jim Granville: Re: Virtex-II Pro Flip-Flop Setup time
121701: 07/07/12: Jim Granville: Altera MAX III Status ?
121723: 07/07/12: Antti: Re: Altera MAX III Status ?
121729: 07/07/12: Jim Granville: Re: Altera MAX III Status ?
121732: 07/07/12: Rob: Re: Altera MAX III Status ?
121762: 07/07/13: Jim Granville: Re: Altera MAX III Status ?
121771: 07/07/12: Rob: Re: Altera MAX III Status ?
121714: 07/07/11: <mailsatishv@gmail.com>: New board JTAG error
121717: 07/07/12: John_H: Re: New board JTAG error
121735: 07/07/12: <mailsatishv@gmail.com>: Re: New board JTAG error
121716: 07/07/12: Yao Sics: Chipscope 9.1: Any easy way to rename and regroup signals?
121719: 07/07/12: Zara: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121721: 07/07/12: Ben Jackson: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121726: 07/07/12: Symon: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121720: 07/07/11: Yao Sics: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121725: 07/07/12: Yao Sics: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121731: 07/07/12: Martin Thompson: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121775: 07/07/13: Patrick Dubois: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121792: 07/07/13: Symon: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121836: 07/07/13: Symon: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121908: 07/07/15: Symon: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121802: 07/07/13: Patrick Dubois: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121843: 07/07/13: Patrick Dubois: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121933: 07/07/15: Weng Tianxiang: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121954: 07/07/16: Patrick Dubois: Re: Chipscope 9.1: Any easy way to rename and regroup signals?
121718: 07/07/11: radarman: Flex 10k100 & EPC2 redux - forgot the special ingredient?
121722: 07/07/12: Ben Jackson: Re: Flex 10k100 & EPC2 redux - forgot the special ingredient?
121727: 07/07/12: Jaco Naude: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
121733: 07/07/12: LilacSkin: ASM within C code in a PPC405 of VIRTEX II Pro
121734: 07/07/12: Matthew Hicks: Re: ASM within C code in a PPC405 of VIRTEX II Pro
121869: 07/07/13: Jeff Cunningham: Re: ASM within C code in a PPC405 of VIRTEX II Pro
121874: 07/07/14: Ken Ryan: Re: ASM within C code in a PPC405 of VIRTEX II Pro
121898: 07/07/14: Matthew Hicks: Re: ASM within C code in a PPC405 of VIRTEX II Pro
121948: 07/07/16: LilacSkin: Re: ASM within C code in a PPC405 of VIRTEX II Pro
121806: 07/07/13: LilacSkin: Re: ASM within C code in a PPC405 of VIRTEX II Pro
121835: 07/07/13: LilacSkin: Re: ASM within C code in a PPC405 of VIRTEX II Pro
121740: 07/07/12: Geronimo Stempovski: Designing the right clock tree for a multi-FPGA setup
121745: 07/07/12: Bob Perlman: Re: Designing the right clock tree for a multi-FPGA setup
121750: 07/07/12: austin: Re: Designing the right clock tree for a multi-FPGA setup
121786: 07/07/13: Geronimo Stempovski: Re: Designing the right clock tree for a multi-FPGA setup
121819: 07/07/13: austin: Re: Designing the right clock tree for a multi-FPGA setup
121824: 07/07/13: Geronimo Stempovski: Re: Designing the right clock tree for a multi-FPGA setup
121831: 07/07/13: austin: Re: Designing the right clock tree for a multi-FPGA setup
121945: 07/07/16: Geronimo Stempovski: Re: Designing the right clock tree for a multi-FPGA setup
121757: 07/07/12: <mikeandmax@aol.com>: Re: Designing the right clock tree for a multi-FPGA setup
121799: 07/07/13: <phil-news-nospam@ipal.net>: Re: Designing the right clock tree for a multi-FPGA setup
121810: 07/07/13: John Larkin: Re: Designing the right clock tree for a multi-FPGA setup
121811: 07/07/13: Symon: Re: Designing the right clock tree for a multi-FPGA setup
121821: 07/07/13: Geronimo Stempovski: Re: Designing the right clock tree for a multi-FPGA setup
121823: 07/07/13: Symon: Re: Designing the right clock tree for a multi-FPGA setup
121825: 07/07/13: PFC: Re: Designing the right clock tree for a multi-FPGA setup
121744: 07/07/12: Maurice Branson: highly-parallel highspeed connection between two FPGA boards
121747: 07/07/12: MM: Re: highly-parallel highspeed connection between two FPGA boards
121748: 07/07/12: John_H: Re: highly-parallel highspeed connection between two FPGA boards
121755: 07/07/12: dave: Re: highly-parallel highspeed connection between two FPGA boards
121776: 07/07/12: whit3rd: Re: highly-parallel highspeed connection between two FPGA boards
121785: 07/07/13: Maurice Branson: Re: highly-parallel highspeed connection between two FPGA boards
121789: 07/07/13: RCIngham: Re: highly-parallel highspeed connection between two FPGA boards
121807: 07/07/13: Symon: Re: highly-parallel highspeed connection between two FPGA boards
121820: 07/07/13: Marc Battyani: Re: highly-parallel highspeed connection between two FPGA boards
121931: 07/07/15: Anton Erasmus: Re: highly-parallel highspeed connection between two FPGA boards
121827: 07/07/13: MM: Re: highly-parallel highspeed connection between two FPGA boards
121790: 07/07/13: comp.arch.fpga: Re: highly-parallel highspeed connection between two FPGA boards
121894: 07/07/14: David L. Jones: Re: highly-parallel highspeed connection between two FPGA boards
121756: 07/07/12: <spacegato@gmail.com>: Xilinx PCIe endpoint core minimalistic design
121773: 07/07/13: Mark McDougall: Re: Xilinx PCIe endpoint core minimalistic design
122310: 07/07/25: <spacegato@gmail.com>: Re: Xilinx PCIe endpoint core minimalistic design
121759: 07/07/12: craigtmoore@googlemail.com: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121761: 07/07/12: austin: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation
121767: 07/07/12: Matthew Hicks: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121770: 07/07/12: austin: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation
121818: 07/07/13: austin: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation
121772: 07/07/13: Craig Moore: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121783: 07/07/13: backhus: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation
121829: 07/07/13: Sandro: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121834: 07/07/13: Duth: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121883: 07/07/14: Craig Moore: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121884: 07/07/14: Craig Moore: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121885: 07/07/14: Craig Moore: Re: Convert Schematic Files (.sch) to Verilog Files (.v) for simulation in ModelSim
121760: 07/07/12: Eddie H: CML output swing for V5
121763: 07/07/12: austin: Re: CML output swing for V5
121778: 07/07/12: Eddie H: Re: CML output swing for V5
121764: 07/07/12: John_H: Re: CML output swing for V5
121779: 07/07/12: Eddie H: Re: CML output swing for V5
121784: 07/07/13: John_H: Re: CML output swing for V5
121801: 07/07/13: Eddie H: Re: CML output swing for V5
121803: 07/07/13: John_H: Re: CML output swing for V5
121830: 07/07/13: Eddie H: Re: CML output swing for V5
121838: 07/07/13: John_H: Re: CML output swing for V5
121840: 07/07/13: Eddie H: Re: CML output swing for V5
121846: 07/07/13: John_H: Re: CML output swing for V5
121866: 07/07/13: Eddie H: Re: CML output swing for V5
121780: 07/07/12: <weg22@drexel.edu>: Help with Libero IDE and Verilog...
122056: 07/07/18: <rouzbeh.h@actel.com>: Re: Help with Libero IDE and Verilog...
122072: 07/07/18: <rouzbeh.h@actel.com>: Re: Help with Libero IDE and Verilog...
121791: 07/07/13: <miche>: Counter ?
121793: 07/07/13: Jon Beniston: Re: Counter ?
121794: 07/07/13: Symon: Re: Counter ?
121797: 07/07/13: <miche>: Re: Counter ?
121862: 07/07/14: Jim Granville: Re: Counter ?
121804: 07/07/13: c d saunter: Re: Counter ?
121795: 07/07/13: Alan Myler: Re: Counter ?
121796: 07/07/13: <miche>: Re: Counter ?
121800: 07/07/13: Jonathan Bromley: Re: Counter ?
121798: 07/07/13: Jon Beniston: Re: Counter ?
121805: 07/07/13: John_H: Re: Counter ?
121812: 07/07/13: <miche>: Re: Counter ?
121814: 07/07/13: Symon: Re: Counter ?
121815: 07/07/13: PFC: Re: Counter ?
121817: 07/07/13: <miche>: Re: Counter ?
121832: 07/07/13: <miche>: Re: Counter ?
121842: 07/07/13: <miche>: Re: Counter ?
121847: 07/07/13: <miche>: Re: Counter ?
121854: 07/07/13: <miche>: Re: Counter ?
121859: 07/07/13: John_H: Re: Counter ?
122142: 07/07/20: Ralf Hildebrandt: Re: Counter ?
121837: 07/07/13: John_H: Re: Counter ?
121849: 07/07/13: <miche>: Re: Counter ?
121855: 07/07/13: <miche>: Re: Counter ?
121864: 07/07/14: Jim Granville: Re: Counter ?
121860: 07/07/13: John_H: Re: Counter ?
121816: 07/07/13: Jon Beniston: Re: Counter ?
121828: 07/07/13: Jon Beniston: Re: Counter ?
121839: 07/07/13: Jon Beniston: Re: Counter ?
121845: 07/07/13: Jon Beniston: Re: Counter ?
121851: 07/07/13: Peter Alfke: Re: Counter ?
121861: 07/07/14: Jim Granville: Re: Counter ?
121872: 07/07/13: Jon Beniston: Re: Counter ?
121808: 07/07/13: jacobusn@xilinx.com: Re: MiG : Memory Interface (DDR SDRAM) as an ISE schematic symbol
121813: 07/07/13: <SWAmdata@gmail.com>: Xilinx V4 Custom IP
121826: 07/07/13: PFC: Newbie's first FPGA board !
121833: 07/07/13: austin: Re: Newbie's first FPGA board !
121897: 07/07/14: PFC: Re: Newbie's first FPGA board !
121852: 07/07/13: Ben Jackson: Re: Newbie's first FPGA board !
121887: 07/07/14: PFC: Re: Newbie's first FPGA board !
121893: 07/07/14: Ben Jackson: Re: Newbie's first FPGA board !
121896: 07/07/14: PFC: Re: Newbie's first FPGA board !
121907: 07/07/15: Ben Jackson: Re: Newbie's first FPGA board !
121916: 07/07/15: PFC: Re: Newbie's first FPGA board !
121922: 07/07/15: John_H: Re: Newbie's first FPGA board !
121952: 07/07/16: PFC: Re: Newbie's first FPGA board !
121956: 07/07/16: John_H: Re: Newbie's first FPGA board !
121962: 07/07/16: PFC: Re: Newbie's first FPGA board !
121963: 07/07/16: John_H: Re: Newbie's first FPGA board !
121973: 07/07/16: PFC: Re: Newbie's first FPGA board !
121972: 07/07/16: Ben Jackson: Re: Newbie's first FPGA board !
122006: 07/07/17: PFC: Re: Newbie's first FPGA board !
122036: 07/07/17: Ben Jackson: Re: Newbie's first FPGA board !
121853: 07/07/13: bwilson79@gmail.com: Seeing failures when clocking system-synchronous inter-FPGA interfaces at lower clock rates
121856: 07/07/13: Gabor: Re: Seeing failures when clocking system-synchronous inter-FPGA interfaces at lower clock rates
121857: 07/07/13: bwilson79@gmail.com: Re: Seeing failures when clocking system-synchronous inter-FPGA interfaces at lower clock rates
121863: 07/07/13: John_H: Re: Seeing failures when clocking system-synchronous inter-FPGA interfaces at lower clock rates
121858: 07/07/13: Marc Battyani: What is the resistance of a big FPGA for VCCINT (unpowered)
121865: 07/07/13: John_H: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121868: 07/07/13: MM: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121870: 07/07/13: austin: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121871: 07/07/13: John_H: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121993: 07/07/16: Eric Smith: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
122004: 07/07/17: John_H: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
122031: 07/07/17: Eric Smith: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121873: 07/07/14: Marc Battyani: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121886: 07/07/14: Georg Acher: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121890: 07/07/14: austin: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121930: 07/07/15: Ben Twijnstra: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121940: 07/07/15: Marc Battyani: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121982: 07/07/16: Ben Jackson: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121979: 07/07/16: Totally_Lost: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121980: 07/07/16: Totally_Lost: Re: What is the resistance of a big FPGA for VCCINT (unpowered)
121875: 07/07/13: Brian Davis: Re: CML output swing for V5
121876: 07/07/14: jjlindula@hotmail.com: Image Resolution Rescaling
121877: 07/07/13: Peter Alfke: Re: Image Resolution Rescaling
121880: 07/07/14: Jim Granville: Re: Image Resolution Rescaling
121889: 07/07/14: John_H: Re: Image Resolution Rescaling
121892: 07/07/14: Pete Fraser: Re: Image Resolution Rescaling
121888: 07/07/14: jjlindula@hotmail.com: Re: Image Resolution Rescaling
121878: 07/07/14: Cla: Which embedded O/S for a 32-bit RISC microcontroller?
121881: 07/07/14: Nico Coesel: Re: Which embedded O/S for a 32-bit RISC microcontroller?
121929: 07/07/16: David R Brooks: Re: Which embedded O/S for a 32-bit RISC microcontroller?
121927: 07/07/15: <ghelbig@lycos.com>: Re: Which embedded O/S for a 32-bit RISC microcontroller?
121934: 07/07/15: Tommy Thorn: Re: Which embedded O/S for a 32-bit RISC microcontroller?
121941: 07/07/15: John_H: Re: Which embedded O/S for a 32-bit RISC microcontroller?
122023: 07/07/17: Sean Durkin: Re: Which embedded O/S for a 32-bit RISC microcontroller?
121879: 07/07/13: ekavirsrikanth@gmail.com: DCM CLK driving load problem
121882: 07/07/14: Andrew Holme: Re: DCM CLK driving load problem
121891: 07/07/14: Pasacco: [ISE] How to create and map user library in command-line?
121895: 07/07/14: Mike Treseler: Re: [ISE] How to create and map user library in command-line?
121918: 07/07/15: Sylvain Munaut: Re: How to create and map user library in command-line?
121928: 07/07/15: Duane Clark: Re: How to create and map user library in command-line?
121938: 07/07/15: Sylvain Munaut: Re: How to create and map user library in command-line?
121917: 07/07/15: Pasacco: Re: How to create and map user library in command-line?
121924: 07/07/15: Pasacco: Re: How to create and map user library in command-line?
121899: 07/07/14: John Larkin: Re: ESR Meter - design contest
121901: 07/07/15: PFC: Re: ESR Meter - design contest
121902: 07/07/14: krw: Re: ESR Meter - design contest
121903: 07/07/15: Jim Granville: Re: ESR Meter - design contest
121904: 07/07/14: John Larkin: Re: ESR Meter - design contest
121905: 07/07/15: Jim Granville: Re: ESR Meter - design contest
121906: 07/07/14: John Larkin: Re: ESR Meter - design contest
121909: 07/07/15: Jim Granville: Re: ESR Meter - design contest
121912: 07/07/15: Nico Coesel: Re: ESR Meter - design contest
121913: 07/07/15: Antonio Pasini: Re: ESR Meter - design contest
122076: 07/07/18: John Larkin: Re: ESR Meter - design contest
121949: 07/07/16: Jasen Betts: Re: ESR Meter - design contest
121911: 07/07/15: Nico Coesel: Re: ESR Meter - design contest
121926: 07/07/15: John Larkin: Re: ESR Meter - design contest
121932: 07/07/15: Ben Twijnstra: Re: ESR Meter - design contest
121900: 07/07/14: <jonpry@gmail.com>: spartan-3e idcode
121915: 07/07/15: Uwe Bonnes: Re: spartan-3e idcode
121920: 07/07/15: Alan Nishioka: Re: spartan-3e idcode
121921: 07/07/15: austin: Re: spartan-3e idcode
121939: 07/07/15: austin: Re: spartan-3e idcode
121987: 07/07/16: austin: Re: spartan-3e idcode
121935: 07/07/15: <jonpry@gmail.com>: Re: spartan-3e idcode
121936: 07/07/15: Alan Nishioka: Re: spartan-3e idcode
121937: 07/07/15: <jonpry@gmail.com>: Re: spartan-3e idcode
121960: 07/07/16: Alan Nishioka: Re: spartan-3e idcode
121974: 07/07/16: <jonpry@gmail.com>: Re: spartan-3e idcode
121985: 07/07/16: Alan Nishioka: Re: spartan-3e idcode
121914: 07/07/15: maxascent: QDR II SRAM Interface
121923: 07/07/15: austin: Re: QDR II SRAM Interface
121942: 07/07/16: Kiran: QuartusII Web Edition software question
121946: 07/07/16: Ben Twijnstra: Re: QuartusII Web Edition software question
122202: 07/07/23: Mike Treseler: Re: QuartusII Web Edition software question
122200: 07/07/23: Kiran: Re: QuartusII Web Edition software question
121947: 07/07/16: <roche.alexis@gmail.com>: Timing in Modelsim
121951: 07/07/16: KJ: Re: Timing in Modelsim
121953: 07/07/16: <roche.alexis@gmail.com>: Re: Timing in Modelsim
121957: 07/07/16: Matthew Hicks: Re: Timing in Modelsim
121950: 07/07/16: Andreas Hofmann: Microblaze V4 / FSL2.0 - putfsl_interruptable() not working reliably
121955: 07/07/16: Göran Bilski: Re: Microblaze V4 / FSL2.0 - putfsl_interruptable() not working reliably
121968: 07/07/16: Andreas Hofmann: Re: Microblaze V4 / FSL2.0 - putfsl_interruptable() not working reliably
121959: 07/07/16: Wei Chen: 1ms delay in V5 FPGA
121961: 07/07/16: Matthew Hicks: Re: 1ms delay in V5 FPGA
121967: 07/07/16: RCIngham: Re: 1ms delay in V5 FPGA
121981: 07/07/16: Jeff Cunningham: Re: 1ms delay in V5 FPGA
121970: 07/07/16: <ghelbig@lycos.com>: Re: New board JTAG problem.
121975: 07/07/16: Pasacco: How to obtain (accurate) critical path delay?
121989: 07/07/17: Ken Ryan: EDK9.1 LWIP network stack crashing?
121990: 07/07/17: Jeff Cunningham: chipscope PLB IBA - how to get meaningful labels on signals?
121996: 07/07/17: <adam.taylor@selex-sas.com>: Re: chipscope PLB IBA - how to get meaningful labels on signals?
122007: 07/07/17: Jeff Cunningham: Re: chipscope PLB IBA - how to get meaningful labels on signals?
122027: 07/07/17: Siva Velusamy: Re: chipscope PLB IBA - how to get meaningful labels on signals?
122038: 07/07/17: Ben Jackson: Re: chipscope PLB IBA - how to get meaningful labels on signals?
121991: 07/07/16: <richng01@gmail.com>: Xilinx System generator vs Simulink HDL Coder
122002: 07/07/17: Martin Thompson: Re: Xilinx System generator vs Simulink HDL Coder
122078: 07/07/18: cwoodring: Re: Xilinx System generator vs Simulink HDL Coder
121992: 07/07/17: Jon Elson: Xilinx XC9536 current draw ?
121995: 07/07/17: Jim Granville: Re: Xilinx XC9536 current draw ?
122015: 07/07/17: Jon Elson: Re: Xilinx XC9536 current draw ?
122020: 07/07/17: Andy Botterill: Re: Xilinx XC9536 current draw ?
122037: 07/07/17: Jon Elson: Re: Xilinx XC9536 current draw ?
122040: 07/07/18: Jim Granville: Re: Xilinx XC9536 current draw ?
122041: 07/07/18: Jim Granville: Re: Xilinx XC9536 current draw ?
122044: 07/07/18: Jon Elson: Re: Xilinx XC9536 current draw ?
122022: 07/07/18: Jim Granville: Re: Xilinx XC9536 current draw ?
122008: 07/07/17: <lb.edc@telenet.be>: Re: Xilinx XC9536 current draw ?
122018: 07/07/17: Jon Elson: Re: Xilinx XC9536 current draw ?
122019: 07/07/17: <lb.edc@telenet.be>: Re: Xilinx XC9536 current draw ?
122034: 07/07/18: <x@x.com>: Re: Xilinx XC9536 current draw ?
122035: 07/07/17: Jon Elson: Re: Xilinx XC9536 current draw ?
122053: 07/07/18: <vze24h5m@verizon.net>: Re: Xilinx XC9536 current draw ?
122409: 07/07/27: Andreas Ehliar: Re: Xilinx XC9536 current draw ?
121998: 07/07/17: gouaich: Req: (Free) Embedded Platforms for Education
121999: 07/07/17: Symon: Re: (Free) Embedded Platforms for Education
122025: 07/07/18: John Williams: Re: Req: (Free) Embedded Platforms for Education
122050: 07/07/18: John Adair: Re: Req: (Free) Embedded Platforms for Education
122189: 07/07/23: svenand: Re: Req: (Free) Embedded Platforms for Education
122203: 07/07/23: <gouaich@lirmm.fr>: Re: Req: (Free) Embedded Platforms for Education
122000: 07/07/17: Antti: Xilinx S3 Starterkit, how hot it is supposed to be?
122005: 07/07/17: Tim (one of many): Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122009: 07/07/17: Symon: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122064: 07/07/18: austin: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122112: 07/07/19: austin: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122066: 07/07/18: Symon: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122069: 07/07/18: Andy Botterill: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122164: 07/07/21: David M. Palmer: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122179: 07/07/23: Symon: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122026: 07/07/17: Tommy Thorn: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122089: 07/07/19: Symon: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122049: 07/07/18: Sandro: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122063: 07/07/18: Antti: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122087: 07/07/19: Antti: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122105: 07/07/19: Antti: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122135: 07/07/19: Antti: Re: Xilinx S3 Starterkit, how hot it is supposed to be?
122001: 07/07/17: Pablo: Unisim versus Virtex2 Xilinx Library
122003: 07/07/17: Marco Albero: Sending large amount of data with lwIP...
122010: 07/07/17: fazulu deen: BD
122011: 07/07/17: Symon: Re: BD
122012: 07/07/17: John_H: Re: BD
122092: 07/07/19: RCIngham: Re: BD
122102: 07/07/19: John_H: Re: BD
122083: 07/07/18: fazulu deen: Re: BD
122013: 07/07/17: Peter Wallace: XC9572XL bus hold - Cant be disabled
122021: 07/07/17: Uwe Bonnes: Re: XC9572XL bus hold - Cant be disabled
122028: 07/07/17: PeteS: Re: XC9572XL bus hold - Cant be disabled
122014: 07/07/17: <dorama2@gmail.com>: Actel. Libero. Synplify
122016: 07/07/17: John_H: Re: Actel. Libero. Synplify
122017: 07/07/17: Symon: Re: Actel. Libero. Synplify
122108: 07/07/19: merche: Re: Actel. Libero. Synplify
122024: 07/07/17: damc4: 8B/10B decoding after serial transmission problem?
122073: 07/07/18: Gabor: Re: 8B/10B decoding after serial transmission problem?
122080: 07/07/18: Colin Hankins: Re: 8B/10B decoding after serial transmission problem?
122029: 07/07/17: Pete Fraser: Generating video noise.
122030: 07/07/18: Rob: Re: Generating video noise.
122033: 07/07/17: Eric Smith: Re: Generating video noise.
122039: 07/07/18: Mark McDougall: Re: Generating video noise.
122077: 07/07/18: Eric Smith: Re: Generating video noise.
122048: 07/07/18: HT-Lab: Re: Generating video noise.
122153: 07/07/20: Pete Fraser: Re: Generating video noise.
122046: 07/07/18: Icky Thwacket: Re: Generating video noise.
122047: 07/07/18: Icky Thwacket: Re: Generating video noise.
122065: 07/07/18: Kevin Neilson: Re: Generating video noise.
122042: 07/07/18: fpgabuilder: DDR SDRAM in extended military applications
122043: 07/07/17: Ssa: How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?
122123: 07/07/19: Antti: Re: How do I use Lattice Mico32's debug-engine on a non-Lattice FPGA?
122045: 07/07/18: merche: Actel. Libero. Synplify: "unbound component..."
122054: 07/07/18: commone: Can multiple Ferrite Beads be used to connect ...?
122055: 07/07/18: austin: Re: Can multiple Ferrite Beads be used to connect ...?
122058: 07/07/18: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122084: 07/07/19: commone: Re: Can multiple Ferrite Beads be used to connect ...?
122091: 07/07/19: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122096: 07/07/19: commone: Re: Can multiple Ferrite Beads be used to connect ...?
122098: 07/07/19: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122103: 07/07/19: John_H: Re: Can multiple Ferrite Beads be used to connect ...?
122111: 07/07/19: commone: Re: Can multiple Ferrite Beads be used to connect ...?
122114: 07/07/19: John_H: Re: Can multiple Ferrite Beads be used to connect ...?
122107: 07/07/19: commone: Re: Can multiple Ferrite Beads be used to connect ...?
122110: 07/07/19: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122117: 07/07/19: commone: Re: Can multiple Ferrite Beads be used to connect ...?
122118: 07/07/19: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122121: 07/07/19: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122139: 07/07/20: RCIngham: Re: Can multiple Ferrite Beads be used to connect ...?
122158: 07/07/20: commone: Re: Can multiple Ferrite Beads be used to connect ...?
122159: 07/07/21: John_H: Re: Can multiple Ferrite Beads be used to connect ...?
122162: 07/07/21: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122163: 07/07/21: PFC: Re: Can multiple Ferrite Beads be used to connect ...?
122166: 07/07/21: John_H: Re: Can multiple Ferrite Beads be used to connect ...?
122168: 07/07/21: PFC: Re: Can multiple Ferrite Beads be used to connect ...?
122175: 07/07/22: PFC: Re: Can multiple Ferrite Beads be used to connect ...?
122178: 07/07/23: commone: Re: Can multiple Ferrite Beads be used to connect ...?
122125: 07/07/19: Jon Elson: Re: Can multiple Ferrite Beads be used to connect ...?
122129: 07/07/19: MM: Re: Can multiple Ferrite Beads be used to connect ...?
122443: 07/07/27: colin: Re: Can multiple Ferrite Beads be used to connect ...?
122476: 07/07/28: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122516: 07/07/30: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122786: 07/08/07: commone: Re: Can multiple Ferrite Beads be used to connect ...?
122792: 07/08/07: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122794: 07/08/07: commone: Re: Can multiple Ferrite Beads be used to connect ...?
122795: 07/08/07: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122804: 07/08/07: commone: Re: Can multiple Ferrite Beads be used to connect ...?
122806: 07/08/07: Symon: Re: Can multiple Ferrite Beads be used to connect ...?
122814: 07/08/07: John_H: Re: Can multiple Ferrite Beads be used to connect ...?
122833: 07/08/08: commone: Re: Can multiple Ferrite Beads be used to connect ...?
122515: 07/07/30: colin: Re: Can multiple Ferrite Beads be used to connect ...?
122057: 07/07/18: <Lue.Her@gmail.com>: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122059: 07/07/18: Symon: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122061: 07/07/18: austin: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational
122068: 07/07/18: Nico Coesel: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122071: 07/07/18: Symon: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122116: 07/07/19: Nico Coesel: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122119: 07/07/19: Symon: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122079: 07/07/18: John Larkin: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122093: 07/07/19: Symon: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122099: 07/07/19: PFC: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122101: 07/07/19: Symon: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122115: 07/07/19: John Larkin: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122122: 07/07/19: Symon: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122127: 07/07/19: John Larkin: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122128: 07/07/19: Symon: Re: Bypass caps for Spartan 3, PQ208, 4-layer board... Educational Project
122062: 07/07/18: Andy: Re: 1ms delay in V5 FPGA
122082: 07/07/19: <suruchi81@gmail.com>: JTAG detection
122085: 07/07/19: <suruchi81@gmail.com>: JTAG detection
122086: 07/07/18: ekavirsrikanth@gmail.com: regarding specifying clock as internal signal in chipscope
122169: 07/07/21: vikram.pasham@gmail.com: Re: regarding specifying clock as internal signal in chipscope
122088: 07/07/19: merche: libero.actel
122090: 07/07/19: merche: modelsim Warning "VIOLATION ON D WITH RESPECT TO CLK"
122094: 07/07/19: KJ: Re: modelsim Warning "VIOLATION ON D WITH RESPECT TO CLK"
122097: 07/07/19: Göran Bilski: Re: modelsim Warning "VIOLATION ON D WITH RESPECT TO CLK"
122100: 07/07/19: John Adair: Enterpoint Web Site
122104: 07/07/19: Xilinx User: Xilinx XST 9.2i.01 - still incomplete support for always @*
122113: 07/07/19: John_H: Re: Xilinx XST 9.2i.01 - still incomplete support for always @*
122120: 07/07/19: Ben Jackson: Re: Xilinx XST 9.2i.01 - still incomplete support for always @*
122146: 07/07/20: <sharp@cadence.com>: Re: Xilinx XST 9.2i.01 - still incomplete support for always @*
122109: 07/07/19: Koustav: Interfacing the EDK based video decoder
122220: 07/07/24: Andreas Hofmann: Re: Interfacing the EDK based video decoder
122124: 07/07/19: Koustav: Using the EDK based video decoder
122126: 07/07/19: Andy Peters: Re: Can multiple Ferrite Beads be used to connect ...?
122130: 07/07/19: <dhruvakshad@gmail.com>: Library unit VPKG is not available in library UNISIM
122131: 07/07/19: Duane Clark: Re: Library unit VPKG is not available in library UNISIM
122132: 07/07/19: Guru: DDR2 vs SDR on Spartan3
122133: 07/07/19: PFC: Re: DDR2 vs SDR on Spartan3
122141: 07/07/20: PFC: Re: DDR2 vs SDR on Spartan3
122140: 07/07/20: Guru: Re: DDR2 vs SDR on Spartan3
122134: 07/07/19: Guru: SDRAM vs DDR2 on Spartan3E
122136: 07/07/20: Antti: Re: SDRAM vs DDR2 on Spartan3E
122137: 07/07/20: merche: libero.actel. i need a clock in a non global pin.
122138: 07/07/20: Alan Myler: Re: libero.actel. i need a clock in a non global pin.
122143: 07/07/20: John Oyler: Xilinx fpgas...
122144: 07/07/20: austin: Re: Xilinx fpgas...
122145: 07/07/20: MM: Re: Xilinx fpgas...
122147: 07/07/20: John Oyler: Re: Xilinx fpgas...
122148: 07/07/20: John McCaskill: Re: Xilinx fpgas...
122151: 07/07/20: PFC: Re: Xilinx fpgas...
122160: 07/07/21: <lb.edc@telenet.be>: Re: Xilinx fpgas...
122149: 07/07/20: mfgunes: Writing to bram and reading from bram with microblazer
122150: 07/07/20: Mike Treseler: Re: Writing to bram and reading from bram with microblazer
122184: 07/07/23: svenand: Re: Writing to bram and reading from bram with microblazer
122209: 07/07/24: mfgunes: Re: Writing to bram and reading from bram with microblazer
122154: 07/07/20: Eddie H: Running Virtex5 GTP at lower data rate
122155: 07/07/20: MM: Re: Running Virtex5 GTP at lower data rate
122156: 07/07/20: Eddie H: Re: Running Virtex5 GTP at lower data rate
122295: 07/07/25: Eddie H: Re: Running Virtex5 GTP at lower data rate
122161: 07/07/21: water9580@yahoo.com: how do Xilinx PCSPMA IP core detect presence of optical input?
122165: 07/07/21: Pasacco: FIFO : Synchronous WRITE, Asynchronous READ ?
122167: 07/07/21: Peter Alfke: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
122173: 07/07/22: Pasacco: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
122174: 07/07/22: Marc Randolph: Re: FIFO : Synchronous WRITE, Asynchronous READ ?
122170: 07/07/21: Aziz: watchdog timer: interrupt handler: microblaze
122204: 07/07/24: John Williams: Re: watchdog timer: interrupt handler: microblaze
122172: 07/07/22: <bart.deboeck@gmail.com>: FPGA for HPC
122198: 07/07/23: Marc Battyani: Re: FPGA for HPC
122176: 07/07/22: motty: FIFO Full logix - V4
122177: 07/07/22: Peter Alfke: Re: FIFO Full logix - V4
122183: 07/07/23: motty: Re: FIFO Full logix - V4
122180: 07/07/23: SangchulJung@gmail.com: Could you explain the procedure about system simulation?
122181: 07/07/23: Marc Randolph: Re: Running Virtex5 GTP at lower data rate
122182: 07/07/23: cpope: xilinx multichannel fir alignment
122194: 07/07/23: MM: Re: xilinx multichannel fir alignment
122205: 07/07/23: cpope: Re: xilinx multichannel fir alignment
122208: 07/07/23: cpope: Re: xilinx multichannel fir alignment
122185: 07/07/23: metiu: help: buggy IDE driver on Intel IXP425 GPIO(EXPB)
122186: 07/07/23: devices: On I2C protocol
122187: 07/07/23: Mike Lewis: Re: On I2C protocol
122196: 07/07/23: devices: Re: On I2C protocol
122188: 07/07/23: John_H: Re: On I2C protocol
122195: 07/07/23: devices: Re: On I2C protocol
122201: 07/07/24: Jim Granville: Re: On I2C protocol
122218: 07/07/24: devices: Re: On I2C protocol
122228: 07/07/24: John_H: Re: On I2C protocol
122240: 07/07/24: devices: Re: On I2C protocol
122253: 07/07/25: Jim Granville: Re: On I2C protocol
122266: 07/07/24: John_H: Re: On I2C protocol
122339: 07/07/25: John_H: Re: On I2C protocol
122217: 07/07/24: devices: Re: On I2C protocol
122197: 07/07/23: Gabor: Re: On I2C protocol
122250: 07/07/24: Gabor: Re: On I2C protocol
122321: 07/07/25: Gabor: Re: On I2C protocol
122193: 07/07/23: <robquigley@gmail.com>: IOSTANDARD LVDS_25 Error after upgrade to ISE 9.2i
122199: 07/07/23: <bgelb.mit.edu@gmail.com>: DDR2 w/ MIG on Xilinx ML501 Board
122237: 07/07/24: jacobusn@xilinx.com: Re: DDR2 w/ MIG on Xilinx ML501 Board
122261: 07/07/24: KF4KJQ: Re: DDR2 w/ MIG on Xilinx ML501 Board
122265: 07/07/24: KF4KJQ: Re: DDR2 w/ MIG on Xilinx ML501 Board
122334: 07/07/25: KF4KJQ: Re: DDR2 w/ MIG on Xilinx ML501 Board
122206: 07/07/23: Chris Carlen: VCD file doesn't show anything in GtkWave
122211: 07/07/24: Petter Gustad: Re: VCD file doesn't show anything in GtkWave
122251: 07/07/24: Chris Carlen: Re: VCD file doesn't show anything in GtkWave
122272: 07/07/24: mk: Re: VCD file doesn't show anything in GtkWave
122275: 07/07/25: Uwe Bonnes: Re: VCD file doesn't show anything in GtkWave
122378: 07/07/26: Chris Carlen: Re: VCD file doesn't show anything in GtkWave
122377: 07/07/26: Chris Carlen: Re: VCD file doesn't show anything in GtkWave
122567: 07/07/31: Chris Carlen: Re: VCD file doesn't show anything in GtkWave
122282: 07/07/25: Petter Gustad: Re: VCD file doesn't show anything in GtkWave
122403: 07/07/26: davem: Re: VCD file doesn't show anything in GtkWave
122609: 07/08/01: bybell: Re: VCD file doesn't show anything in GtkWave
122648: 07/08/02: davem: Re: VCD file doesn't show anything in GtkWave
122207: 07/07/23: austin: Re: Bizarre Xilinx configuration problem
122236: 07/07/24: austin: Re: Bizarre Xilinx configuration problem -- oops never mind
122210: 07/07/24: mfgunes: Connecting Bram LMB Controller to Microblaze
122213: 07/07/24: PFC: Re: Connecting Bram LMB Controller to Microblaze
122215: 07/07/24: mfgunes: Re: Connecting Bram LMB Controller to Microblaze
122216: 07/07/24: PFC: Re: Connecting Bram LMB Controller to Microblaze
122222: 07/07/24: mfgunes: Re: Connecting Bram LMB Controller to Microblaze
122223: 07/07/24: Andreas Hofmann: Re: Connecting Bram LMB Controller to Microblaze
122242: 07/07/24: PFC: Re: Connecting Bram LMB Controller to Microblaze
122274: 07/07/25: mfgunes: Re: Connecting Bram LMB Controller to Microblaze
122276: 07/07/25: Göran Bilski: Re: Connecting Bram LMB Controller to Microblaze
122212: 07/07/24: <lkjrsy@gmail.com>: Corgen Adder Vs DSP48 Adder in Virtex4
122224: 07/07/24: Matthew Hicks: Re: Corgen Adder Vs DSP48 Adder in Virtex4
122660: 07/08/02: Ray Andraka: Re: Corgen Adder Vs DSP48 Adder in Virtex4
122662: 07/08/02: Matthew Hicks: Re: Corgen Adder Vs DSP48 Adder in Virtex4
122214: 07/07/24: dude: ise 9.2 fatal error
122313: 07/07/25: davide: Re: ise 9.2 fatal error
122219: 07/07/24: Paul: hard_temac : mdio conflict
122238: 07/07/24: austin: Re: hard_temac : mdio conflict
122292: 07/07/25: Brian Drummond: Re: hard_temac : mdio conflict
122304: 07/07/25: austin: Re: hard_temac : mdio conflict
122652: 07/08/02: Brian Drummond: Re: hard_temac : mdio conflict
122243: 07/07/24: MM: Re: hard_temac : mdio conflict
122246: 07/07/24: Paul: Re: hard_temac : mdio conflict
122255: 07/07/24: MM: Re: hard_temac : mdio conflict
122260: 07/07/24: Paul: Re: hard_temac : mdio conflict
122302: 07/07/25: Paul: Re: hard_temac : mdio conflict
122221: 07/07/24: Thomas Reinemann: Arming the Chipscope Pro ILA
122225: 07/07/24: Matthew Hicks: Re: Arming the Chipscope Pro ILA
122227: 07/07/24: <SKatsyuba@gmail.com>: Re: Arming the Chipscope Pro ILA
122232: 07/07/24: Thomas Reinemann: Re: Arming the Chipscope Pro ILA
122226: 07/07/24: skyworld: 3 input adder in Spartan 3E
122229: 07/07/24: Matthew Hicks: Re: 3 input adder in Spartan 3E
122230: 07/07/24: John_H: Re: 3 input adder in Spartan 3E
122239: 07/07/24: John_H: Re: 3 input adder in Spartan 3E
122241: 07/07/24: Symon: Re: 3 input adder in Spartan 3E
122231: 07/07/24: skyworld: Re: 3 input adder in Spartan 3E
122234: 07/07/24: Matthew Hicks: Re: 3 input adder in Spartan 3E
122244: 07/07/24: Peter Alfke: Re: 3 input adder in Spartan 3E
122245: 07/07/24: Peter Alfke: Re: 3 input adder in Spartan 3E
122249: 07/07/24: Uwe Bonnes: Re: 3 input adder in Spartan 3E
122256: 07/07/24: Dave Pollum: Re: 3 input adder in Spartan 3E
122258: 07/07/24: Matthew Hicks: Re: 3 input adder in Spartan 3E
122311: 07/07/25: John_H: Re: 3 input adder in Spartan 3E
122268: 07/07/24: Peter Alfke: Re: 3 input adder in Spartan 3E
122306: 07/07/25: skyworld: Re: 3 input adder in Spartan 3E
125578: 07/10/29: MGT78000: Re: 3 input adder in Spartan 3E
122233: 07/07/24: Philip Potter: Spurious NULs using uartlite
122235: 07/07/24: <spgoldman@gmail.com>: Aldec ActiveHDL vs. ModelSim
122661: 07/08/02: Ray Andraka: Re: Aldec ActiveHDL vs. ModelSim
122247: 07/07/24: Eric Smith: tiny Spartan 3 module?
122248: 07/07/24: Symon: Re: tiny Spartan 3 module?
122267: 07/07/24: Eric Smith: Re: tiny Spartan 3 module?
122322: 07/07/25: <pbFJKD@ludd.invalid>: Re: tiny Spartan 3 module?
122269: 07/07/24: Mike Harrison: Re: tiny Spartan 3 module?
122271: 07/07/24: Eric Smith: Re: tiny Spartan 3 module?
122273: 07/07/25: Ulrich Bangert: Re: tiny Spartan 3 module?
122277: 07/07/25: Uwe Bonnes: Re: tiny Spartan 3 module?
122252: 07/07/24: Andrea05: Xint64 ?
122254: 07/07/24: Matthew Hicks: Re: Xint64 ?
122263: 07/07/24: Eric Smith: Re: Xint64 ?
122281: 07/07/25: <jetmarc@hotmail.com>: Re: Xint64 ?
122557: 07/07/31: Franz Hollerer: Re: Xint64 ?
122318: 07/07/25: Andrea05: Re: Xint64 ?
122257: 07/07/24: Stef: Altera or Xilinx
122259: 07/07/24: Matthew Hicks: Re: Altera or Xilinx
122262: 07/07/24: Stef: Re: Altera or Xilinx
122264: 07/07/24: Eric Smith: Re: Altera or Xilinx
122270: 07/07/24: Mike Treseler: Re: Altera or Xilinx
122280: 07/07/25: Nico Coesel: Re: Altera or Xilinx
122298: 07/07/25: Mike Treseler: Re: Altera or Xilinx
122300: 07/07/25: Dave Pollum: Re: Altera or Xilinx
122324: 07/07/25: <pbFJKD@ludd.invalid>: Re: Altera or Xilinx
122328: 07/07/25: Petter Gustad: Re: Altera or Xilinx
122332: 07/07/25: Mike Treseler: Re: Altera or Xilinx
122341: 07/07/26: Petter Gustad: Re: Altera or Xilinx
122335: 07/07/25: Gabor: Re: Altera or Xilinx
122338: 07/07/25: Stef: Re: Altera or Xilinx
122343: 07/07/25: Mike Treseler: Re: Altera or Xilinx
122347: 07/07/26: Jim Granville: Re: Altera or Xilinx
122363: 07/07/26: Stef: Re: Altera or Xilinx
122369: 07/07/26: Richard Klingler: Re: Altera or Xilinx
122353: 07/07/26: John_H: Re: Altera or Xilinx
122356: 07/07/26: Rob: Re: Altera or Xilinx
122696: 07/08/03: Ray Andraka: Re: Altera or Xilinx
122365: 07/07/26: Stef: Re: Altera or Xilinx
122646: 07/08/02: Stef: Re: Altera or Xilinx
122368: 07/07/26: Nial Stewart: Re: Altera or Xilinx
122370: 07/07/26: Stef: Re: Altera or Xilinx
122420: 07/07/27: Stef: Re: Altera or Xilinx
122349: 07/07/25: Peter Alfke: Re: Altera or Xilinx
122357: 07/07/25: Peter Alfke: Re: Altera or Xilinx
122361: 07/07/26: Tommy Thorn: Re: Altera or Xilinx
122410: 07/07/27: Karl: Re: Altera or Xilinx
122438: 07/07/27: dimtsios@ix.netcom.com: Re: Altera or Xilinx
122642: 07/08/02: Paul Leventis: Re: Altera or Xilinx
122645: 07/08/01: Peter Alfke: Re: Altera or Xilinx
122669: 07/08/02: <FBergemann@web.de>: Re: Altera or Xilinx
122673: 07/08/02: Wei Wang: Re: Altera or Xilinx
122700: 07/08/03: <fpga_toys@yahoo.com>: Re: Altera or Xilinx
122278: 07/07/25: colin: pci express pinout
122290: 07/07/25: Evan Lavelle: Re: pci express pinout
122359: 07/07/26: Ben Jackson: Re: pci express pinout
122296: 07/07/25: colin: Re: pci express pinout
122279: 07/07/25: raphfrk: verilog parser question about `defines
122291: 07/07/25: Evan Lavelle: Re: verilog parser question about `defines
122376: 07/07/26: Gabor: Re: verilog parser question about `defines
122582: 07/07/31: raphfrk: Re: verilog parser question about `defines
122283: 07/07/25: <Tonico>: Beginners question
122285: 07/07/25: PFC: Re: Beginners question
122288: 07/07/25: <Tonico>: Re: Beginners question
122303: 07/07/25: <Tonico>: Re: Beginners question
122307: 07/07/25: <Tonico>: Re: Beginners question
122308: 07/07/25: <Tonico>: Re: Beginners question
122289: 07/07/25: <randomdude@gmail.com>: Re: Beginners question
122293: 07/07/25: John_H: Re: Beginners question
122301: 07/07/25: <Tonico>: Re: Beginners question
122299: 07/07/25: Dave Pollum: Re: Beginners question
122309: 07/07/25: <Tonico>: Re: Beginners question
122312: 07/07/25: PFC: Re: Beginners question
122315: 07/07/25: <Tonico>: Re: Beginners question
122336: 07/07/25: Jon Elson: Re: Beginners question
122344: 07/07/25: John_H: Re: Beginners question
122455: 07/07/27: <tonico>: Re: Beginners question
122483: 07/07/28: <tonico>: Re: Beginners question
122284: 07/07/25: mfgunes: ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm
122286: 07/07/25: mfgunes: ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm
122500: 07/07/29: Guy_FPGA: Re: ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm
122513: 07/07/30: mfgunes: Re: ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm
122514: 07/07/30: mfgunes: Re: ERROR:NgdBuild:927 - Failed to process BMM file edkBmmFile.bmm
122287: 07/07/25: awa: PC104+ communication with FPGA using Xilinx IPCore
122317: 07/07/25: John Adair: Re: PC104+ communication with FPGA using Xilinx IPCore
122350: 07/07/25: awa: Re: PC104+ communication with FPGA using Xilinx IPCore
122294: 07/07/25: <janbeck@gmail.com>: Virtex-5 and powerpc
122297: 07/07/25: Antti: Re: Virtex-5 and powerpc
122305: 07/07/25: austin: Re: Virtex-5 and powerpc...its alive....
122316: 07/07/25: austin: Re: Virtex-5 and powerpc...its alive....
122326: 07/07/25: Sean Durkin: Re: Virtex-5 and powerpc...its alive....
122314: 07/07/25: Antti: Re: Virtex-5 and powerpc...its alive....
122320: 07/07/25: Antti: Re: Virtex-5 and powerpc...its alive....
122319: 07/07/25: John Adair: Re: tiny Spartan 3 module?
122323: 07/07/25: <Tonico>: Documentation/leds/simulation
122333: 07/07/25: Peter Alfke: Re: Documentation/leds/simulation
122340: 07/07/26: Jim Granville: Re: Documentation/leds/simulation
122325: 07/07/25: John Oyler: Anyone know any good vhdl ethernet tutorials?
122345: 07/07/26: PFC: Re: Anyone know any good vhdl ethernet tutorials?
122373: 07/07/26: John Oyler: Re: Anyone know any good vhdl ethernet tutorials?
122413: 07/07/27: Andreas Ehliar: Re: Anyone know any good vhdl ethernet tutorials?
122327: 07/07/25: JD Newcomb: EDK Microblaze project without OPB?
122330: 07/07/25: Siva Velusamy: Re: EDK Microblaze project without OPB?
122337: 07/07/25: morphiend: Re: EDK Microblaze project without OPB?
122329: 07/07/25: Brad Smallridge: Xilinx VHDL multidimensional array synthesis
122331: 07/07/25: Mike Treseler: Re: Xilinx VHDL multidimensional array synthesis
122390: 07/07/26: Brad Smallridge: Re: Xilinx VHDL multidimensional array synthesis
122405: 07/07/26: Brad Smallridge: Re: Xilinx VHDL multidimensional array synthesis
122417: 07/07/27: Martin Thompson: Re: Xilinx VHDL multidimensional array synthesis
122532: 07/07/30: Mike Treseler: Re: Xilinx VHDL multidimensional array synthesis
122342: 07/07/25: Eddie H: Timing simulation
122346: 07/07/25: Mike Treseler: Re: Timing simulation
122348: 07/07/25: Eddie H: Re: Timing simulation
122354: 07/07/25: Mike Treseler: Re: Timing simulation
122358: 07/07/25: Eddie H: Re: Timing simulation
122404: 07/07/26: MM: Re: Timing simulation
122429: 07/07/27: Eddie H: Re: Timing simulation
122511: 07/07/29: Mike Treseler: Re: Timing simulation
122351: 07/07/25: <bob.zigon@gmail.com>: Why is Xilinx XPS 8.2i so slow?
122355: 07/07/25: Siva Velusamy: Re: Why is Xilinx XPS 8.2i so slow?
122372: 07/07/26: morphiend: Re: Why is Xilinx XPS 8.2i so slow?
122352: 07/07/25: X.Y.: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122395: 07/07/26: Ben Twijnstra: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122396: 07/07/26: Subroto Datta: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122411: 07/07/27: X.Y.: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122470: 07/07/27: Subroto Datta: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122521: 07/07/30: X.Y.: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122539: 07/07/30: Subroto Datta: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122543: 07/07/31: X.Y.: Re: Question about Bottom-Up Incremental Compilation Methodology in Quartus II
122360: 07/07/26: swamy_digital: XMD crashes on EDK 9.1i
122374: 07/07/26: morphiend: Re: XMD crashes on EDK 9.1i
122362: 07/07/26: Sylvain Munaut: Xilinx, converting ncd back to edif
122364: 07/07/26: Petter Gustad: Re: Xilinx, converting ncd back to edif
122398: 07/07/26: Sylvain Munaut: Re: Xilinx, converting ncd back to edif
122394: 07/07/26: Kevin Neilson: Re: Xilinx, converting ncd back to edif
122397: 07/07/26: Sylvain Munaut: Re: Xilinx, converting ncd back to edif
122415: 07/07/27: Markus: Re: Xilinx, converting ncd back to edif
122452: 07/07/27: Kevin Neilson: Re: Xilinx, converting ncd back to edif
122366: 07/07/26: Fabian Schulte: ICAP in Virtex 4
122371: 07/07/26: archana: Programing Vertex 4 FPGA by PIC
122375: 07/07/26: Gabor: Re: Programing Vertex 4 FPGA by PIC
122379: 07/07/26: Joe: LogicSim 3.1 Verilog Simulator Released!
122380: 07/07/26: <michel.talon@gmail.com>: Problem with X_FF primitive acting as a latch instead of a fliflop
122382: 07/07/26: Peter Alfke: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122399: 07/07/27: Jim Granville: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122383: 07/07/26: <michel.talon@gmail.com>: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122384: 07/07/26: John_H: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122385: 07/07/26: <michel.talon@gmail.com>: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122388: 07/07/26: PFC: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122389: 07/07/26: Peter Alfke: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122418: 07/07/27: Sylvain Munaut: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122419: 07/07/27: <michel.talon@gmail.com>: Re: Problem with X_FF primitive acting as a latch instead of a fliflop
122381: 07/07/26: Paul: plb_temac with lwip and sgdma
122386: 07/07/26: <markmcmahon@hotmail.com>: Is my microblaze cache functioning?
122387: 07/07/26: hurleybp: Re: Is my microblaze cache functioning?
122391: 07/07/26: Markus Fras: DCM with Xilinx Spartan 3E and Precision
122392: 07/07/26: John_H: Re: DCM with Xilinx Spartan 3E and Precision
122393: 07/07/26: Sean Durkin: Re: DCM with Xilinx Spartan 3E and Precision
122416: 07/07/27: Markus Fras: Re: DCM with Xilinx Spartan 3E and Precision
122400: 07/07/26: <jjohnson@cs.ucf.edu>: Best CPU platform(s) for FPGA synthesis
122402: 07/07/26: <sharp@cadence.com>: Re: Best CPU platform(s) for FPGA synthesis
122444: 07/07/27: Kai Harrekilde-Petersen: Re: Best CPU platform(s) for FPGA synthesis
122458: 07/07/27: Kai Harrekilde-Petersen: Re: Best CPU platform(s) for FPGA synthesis
122459: 07/07/27: Kai Harrekilde-Petersen: Re: Best CPU platform(s) for FPGA synthesis
122488: 07/07/28: Andreas Hofmann: Re: Best CPU platform(s) for FPGA synthesis
122501: 07/07/29: PFC: Re: Best CPU platform(s) for FPGA synthesis
122509: 07/07/30: Matthieu: Re: Best CPU platform(s) for FPGA synthesis
122445: 07/07/27: Eric Smith: Re: Best CPU platform(s) for FPGA synthesis
122585: 07/08/01: Ioiod: Re: Best CPU platform(s) for FPGA synthesis
122584: 07/08/01: Ioiod: Re: Best CPU platform(s) for FPGA synthesis
122633: 07/08/01: glen herrmannsfeldt: Re: Best CPU platform(s) for FPGA synthesis
122435: 07/07/27: Jon Beniston: Re: Best CPU platform(s) for FPGA synthesis
122436: 07/07/27: Nial Stewart: Re: Best CPU platform(s) for FPGA synthesis
122437: 07/07/27: Frank Buss: Re: Best CPU platform(s) for FPGA synthesis
122674: 07/08/02: <steve.lass@xilinx.com>: Re: Best CPU platform(s) for FPGA synthesis
122681: 07/08/02: MM: Re: Best CPU platform(s) for FPGA synthesis
122682: 07/08/02: <steve.lass@xilinx.com>: Re: Best CPU platform(s) for FPGA synthesis
122683: 07/08/02: Eric Smith: Re: Best CPU platform(s) for FPGA synthesis
122687: 07/08/03: MM: Re: Best CPU platform(s) for FPGA synthesis
122695: 07/08/03: MM: Re: Best CPU platform(s) for FPGA synthesis
122698: 07/08/03: <steve.lass@xilinx.com>: Re: Best CPU platform(s) for FPGA synthesis
122441: 07/07/27: Patrick Dubois: Re: Best CPU platform(s) for FPGA synthesis
122479: 07/07/28: PeteS: Re: Best CPU platform(s) for FPGA synthesis
122685: 07/08/03: Andreas Ehliar: Re: Best CPU platform(s) for FPGA synthesis
122447: 07/07/27: <jjohnson@cs.ucf.edu>: Re: Best CPU platform(s) for FPGA synthesis
122448: 07/07/27: Jon Beniston: Re: Best CPU platform(s) for FPGA synthesis
122477: 07/07/28: comp.arch.fpga: Re: Best CPU platform(s) for FPGA synthesis
122499: 07/07/29: comp.arch.fpga: Re: Best CPU platform(s) for FPGA synthesis
122637: 07/08/02: Paul Leventis: Re: Best CPU platform(s) for FPGA synthesis
122638: 07/08/02: Paul Leventis: Re: Best CPU platform(s) for FPGA synthesis
122639: 07/08/02: Paul Leventis: Re: Best CPU platform(s) for FPGA synthesis
122649: 07/08/02: Jon Beniston: Re: Best CPU platform(s) for FPGA synthesis
122668: 07/08/02: <jjohnson@cs.ucf.edu>: Re: Best CPU platform(s) for FPGA synthesis
122670: 07/08/02: Wei Wang: Re: Best CPU platform(s) for FPGA synthesis
122671: 07/08/02: Wei Wang: Re: Best CPU platform(s) for FPGA synthesis
122672: 07/08/02: Wei Wang: Re: Best CPU platform(s) for FPGA synthesis
122690: 07/08/03: Wei Wang: Re: Best CPU platform(s) for FPGA synthesis
122694: 07/08/03: Patrick Dubois: Re: Best CPU platform(s) for FPGA synthesis
122406: 07/07/26: luu: why my usb cable can established,but can't download??? xilinx
122475: 07/07/28: svenand: Re: why my usb cable can established,but can't download??? xilinx
122407: 07/07/27: Akhil: X values in ASIC
122433: 07/07/27: Mike Lewis: Re: X values in ASIC
122440: 07/07/27: Petter Gustad: Re: X values in ASIC
122561: 07/07/31: Colin Paul Gloster: Re: X values in ASIC
122408: 07/07/27: Akhil: MS 6.2 code coverage report
122412: 07/07/27: Adam Megacz: completely open source fpga toolchain
122422: 07/07/27: Philipp Klaus Krause: Re: completely open source fpga toolchain
122517: 07/07/30: Philipp Klaus Krause: Re: completely open source fpga toolchain
122503: 07/07/29: <fpga_toys@yahoo.com>: Re: completely open source fpga toolchain
122504: 07/07/29: <fpga_toys@yahoo.com>: Re: completely open source fpga toolchain
122518: 07/07/30: Antti: Re: completely open source fpga toolchain
122529: 07/07/30: Adam Megacz: Re: completely open source fpga toolchain
122565: 07/07/31: <john@griessen.com>: Re: completely open source fpga toolchain
122608: 07/08/01: Totally_Lost: Re: completely open source fpga toolchain
122414: 07/07/27: kil: regarding the post PnR timing simulation.....
122421: 07/07/27: Slawek: Re: regarding the post PnR timing simulation.....
122425: 07/07/27: Steve: Re: regarding the post PnR timing simulation.....
122424: 07/07/27: kil: Re: regarding the post PnR timing simulation.....
122423: 07/07/27: fazulu deen: doubts
122426: 07/07/27: Dale: Can Xilinx and Altera be on the same JTAG chain for programming?
122428: 07/07/27: Antti: Re: Can Xilinx and Altera be on the same JTAG chain for programming?
122427: 07/07/27: <pbFJKD@ludd.invalid>: Xilinx XC3S400-4PQ208C pin name files?
122430: 07/07/27: <pbFJKD@ludd.invalid>: Re: Xilinx XC3S400-4PQ208C pin name files?
122432: 07/07/27: PFC: Re: Xilinx XC3S400-4PQ208C pin name files?
122431: 07/07/27: PFC: Re: Xilinx XC3S400-4PQ208C pin name files?
122434: 07/07/27: Aaron Chen: V5 Differential Select I/O
122439: 07/07/27: austin: Re: V5 Differential Select I/O
122442: 07/07/27: <tonico>: Question about GSR?
122450: 07/07/27: austin: Re: Question about GSR?
122453: 07/07/27: John_H: Re: Question about GSR?
122456: 07/07/27: austin: Re: Question about GSR?
122460: 07/07/27: John_H: Re: Question about GSR?
122465: 07/07/27: austin: Re: Question about GSR?
122464: 07/07/27: John_H: Re: Question about GSR?
122466: 07/07/27: John_H: Re: Question about GSR?
122468: 07/07/27: austin: Re: Question about GSR?
122467: 07/07/27: austin: Re: Question about GSR?
122469: 07/07/27: John_H: Re: Question about GSR?
122471: 07/07/27: austin: Re: Question about GSR?
122473: 07/07/28: John Retta: Re: Question about GSR?
122454: 07/07/27: Dale: Can Altera and Xilinx Done signals be tied together? Has anyone done it?
122457: 07/07/27: austin: Re: Can Altera and Xilinx Done signals be tied together? Has anyone
122462: 07/07/27: <bgelb.mit.edu@gmail.com>: Xilinx MIG DDR2 initialization problems
123178: 07/08/18: Carson He: Re: Xilinx MIG DDR2 initialization problems
122463: 07/07/27: <bgelb.mit.edu@gmail.com>: Xilinx MIG DDR2 initialization problems
122472: 07/07/27: <jonpry@gmail.com>: spartan-3e spi problems
122484: 07/07/28: Antti: Re: spartan-3e spi problems
122491: 07/07/29: <jonpry@gmail.com>: Re: spartan-3e spi problems
122494: 07/07/29: Antti: Re: spartan-3e spi problems
122474: 07/07/28: ram: query in byte blaster/signal topic logic analyser
122478: 07/07/28: Andy Botterill: dual port ram
122480: 07/07/28: Symon: Re: dual port ram
122481: 07/07/28: Andy Botterill: Re: dual port ram
122482: 07/07/28: Jonathan Bromley: Re: dual port ram
122486: 07/07/28: Andy Botterill: Re: dual port ram
122487: 07/07/28: austin: Re: dual port ram
122489: 07/07/28: Ben Jackson: Re: dual port ram
122496: 07/07/29: Andy Botterill: Re: dual port ram
122497: 07/07/29: Jonathan Bromley: Re: dual port ram
122502: 07/07/29: Andy Botterill: Re: dual port ram
122505: 07/07/29: Ben Jackson: Re: dual port ram
122485: 07/07/28: charon: EDK 9.1.02i warnings flood
122495: 07/07/29: Antti: Re: EDK 9.1.02i warnings flood
122498: 07/07/29: charon: Re: EDK 9.1.02i warnings flood
123180: 07/08/18: JD Newcomb: Re: EDK 9.1.02i warnings flood
122490: 07/07/28: Neil Steiner: Restricting XST parameter widths from .mpd files?
122520: 07/07/30: Gabor: Re: Restricting XST parameter widths from .mpd files?
122537: 07/07/30: Neil Steiner: Re: Restricting XST parameter widths from .mpd files?
122492: 07/07/28: Peter Alfke: Re: dual port ram
122493: 07/07/29: Antti: Xilinx something happening with Spartan-3?
122523: 07/07/30: austin: Re: Website
122531: 07/07/30: austin: Re: Website
122525: 07/07/30: Antti: Re: Website
122506: 07/07/29: <ryufrank@hotmail.com>: Simple UDP packets forwarding using lwip sockets
122507: 07/07/29: icegray: Microblaze Interrupt Handler
122512: 07/07/30: Antti: Re: Microblaze Interrupt Handler
122519: 07/07/30: icegray: Re: Microblaze Interrupt Handler
122508: 07/07/29: Han Phan: Odelay usage in virtex5
122510: 07/07/29: motty: Re: Odelay usage in virtex5
122522: 07/07/30: Han Phan: Re: Odelay usage in virtex5
122542: 07/07/30: motty: Re: Odelay usage in virtex5
122524: 07/07/30: MM: Question on using RLOC_RANGE
122528: 07/07/30: austin: Re: Question on using RLOC_RANGE
122533: 07/07/30: MM: Re: Question on using RLOC_RANGE
122534: 07/07/30: austin: Re: Question on using RLOC_RANGE
122535: 07/07/30: austin: Re: Question on using RLOC_RANGE
122536: 07/07/30: MM: Re: Question on using RLOC_RANGE
122540: 07/07/30: austin: Re: Question on using RLOC_RANGE
122526: 07/07/30: sriman: Help on TRB_DC2 Camera module interface
122530: 07/07/30: devices: Re: Help on TRB_DC2 Camera module interface
122541: 07/07/30: devices: Re: Help on TRB_DC2 Camera module interface
122538: 07/07/30: sriman: Re: Help on TRB_DC2 Camera module interface
122527: 07/07/30: sriman: Help on TRB_DC2 Camera module interface
122544: 07/07/30: <bob.zigon@gmail.com>: Looking for 2 simple Xilinx examples of FSL
122545: 07/07/31: Antti: Re: Looking for 2 simple Xilinx examples of FSL
122551: 07/07/31: <jetmarc@hotmail.com>: Re: Looking for 2 simple Xilinx examples of FSL
122554: 07/07/31: Antti: Re: Looking for 2 simple Xilinx examples of FSL
122546: 07/07/31: jega: Clarifications Regarding FlexRay Stand Alone Cotroller Interfacing With PIC Microcontroller
122547: 07/07/31: Philipp Klaus Krause: Looking for PLD with embedded memory
122548: 07/07/31: Philipp Klaus Krause: Re: Looking for PLD with embedded memory
122556: 07/07/31: Philipp Klaus Krause: Re: Looking for PLD with embedded memory
122558: 07/07/31: Jim Granville: Re: Looking for PLD with embedded memory
122559: 07/07/31: Philipp Klaus Krause: Re: Looking for PLD with embedded memory
122581: 07/08/01: Jim Granville: Re: Looking for PLD with embedded memory
122626: 07/08/01: Evan Lavelle: Re: Looking for PLD with embedded memory
122692: 07/08/03: Philipp Klaus Krause: Re: Looking for PLD with embedded memory
122703: 07/08/03: Eric Smith: Re: Looking for PLD with embedded memory
122550: 07/07/31: <jetmarc@hotmail.com>: Re: Looking for PLD with embedded memory
122553: 07/07/31: Petter Gustad: Re: Looking for PLD with embedded memory
122555: 07/07/31: Antti: Re: Looking for PLD with embedded memory
122578: 07/07/31: Eric Smith: Re: Looking for PLD with embedded memory
122549: 07/07/31: Roger: V5 compared to V2P
122552: 07/07/31: Symon: Re: V5 compared to V2P
122629: 07/08/01: austin: Re: V5 compared to V2P
122560: 07/07/31: Sylvain Munaut: Xilinx/ModelSim bug ? Clocking headache ...
122562: 07/07/31: Andy: Re: Xilinx/ModelSim bug ? Clocking headache ...
122563: 07/07/31: Sylvain Munaut: Re: Xilinx/ModelSim bug ? Clocking headache ...
122569: 07/07/31: Mike Treseler: Re: Xilinx/ModelSim bug ? Clocking headache ...
122572: 07/07/31: Sylvain Munaut: Re: Xilinx/ModelSim bug ? Clocking headache ...
122628: 07/08/01: Georg Acher: Re: Xilinx/ModelSim bug ? Clocking headache ...
122632: 07/08/01: Mike Treseler: Re: Xilinx/ModelSim bug ? Clocking headache ...
122684: 07/08/02: Mike Treseler: Re: Xilinx/ModelSim bug ? Clocking headache ...
122568: 07/07/31: Sylvain Munaut: Re: Xilinx/ModelSim bug ? Clocking headache ...
122574: 07/07/31: Jonathan Bromley: Re: Xilinx/ModelSim bug ? Clocking headache ...
122589: 07/08/01: Sylvain Munaut: Re: Xilinx/ModelSim bug ? Clocking headache ...
122619: 07/08/01: Mike Treseler: Re: Xilinx/ModelSim bug ? Clocking headache ...
122654: 07/08/02: Brian Drummond: Re: Xilinx/ModelSim bug ? Clocking headache ...
122627: 07/08/01: Andy: Re: Xilinx/ModelSim bug ? Clocking headache ...
122659: 07/08/02: Erik Widding: Re: Xilinx/ModelSim bug ? Clocking headache ...
122564: 07/07/31: <sego@hrz.tu-chemnitz.de>: DDR Simulation Model
122570: 07/07/31: B. Joshua Rosen: Re: DDR Simulation Model
122599: 07/08/01: PFC: Re: DDR Simulation Model
122600: 07/08/01: PFC: Re: DDR Simulation Model
122604: 07/08/01: Brian Drummond: Re: DDR Simulation Model
122655: 07/08/02: Brian Drummond: Re: DDR Simulation Model
122630: 07/08/01: Kevin Neilson: Re: DDR Simulation Model
122577: 07/07/31: Weng Tianxiang: Re: DDR Simulation Model
122592: 07/08/01: Sebastian Goller: Re: DDR Simulation Model
122594: 07/08/01: Sebastian Goller: Re: DDR Simulation Model
122595: 07/08/01: Sebastian Goller: Re: DDR Simulation Model
122605: 07/08/01: Sebastian Goller: Re: DDR Simulation Model
122606: 07/08/01: Sebastian Goller: Re: DDR Simulation Model
123108: 07/08/16: Sebastian Goller: Re: DDR Simulation Model
122566: 07/07/31: Nir Dahan: ASIC Digital Design Blog
122576: 07/07/31: Weng Tianxiang: Re: ASIC Digital Design Blog
122580: 07/07/31: Nir Dahan: Re: ASIC Digital Design Blog
122590: 07/08/01: <michel.talon@gmail.com>: Re: ASIC Digital Design Blog
122616: 07/08/01: Kunal: Re: ASIC Digital Design Blog
122618: 07/08/01: Tommy Thorn: Re: ASIC Digital Design Blog
122621: 07/08/01: Nir Dahan: Re: ASIC Digital Design Blog
122571: 07/07/31: <bob.zigon@gmail.com>: Upgrading from EDK 8.1 to EDK 9.1i
122573: 07/07/31: Antti: Re: Upgrading from EDK 8.1 to EDK 9.1i
122579: 07/07/31: Eric Smith: Re: Upgrading from EDK 8.1 to EDK 9.1i
122575: 07/07/31: sriman: regarding RTOS in NIOS II
122631: 07/08/02: PretzelX: Re: regarding RTOS in NIOS II
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