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On Jul 26, 7:40 am, archana <ramaarch...@gmail.com> wrote: > Hi all > > I am trying to program the Vertex 4 FPGA (XC4VFX100) in the slave > serial mode using a PIC. > > I am facing a problem while doing the programming. > > when I am sending the first configuration bit on the din pin of the > FPGA , the prog_b & the init_b pins which were otherwise high are > going low. > > can anybody suggest me about the problem and any solution for this. > > thanks & regards > archana The prog_b pin should not be driven by the FPGA. If the PIC is the only other thing connected to the net, I would suggest checking your PIC program. If the PIC is not actively driving prog_b high, you should have a pullup resistor on the net. The init_b pin will go low when prog_b is asserted low. This may just be a side-effect of the prog_b issue or you may be driving it low from the PIC. When you drive the din pin are you using a bit set/clear instruction or writing directly to the I/O port? If the latter, is the prog_b on the same port? HTH, GaborArticle: 122376
On Jul 25, 8:38 am, Evan Lavelle <nos...@nospam.com> wrote:
> On Wed, 25 Jul 2007 02:10:00 -0700, raphfrk <raph...@netscape.net>
> wrote:
>
> >I have a set of verilog files that uses `defines. The same `define is
> >applied to each file to select which code to use.
>
> >Is there a way to setup Xilinx ISE so that when processing all verilog
> >files it assumes that a certain `define has been defined ?
>
> vlogcomp has a '-d' option:
>
> evan 63 > vlogcomp
> Release - ISE Simulator Vlogcomp I.31
> Copyright (c) 1995-2006 Xilinx, Inc. All rights reserved.
> ...
> Usage: vlogcomp {options}
> ...
> -d <macro> Define <macro>; The format of the <macro>
> argument is <name>[=<val>] where <name> is
> the name of the macro, and <val> is an
> optional
> value for the macro
>
> Evan
You can also add macros in the GUI under synthesis options
(Advanced) "Verilog Macros". Use the same format for
definitions. Use a vertical bar to separate multiple entries.
Article: 122377mk wrote: > On Tue, 24 Jul 2007 13:25:33 -0700, Chris Carlen > <crcarleRemoveThis@BOGUSsandia.gov> wrote: > >>Petter Gustad wrote: >>>Chris Carlen <crcarleRemoveThis@BOGUSsandia.gov> writes: >>> >>>>Is there something wrong with my .vcd file, or Gtkwave? >>Thanks for the reply. >> >>>Did you try to: >>> >>>click on the + in the SST window >>What is the SST window? Do you mean the zoom-in? > > Let's get some layout decided. At the top left there is a window which > says "VCD loaded succesfully[12] facilities..." right? You're also > seeing a window which has a title "Signals" and the content "Time" at > this point from what you're describing. Now below "VCD loaded ..." > window and to the left of "Signals" window, you should see a window > which has SST in its title with a '+' to the left of SST string. If > you see this click on the '+' and you should see your hierarchy. If > you don't see the SST window, it's possible that your GTK+ setup is > broken and you don't the right GTK+ installed. Hi, and thanks for the reply! 1. I have the '"VCD loaded succesfully[12] facilities..."' 2. I have the '"Signals" and the content "Time"' But, >you should see a window >which has SST in its title with a '+' to the left of SST string. I don't see this! I think the conclusion is that my GTK+ might be screwed. This Suse Linux has been known to have a shoddy GNOME installation at times. So perhaps the libs are just old, or Suse tinkered with them and broke it. Thanks for the help. It isn't worth any more time at this point. I may try Windows, or may just live with the text output from the Icarus simulator (which is usable). I'll try GtkWave again once I have a chance to update Linux. -- Good day! ________________________________________ Christopher R. Carlen Principal Laser&Electronics Technologist Sandia National Laboratories CA USA crcarleRemoveThis@BOGUSsandia.gov NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.Article: 122378
Uwe Bonnes wrote: > > Another option might be Dinotrace... Wow, that looks ancient! Haven't used any raw X apps in a while. I'll give it a shot... -- Good day! ________________________________________ Christopher R. Carlen Principal Laser&Electronics Technologist Sandia National Laboratories CA USA crcarleRemoveThis@BOGUSsandia.gov NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.Article: 122379
Hi there, I'd like to announce the release of LogicSim 3.1. This is a maintenance and support release that addresses some outstanding issues that were not addressed with 3.0 including some feature enhancements and many bug fixes. In this release, we have fixed some minor bugs and memory leaks. We have also added some new features for the workspace, such as support for creating sub-folders in the file navigator to improve navigation for projects with many files. Please check out the release notes for more info. For existing customers, please receive your free upgrade here (http:// www.zeemz.com/maintenance.php), just enter your purchase time email address and an activation key will be sent to you immediately. I'd like to thank those who continue submitting bugs and feedbacks. Without them, we would not be able to improve our software. Thanks for being our valuable customers and users. You can download LogicSim 3.1 here (http://www.zeemz.com/) You can find this press release on our blog (http://www.zeemz.com/ blog/) Joe, Zeemz, Inc.Article: 122380
Hi alls,
I've a amazing problem in my virtex XC2V1000 design.
I've verilog code which normaly should generate a D flipFlop with
preload ( and it did in functional simulation):
input [7:0] reset;
input [7:0] n_set;
input [7:0] d;
input clockIn;
output [7:0] out;
reg [7:0] out_reg;
wire [7:0] out = out_reg;
wire trigSig = |(reset | ~(n_set));
always@(posedge clockIn or posedge trigSig)
begin
if(trigSig)
out_reg = ~reset;
else
out_reg = d;
end
The problem append when I use post translate simulation model ( based
on simprims ) after synthesize my design with ISE 9.1i
It seems my Flipflop has been convert to a latch : out_reg copy the d
value during clockIn high state and block it during low state.
So I verify which primitive was instantiate in the post translate
simulation model generated by ISE, and I found a X_FF which is a
flipflop... So I don't understand anything.. It looks very strange.. :-
(
For information, I simulate with Cadence NC-verilog and NC-sim and I
join simprims directory to my project to have Xilinx primitives.
If anyone could help me, because I haven't more ideas about what
append..
Thanks by advance, best regards, Michel Talon.
Article: 122381Hi, is there any documentation for using plb_temac and lwip with the DMA enabled in plb_temac ? Thank's. Paul.Article: 122382
Check the signal integrity of your clock. You may have double edges. Easy test: Add a single toggling flip-flop ( or a divide-by 4 counter) and observe its behavior. It will clearly indicate any double- triggering. Peter Alfke, from home. ================== On Jul 26, 8:09 am, michel.ta...@gmail.com wrote: > Hi alls, > > I've a amazing problem in my virtex XC2V1000 design. > > I've verilog code which normaly should generate a D flipFlop with > preload ( and it did in functional simulation): > input [7:0] reset; > input [7:0] n_set; > input [7:0] d; > input clockIn; > output [7:0] out; > > reg [7:0] out_reg; > wire [7:0] out = out_reg; > wire trigSig = |(reset | ~(n_set)); > always@(posedge clockIn or posedge trigSig) > begin > if(trigSig) > out_reg = ~reset; > else > out_reg = d; > end > > The problem append when I use post translate simulation model ( based > on simprims ) after synthesize my design with ISE 9.1i > It seems my Flipflop has been convert to a latch : out_reg copy the d > value during clockIn high state and block it during low state. > So I verify which primitive was instantiate in the post translate > simulation model generated by ISE, and I found a X_FF which is a > flipflop... So I don't understand anything.. It looks very strange.. :- > ( > > For information, I simulate with Cadence NC-verilog and NC-sim and I > join simprims directory to my project to have Xilinx primitives. > > If anyone could help me, because I haven't more ideas about what > append.. > > Thanks by advance, best regards, Michel Talon.Article: 122383
I've checked my clock on the waveform viewer and it seems good.. but I did what you say, I add a divisor on my clock, and I send divided clock to my process. ISE is running, so I'm going to see the results in ten minutes.. ( because the rest of the design is big, and it's too long to synthesize.. ) thanks On 26 juil, 17:18, Peter Alfke <al...@sbcglobal.net> wrote: > Check the signal integrity of your clock. You may have double edges. > > Easy test: Add a single toggling flip-flop ( or a divide-by 4 counter) > and observe its behavior. It will clearly indicate any double- > triggering. > Peter Alfke, from home. > ================== > On Jul 26, 8:09 am, michel.ta...@gmail.com wrote: > > > Hi alls, > > > I've a amazing problem in my virtex XC2V1000 design. > > > I've verilog code which normaly should generate a D flipFlop with > > preload ( and it did in functional simulation): > > input [7:0] reset; > > input [7:0] n_set; > > input [7:0] d; > > input clockIn; > > output [7:0] out; > > > reg [7:0] out_reg; > > wire [7:0] out = out_reg; > > wire trigSig = |(reset | ~(n_set)); > > always@(posedge clockIn or posedge trigSig) > > begin > > if(trigSig) > > out_reg = ~reset; > > else > > out_reg = d; > > end > > > The problem append when I use post translate simulation model ( based > > on simprims ) after synthesize my design with ISE 9.1i > > It seems my Flipflop has been convert to a latch : out_reg copy the d > > value during clockIn high state and block it during low state. > > So I verify which primitive was instantiate in the post translate > > simulation model generated by ISE, and I found a X_FF which is a > > flipflop... So I don't understand anything.. It looks very strange.. :- > > ( > > > For information, I simulate with Cadence NC-verilog and NC-sim and I > > join simprims directory to my project to have Xilinx primitives. > > > If anyone could help me, because I haven't more ideas about what > > append.. > > > Thanks by advance, best regards, Michel Talon.Article: 122384
Are you *certian* you're looking at the flop output in the simulation and not accidentally an internal signal? [By the way - the "I've" contraction is commonly used for verbs such as "I've checked" but I've only seen (I've... seen) the use with nouns (e.g., I've a problem) with posts from India. It's distracting whenever I see "I've a noun" constructs. You still communicate, it just takes away from your message.] <michel.talon@gmail.com> wrote in message news:1185462599.540368.277580@g4g2000hsf.googlegroups.com... > Hi alls, > > I've a amazing problem in my virtex XC2V1000 design. > > I've verilog code which normaly should generate a D flipFlop with > preload ( and it did in functional simulation): > input [7:0] reset; > input [7:0] n_set; > input [7:0] d; > input clockIn; > output [7:0] out; > > reg [7:0] out_reg; > wire [7:0] out = out_reg; > wire trigSig = |(reset | ~(n_set)); > always@(posedge clockIn or posedge trigSig) > begin > if(trigSig) > out_reg = ~reset; > else > out_reg = d; > end > > The problem append when I use post translate simulation model ( based > on simprims ) after synthesize my design with ISE 9.1i > It seems my Flipflop has been convert to a latch : out_reg copy the d > value during clockIn high state and block it during low state. > So I verify which primitive was instantiate in the post translate > simulation model generated by ISE, and I found a X_FF which is a > flipflop... So I don't understand anything.. It looks very strange.. :- > ( > > For information, I simulate with Cadence NC-verilog and NC-sim and I > join simprims directory to my project to have Xilinx primitives. > > If anyone could help me, because I haven't more ideas about what > append.. > > Thanks by advance, best regards, Michel Talon.Article: 122385
On 26 juil, 17:18, Peter Alfke <al...@sbcglobal.net> wrote: > Check the signal integrity of your clock. You may have double edges. > > Easy test: Add a single toggling flip-flop ( or a divide-by 4 counter) > and observe its behavior. It will clearly indicate any double- > triggering. > Peter Alfke, from home. > ================== You are right, by dividing my clock by 2, I divide by 2 out_reg value variations.. but I don't understand why my clock is like that, because when I look it one level up, it is fine. And I see something strange on the divided clock, it's like that : ________ __ ________________ ____ _ | |____| |_| |________| | __| | instead of the expected clock : ________________ ________________ | | ________________| divided by 2 : ________ ________ | |________| |________ There is a ratio by 2 : High state = 8x, Low state = 4x, High state = 2x, Low state = 1x.. On 26 juil, 17:56, "John_H" <newsgr...@johnhandwork.com> wrote: > Are you *certian* you're looking at the flop output in the simulation and > not accidentally an internal signal? > Yes I think, because I use the synthesis keep attribute to keep the signal name during synthesis. > [By the way - the "I've" contraction is commonly used for verbs such as > "I've checked" but I've only seen (I've... seen) the use with nouns (e.g., > I've a problem) with posts from India. It's distracting whenever I see > "I've a noun" constructs. You still communicate, it just takes away from > your message.] Thank you for the explanation, my english is not very fine... :-(Article: 122386
Hello all,
I am using a Spartan 2E 600-LC development board. When I created the
project using the BSB I did not specify the use of caches. I am now
trying to enable instruction and data caches. I did not re-open the
BSB file as I have added other periperals which I don't want to
change.
Can someone confirm the steps needed to enable the cache?
In the MHS file, I have :
PARAMETER C_USE_ICACHE = 1
PARAMETER C_CACHE_BYTE_SIZE = 1024
PARAMETER C_USE_DCACHE = 1
PARAMETER C_DCACHE_BYTE_SIZE = 2048
PARAMETER C_ICACHE_BASEADDR = 0x24000000
PARAMETER C_ICACHE_HIGHADDR = 0x25ffffff
PARAMETER C_DCACHE_BASEADDR = 0x24000000
PARAMETER C_DCACHE_HIGHADDR = 0x25ffffff
The 32MB of SDRAM starts at 0x2400000, I am using a bootloader.
In the application, I have added:
#include "mb_interface.h"
#define ICACHE_SIZE 1024
#define DCACHE_SIZE 2048
main() {
microblaze_disable_icache();
microblaze_init_icache_range(0, ICACHE_SIZE);
microblaze_enable_icache();
microblaze_disable_dcache();
microblaze_init_dcache_range(0, DCACHE_SIZE);
microblaze_enable_dcache();
In the System Assembly > Addresses view, both ICache and DCache boxes
are ticked for the SDRAM.
Using the debugger I can see that the above disable and enable
functions clear and set the ICE and DCE bits in the MSR.
The problem I am having is that the application does not seem to run
any faster.
Is there anything else I need to do to enable the cache?
What else can I do to verify that the cache is being used?
Is there some sample code which I can run as a benchmark? (something
which will show a marked speedup if the cache is functioning?).
Thanks for your help.
Mark.
Article: 122387
On Jul 26, 1:07 pm, markmcma...@hotmail.com wrote:
> Hello all,
>
> I am using a Spartan 2E 600-LC development board. When I created the
> project using the BSB I did not specify the use of caches. I am now
> trying to enable instruction and data caches. I did not re-open the
> BSB file as I have added other periperals which I don't want to
> change.
>
> Can someone confirm the steps needed to enable the cache?
>
> In the MHS file, I have :
> PARAMETER C_USE_ICACHE = 1
> PARAMETER C_CACHE_BYTE_SIZE = 1024
> PARAMETER C_USE_DCACHE = 1
> PARAMETER C_DCACHE_BYTE_SIZE = 2048
> PARAMETER C_ICACHE_BASEADDR = 0x24000000
> PARAMETER C_ICACHE_HIGHADDR = 0x25ffffff
> PARAMETER C_DCACHE_BASEADDR = 0x24000000
> PARAMETER C_DCACHE_HIGHADDR = 0x25ffffff
>
> The 32MB of SDRAM starts at 0x2400000, I am using a bootloader.
>
> In the application, I have added:
>
> #include "mb_interface.h"
> #define ICACHE_SIZE 1024
> #define DCACHE_SIZE 2048
>
> main() {
> microblaze_disable_icache();
> microblaze_init_icache_range(0, ICACHE_SIZE);
> microblaze_enable_icache();
>
> microblaze_disable_dcache();
> microblaze_init_dcache_range(0, DCACHE_SIZE);
> microblaze_enable_dcache();
>
> In the System Assembly > Addresses view, both ICache and DCache boxes
> are ticked for the SDRAM.
> Using the debugger I can see that the above disable and enable
> functions clear and set the ICE and DCE bits in the MSR.
>
> The problem I am having is that the application does not seem to run
> any faster.
>
> Is there anything else I need to do to enable the cache?
> What else can I do to verify that the cache is being used?
>
> Is there some sample code which I can run as a benchmark? (something
> which will show a marked speedup if the cache is functioning?).
>
> Thanks for your help.
> Mark.
How is your microblaze connected to your external memory? Do you a
standard OPB memory controller or do you use one of the multi-channel
memory controllers? If you answer the former, what you need is the
latter. Then, you interface your microblaze XCL (cachelink) ports
directly to the memory controller. The rationale for this strategy is
that the microblaze (at least in modern versions) is only designed to
cache over XCL.
Article: 122388> I've verilog code which normaly should generate a D flipFlop with > preload ( and it did in functional simulation): > always@(posedge clockIn or posedge trigSig) > begin > if(trigSig) > out_reg =3D ~reset; > else > out_reg =3D d; > end Replace "=3D" with "<=3D".Article: 122389
I suppose you have reflections on your clock input. Your scope may not be fast enough to see these reflections of perhaps 1 to 3 ns duration. There are several ways to solve this, depending on the internal clock distribution, depending on your willingness to change the pc-board, whether this is a one-off or a production design, etc. But when you see a single toggle flip-flop misbehaving, you know that you have to do something. Peter Alfke, Xilinx Applications On Jul 26, 9:54 am, michel.ta...@gmail.com wrote: > On 26 juil, 17:18, Peter Alfke <al...@sbcglobal.net> wrote: > > > Check the signal integrity of your clock. You may have double edges. > > > Easy test: Add a single toggling flip-flop ( or a divide-by 4 counter) > > and observe its behavior. It will clearly indicate any double- > > triggering. > > Peter Alfke, from home. > > ================== > > You are right, by dividing my clock by 2, I divide by 2 out_reg value > variations.. but I don't understand why my clock is like that, because > when I look it one level up, it is fine. And I see something strange > on the divided clock, it's like that : > ________ __ ________________ ____ _ > | |____| |_| |________| | > __| | > instead of the expected clock : > ________________ ________________ > | | > ________________| > divided by 2 : > ________ ________ > | |________| |________ > > There is a ratio by 2 : High state = 8x, Low state = 4x, High state = > 2x, Low state = 1x.. > > On 26 juil, 17:56, "John_H" <newsgr...@johnhandwork.com> wrote:> Are you *certian* you're looking at the flop output in the simulation and > > not accidentally an internal signal? > > Yes I think, because I use the synthesis keep attribute to keep the > signal name during synthesis. > > > [By the way - the "I've" contraction is commonly used for verbs such as > > "I've checked" but I've only seen (I've... seen) the use with nouns (e.g., > > I've a problem) with posts from India. It's distracting whenever I see > > "I've a noun" constructs. You still communicate, it just takes away from > > your message.] > > Thank you for the explanation, my english is not very fine... :-(Article: 122390
>> I vaguely remember reading that the synthesis >> tool will not synthesize multidimensional arrays >> into BRAM. Is this correct? > > The basic requirement to infer a bram is > a clocked process with no reset. Hmm. I do remember taking a reset out of the code. I'll have to check to see if that was before or after I flattened the 2D array. Thanks.Article: 122391
Hello everyone, I would like to use an DCM in a Xilinx Spartan 3E device. The synthesis is done with Mentor Graphics Precision. So I created a verilog file with verilog, but when I run synthesis, I get the error message: # Error: [216]: Unable to resolve reference to an Instance: DCM_SP_INST of Cell work.DCM_SP. # Error: Found unresolved black-boxes in the design, please fix the previous error messages before continuing It seems to me that Precision does not recognize Xilinx' DCM for Spartan devices. Do You have any ideas? Markus FrasArticle: 122392
Is the DCM_SP_INST something that was generated by the Xilinx Architecture Wizard? The Software Manual does not show a DCM_SP_INST primitive for the Spartan-3E. You would need to include the black box Verilog file generated by the Architecture wizard in your project. "Markus Fras" <fras@mppmu.mpg.de> wrote in message news:f8aqru$1ms8$1@gwdu112.gwdg.de... > Hello everyone, > > I would like to use an DCM in a Xilinx Spartan 3E device. The synthesis is > done with Mentor Graphics Precision. > So I created a verilog file with verilog, but when I run synthesis, I get > the error message: > > # Error: [216]: Unable to resolve reference to an Instance: DCM_SP_INST of > Cell work.DCM_SP. > # Error: Found unresolved black-boxes in the design, please fix the > previous error messages before continuing > > It seems to me that Precision does not recognize Xilinx' DCM for Spartan > devices. > > Do You have any ideas? > > Markus FrasArticle: 122393
Markus Fras wrote: > It seems to me that Precision does not recognize Xilinx' DCM for Spartan > devices. > > Do You have any ideas? I haven't worked with Spartan devices, and I don't use Verilog, but I've had problems with instantiating Xilinx primitives in VHDL without declaring them first, i.e. I get the same error message as you do when I just instantiate e.g. a BUFG out of the work library, without declaring it first. The same applies in designs where I use the PicoBlaze... in the HDL for the PicoBlaze, there are flipflops, shift registers and such instantiated without being declared first, and I could never get that synthesized with Precision at first. What I then did was add the source code for the UNISIM-library to my synthesis project (in $XILINX/vhdl/src/unisims/unisim_VCOMP.vhd). Inside this file are declarations for all Xilinx primitives, including the DSP_SP. Just including this in the synthesis fixed it for me. HTH, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 122394
Sylvain Munaut wrote: > Hello everyone, > > > I have a placed and routed .ncd file and I'd like to be able to convert it back to a simple netlist. > It doesn't contain any "secured" core, so I can freely use all the xilinx tools suite on it. But there is no "ncd2edif" ... > > I convert it to XDL then somehow parse it ... but in the xdl I have the slice configuration, which means I would have to convert it to a basic element (LUT/MUXF5/...) + interconnections first ... That's gonna be quite painful to do. > > Does someone has a better idea/tool to do the job ? > > > Thanks, > > Sylvain Presumably you have the NGD which you used to create the NCD. Then you can use NDG2EDIF.Article: 122395
Hi X.Y. > I am new to use Bottom-Up Incremental Compilation Methodology in > Quartus and I have a question about it. I have exported partition from > subproject and imported it to top-level design successfully. However, > I can import a partition for only one time. In my project, I need to > import the same partition for multiple times. Currently, Quartus uses absolute placement for imported blocks. So, every block that you import is forced to be placed onto the same location, generating the eror you descibe. At this moment, the only thing you can do is to run multiple fits for every instance into a non-overlapping LogicLock region (in order to make sure that you don't get conflicting location assignments), and import every separate result into your toplevel project to solve your problem. I do know though, that Altera is working on a solution to this issue. Best regards, BenArticle: 122396
Hi X.Y, The Incremental Compilation flow currently does not allow the imported .qxp to be "stamped" onto different instances. This is coming. One workaround is to have a different HDL file and name for each instance. Admittedly, this is not ideal but in many cases is an easy solution. (If you're making changes on the top-level file, it's painful to repeat in multiple files. But if the changes are in the HDL files beneath that entity, then it all works smoothly after the initial set-up.) One flow Iused often, mainly because it works and is easy, is the pseudo-bottom up flow. This basically involves putting partitions on the hierarchies that are in the same level as the one/s you are interested in and set them to Empty(so they have no logic, but nothing gets removed). I then work on the partitions I want with quick compiles. Then, when I get what I want, I set that partition to post- fit and either set the other partitions to Source or delete them altogether(making everything else one big partition). It's quick and easy without creating sub-projects, making sure their layout fits into the top-level, etc. Also, in Q7.1 you can export a .qxp from sub partitions, so you can always save off your results. This works with multiple instances of the same thing, since they now have different instances(and locations). What end goal are you using Incremental Compilation flow for? Are you trying to reduce compile times, are you trying to preserve performance, or something else? - Subroto Datta Altera Corp.Article: 122397
Kevin Neilson wrote:
> Sylvain Munaut wrote:
>> Hello everyone,
>>
>>
>> I have a placed and routed .ncd file and I'd like to be able to
>> convert it back to a simple netlist.
>> It doesn't contain any "secured" core, so I can freely use all the
>> xilinx tools suite on it. But there is no "ncd2edif" ...
>>
>> I convert it to XDL then somehow parse it ... but in the xdl I have
>> the slice configuration, which means I would have to convert it to a
>> basic element (LUT/MUXF5/...) + interconnections first ... That's
>> gonna be quite painful to do.
>>
>> Does someone has a better idea/tool to do the job ?
>>
>>
>> Thanks,
>>
>> Sylvain
>
> Presumably you have the NGD which you used to create the NCD. Then you
> can use NDG2EDIF.
No I don't ;)
All I have recovered is the .ncd, the .bit, and all the .ngc except one ...
I'm hoping to be able to reconstruct my missing ngc by "isolating" it from
the rest in the ngc.
I tried netgen, that gives me a vhdl (or verilog file), but parsing it
is gonna be painful as well ;)
Sylvain
Article: 122398Petter Gustad wrote: > Sylvain Munaut <tnt-at-246tNt-dot-com@youknowwhattodo.com> writes: > >> I have a placed and routed .ncd file and I'd like to be able to >> convert it back to a simple netlist. > > You can convert it to a verilog netlist with netgen, here's from one > of my older Makefiles: > > netgen -sim -aka -dir . -ofmt verilog -pcf $(CHIP).pcf -sdf_anno true -sdf_path ../../impl/2vp20/xst-compiled -w $< $@ Thanks, that's a start. Maybe by running xst on it I'll get an edif ... SylvainArticle: 122399
Peter Alfke wrote: > I suppose you have reflections on your clock input. Your scope may not > be fast enough to see these reflections of perhaps 1 to 3 ns duration. > There are several ways to solve this, depending on the internal clock > distribution, depending on your willingness to change the pc-board, > whether this is a one-off or a production design, etc. > But when you see a single toggle flip-flop misbehaving, you know that > you have to do something. > Peter Alfke, Xilinx Applications I'm not sure he is at the silicon yet - I think this is still a simulation result ? OP: > The problem append when I use post translate simulation model ( based > on simprims ) after synthesize my design with ISE 9.1i > It seems my Flipflop has been convert to a latch : out_reg copy the d > value during clockIn high state and block it during low state. > So I verify which primitive was instantiate in the post translate > simulation model generated by ISE, and I found a X_FF which is a > flipflop... So I don't understand anything.. It looks very strange.. :-
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