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On Jul 24, 9:39 am, John_H <newsgr...@johnhandwork.com> wrote: > devices wrote: > > "Jim Granville" <no.s...@designtools.maps.co.nz> wrote in message > >news:46a51c8d$1@clear.net.nz... > > >> Serial EE proms, have chosen a polling system for their 'wait' > >> requirements. > > >> -jg > > > Yeah, i notice the Ack polling in Microchip's seeproms. > > > By the way, are royalties still due to Philips? Or have the copyrights > > expired. Just curious, i read something about it time ago. > > > bye, Jim > > If you limit yourself to 400 kHz and 10 bit addressing, no royalties. > Our company contacted the Philips legal folks a couple years ago to > clear it up for ourselves. Do you mean no more than 400 KHz and no more than 10 bits? Or should there be royalties for 100 KHz and 7 bit addressing? The last time I talked with Philips they said it was okay to use I2C if there were Philips chips on the bus. In our case this is generally true.Article: 122251
Petter Gustad wrote: > Chris Carlen <crcarleRemoveThis@BOGUSsandia.gov> writes: > >>Is there something wrong with my .vcd file, or Gtkwave? Thanks for the reply. > Did you try to: > > click on the + in the SST window What is the SST window? Do you mean the zoom-in? > click on DFM1 There is no reference to DFM1 in the GtkWave window. > select all the signal names which appered in the Signals window > click Insert > > Looks fine in gtkwave on my machine. Interesting. Windows or Linux? Perhaps I will test a Windows version... -- Good day! ________________________________________ Christopher R. Carlen Principal Laser&Electronics Technologist Sandia National Laboratories CA USA crcarleRemoveThis@BOGUSsandia.gov NOTE, delete texts: "RemoveThis" and "BOGUS" from email address to reply.Article: 122252
Hi everybody, I'm using XPS/EDK with a MicroBlaze design and in my code I need a 64- bit wide variable. Is it possible in to define something like Xint32 but for 64bit? I know that the underlying architecture is 32bit wide but some compilers give the opportunity to declare 64bit variables and manage them (as two 32bit variables) in a transparent way to the developer. Is it possible to do it in EDK? Does exist a workaround to this issue? P.S. is it possible (also in assembler) to access to the 64bit register used by the processor for the result of the multiplication of two 32bit operands? Thanks a lot! AndreaArticle: 122253
Gabor wrote: > On Jul 24, 9:39 am, John_H <newsgr...@johnhandwork.com> wrote: > >>devices wrote: >>>By the way, are royalties still due to Philips? Or have the copyrights >>>expired. Just curious, i read something about it time ago. >> >>>bye, Jim >> >>If you limit yourself to 400 kHz and 10 bit addressing, no royalties. >>Our company contacted the Philips legal folks a couple years ago to >>clear it up for ourselves. > > > > Do you mean no more than 400 KHz and no more than 10 bits? Or > should there be royalties for 100 KHz and 7 bit addressing? > The last time I talked with Philips they said it was okay to > use I2C if there were Philips chips on the bus. In our case > this is generally true. I was told recently by a NXP disti, that i2c expired a 'couple of years ago'. It was always a loose coverage they had anyway, many of the docs state ~"you are free to use, provided you adhere to spec", but I think they did charge for the i2c logo/tm and so there was a quasi-license. In the embedded space, I doubt they could care either way. There was a 3.4MHz spec, but I never saw silicon. The new FM+ specs 20mA drivers, and lower pullups -jgArticle: 122254
EDK is based on gcc so look what gcc offers for 64 bit ints. Xilinx offers Xint64 (or something along those lines), but I didn't think it was very usable because it really is a struct containing a 32-bit low part and a 32-bit high part. Having the compiler take care of the work is much easier. As far as assembler goes, you can do almost anything in assembly, at least anything that a compiler can do. So yes, you can access that multiplication result registers, which in this case are user defined. There are no 64-bit registers, all are 32-bits. Find the PPC405 reference manual and look for the instructions mullw and mulhw. ---Matthew Hicks > Hi everybody, > > I'm using XPS/EDK with a MicroBlaze design and in my code I need a 64- > bit wide variable. > > Is it possible in to define something like Xint32 but for 64bit? > > I know that the underlying architecture is 32bit wide but some > compilers give the opportunity to declare 64bit variables and manage > them (as two 32bit variables) in a transparent way to the developer. > > Is it possible to do it in EDK? > Does exist a workaround to this issue? > P.S. is it possible (also in assembler) to access to the 64bit > register used by the processor for the result of the multiplication of > two 32bit operands? > > Thanks a lot! > > Andrea >Article: 122255
<Paul> wrote in message news:eea82cc.2@webx.sUN8CHnE... > there is a pullup on the bus. I made another test: decreasing the drive > strength of the FPGA from 12mA to 2mA allow MDIO to reach 3.3V ... What's the value of your pullup? I haven't looked at this pin with a scope but my design is working fine with 4mA drive, 2.1K pullup, 2.5 V voltage, and a VSC8201 PHY... /MikhailArticle: 122256
On Jul 24, 1:32 pm, Peter Alfke <pe...@xilinx.com> wrote: > We still do not know the width of the adder. > If it's a bit-serial 3-input adder, that takes only 4 LUTs plus two > flip-flops, and the combinatorial chain is only through two LUTs, so > it should easily meet the speed requirements. > Peter Alfke, Xilinx Applications > > On Jul 24, 7:18 am, skyworld <chenyong20...@gmail.com> wrote: > > > On 7 24 , 9 48 , John_H <newsgr...@johnhandwork.com> wrote: > > > > skyworld wrote: > > > > Hi, > > > > > I have to design with 3 input adder, i.e. D = A + B + C, in Spartan > > > > 3E. The addition has to be finished in one 153.6MHz clock. When I do > > > > PAR, I met timing violations. Can anybody give me some advices on how > > > > to implement this design? (I can't upgrade to other device because of > > > > cost). Thanks very much. > > > > > best regards > > > > > skyworld > > > > How large are the vectors you're adding? > > > > Have you looked at the timing analysis of your path to sanity-check the > > > timing violations? If you have long routing delays, that can be > > > accommodated with relative placements to keep the register-to-adder and > > > adder-to-adder routing delays down. Getting on and off the carry chain > > > may limit you at this speed. > > > > You may have to ask yourself if your requirement is *really* three adds > > > in one cycle. What do you do with the data after the clock? Comparing > > > to a constant, for instance, would allow you to take the difference of > > > the constant with A in the first cycle and compare to a B+C result > > > rather than a direct comparison to A+B+C. If the logic generating any > > > two vectors is simple enough, the values could be generated and the > > > difference taken before the first register. > > > > I do know that a divider that needed to completely daisy-chain four > > > 14-bit add/subtract stages per cycle was only happy at 66 MHz with some > > > RLOC constraints. Your situation is a little better since you're not > > > MSB carry-out to LSB, but not much. The time to get on and off that > > > carry chain may swamp your results. > > > > - John_H > > > Hi John, > > > in fact this design is for sigme-delta transmission modulator. I need > > a filter to transform 10 bit parallel input data (15.36MHz) to one bit > > output stream (153.6MHz). The filter are composed by 3 stage adders. > > Each adder has three inputs, i.e., what I have mentioned D = A + B + > > C. Every adder has to finish A + B + C within one 153.6MHz clock so > > that 153.6Mbps data stream works well. I have tried to use pipeline > > adder, but for this structure failed. So I am searching a way for > > "fast adder algorithm", or "fast three input adder algorithm", which > > could be implemented in Spartan 3E and runs fast enough. Thanks very > > much. > > > skyworld In the OP's second post he did say: "I need a filter to transform 10 bit parallel input data (15.36MHz) to one bit output stream (153.6MHz)." So I assumed that he meant 10-bits parallel data is input, then multipled and added, and then the ten-bit result is shifted out 1-bit at a time. -Dave PollumArticle: 122257
Hi all, For a new project we will need an FPGA and need to select one, so the question is: Altera or Xilinx? At least, it is my impression that those two are the major fpga companies today. Or did I mis something? I have searched this group and have called distributors for both, but there seems te be not much difference between them. Not in devices, EV-kits, free tools or price of the payed tools. Searching this group with google (starting from 2006-01-01 as I think much older information will be outdated by now) I found only found 87 messages containing both Altera and Xilinx. Most of those are in a thread that starts it's focus on Nios vs Microblaze and than soon derails unfortunately. The some meaningless statistics: Searching for Altera or Xilinx alone, also from 2006-01-01 to 2007-07-24: Altera : 2140 Xilinx : 11200 Searching older messages gives simular results. My previous experience with FPGA is rather old (+10 jears) and was with Actel and Quicklogic. Both seem to still be around, but seem far less in use than Xilinx or Altera. My latest experience with programmable logic is with a Xilinx CPLD (XC2C128), 2 1/2 jears ago. Although I'm trying to find the "best" choice for not only this project, but also for future projects, I will give some info on the current project. The designs needs a serial bus with automatic module enumeration (2 - 12 changeable modules, not hotplug), access control (master slave probably), buffers at each module (< 1kB), fixed timing, 10 - 40 Mbs. The master module will need aditional buffering, ethernet and a processsor (probably next to the fpga, not inside, but who knows). Slaves may or may not require a (simple) processor. And in future there may be a need for digital signal filters in some new slaves, but that could also be implemented in a DSP. My guess is that if it wasn't for the buffers, it could probably fit inside a CPLD. Any insights in what is the best FPGA for this (and other) application? What is the major difference, are the differences, between Altera and Xilinx? -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 122258
Then he would only need to add at 15.3 MHz which should be pretty easy to do. ---Matthew Hicks > On Jul 24, 1:32 pm, Peter Alfke <pe...@xilinx.com> wrote: > >> We still do not know the width of the adder. >> If it's a bit-serial 3-input adder, that takes only 4 LUTs plus two >> flip-flops, and the combinatorial chain is only through two LUTs, so >> it should easily meet the speed requirements. >> Peter Alfke, Xilinx Applications >> On Jul 24, 7:18 am, skyworld <chenyong20...@gmail.com> wrote: >> >>> On 7 24 , 9 48 , John_H <newsgr...@johnhandwork.com> wrote: >>> >>>> skyworld wrote: >>>> >>>>> Hi, >>>>> >>>>> I have to design with 3 input adder, i.e. D = A + B + C, in >>>>> Spartan 3E. The addition has to be finished in one 153.6MHz clock. >>>>> When I do PAR, I met timing violations. Can anybody give me some >>>>> advices on how to implement this design? (I can't upgrade to other >>>>> device because of cost). Thanks very much. >>>>> >>>>> best regards >>>>> >>>>> skyworld >>>>> >>>> How large are the vectors you're adding? >>>> >>>> Have you looked at the timing analysis of your path to sanity-check >>>> the timing violations? If you have long routing delays, that can >>>> be accommodated with relative placements to keep the >>>> register-to-adder and adder-to-adder routing delays down. Getting >>>> on and off the carry chain may limit you at this speed. >>>> >>>> You may have to ask yourself if your requirement is *really* three >>>> adds in one cycle. What do you do with the data after the clock? >>>> Comparing to a constant, for instance, would allow you to take the >>>> difference of the constant with A in the first cycle and compare to >>>> a B+C result rather than a direct comparison to A+B+C. If the >>>> logic generating any two vectors is simple enough, the values could >>>> be generated and the difference taken before the first register. >>>> >>>> I do know that a divider that needed to completely daisy-chain four >>>> 14-bit add/subtract stages per cycle was only happy at 66 MHz with >>>> some RLOC constraints. Your situation is a little better since >>>> you're not MSB carry-out to LSB, but not much. The time to get on >>>> and off that carry chain may swamp your results. >>>> >>>> - John_H >>>> >>> Hi John, >>> >>> in fact this design is for sigme-delta transmission modulator. I >>> need a filter to transform 10 bit parallel input data (15.36MHz) to >>> one bit output stream (153.6MHz). The filter are composed by 3 stage >>> adders. Each adder has three inputs, i.e., what I have mentioned D = >>> A + B + C. Every adder has to finish A + B + C within one 153.6MHz >>> clock so that 153.6Mbps data stream works well. I have tried to use >>> pipeline adder, but for this structure failed. So I am searching a >>> way for "fast adder algorithm", or "fast three input adder >>> algorithm", which could be implemented in Spartan 3E and runs fast >>> enough. Thanks very much. >>> >>> skyworld >>> > In the OP's second post he did say: "I need a filter to transform 10 > bit parallel input data (15.36MHz) to one bit output stream > (153.6MHz)." So I assumed that he meant 10-bits parallel data is > input, then multipled and added, and then the ten-bit result is > shifted out 1-bit at a time. > -Dave PollumArticle: 122259
For low-end projects that need things like ethernet or other high-end macros I would look at Lattice. I haven't had the opportunity to use any of their hardware or software but it seems that they offer more to lower-end customers. ---Matthew Hicks > Hi all, > > For a new project we will need an FPGA and need to select one, so the > question is: Altera or Xilinx? > > At least, it is my impression that those two are the major fpga > companies today. Or did I mis something? > > I have searched this group and have called distributors for both, but > there seems te be not much difference between them. Not in devices, > EV-kits, free tools or price of the payed tools. > > Searching this group with google (starting from 2006-01-01 as I think > much older information will be outdated by now) I found only found 87 > messages containing both Altera and Xilinx. Most of those are in a > thread that starts it's focus on Nios vs Microblaze and than soon > derails unfortunately. > > The some meaningless statistics: > Searching for Altera or Xilinx alone, also from 2006-01-01 to > 2007-07-24: > Altera : 2140 > Xilinx : 11200 > Searching older messages gives simular results. > My previous experience with FPGA is rather old (+10 jears) and was > with Actel and Quicklogic. Both seem to still be around, but seem far > less in use than Xilinx or Altera. My latest experience with > programmable logic is with a Xilinx CPLD (XC2C128), 2 1/2 jears ago. > > Although I'm trying to find the "best" choice for not only this > project, but also for future projects, I will give some info on the > current project. > > The designs needs a serial bus with automatic module enumeration (2 - > 12 changeable modules, not hotplug), access control (master slave > probably), buffers at each module (< 1kB), fixed timing, 10 - 40 Mbs. > The master module will need aditional buffering, ethernet and a > processsor (probably next to the fpga, not inside, but who knows). > Slaves may or may not require a (simple) processor. And in future > there may be a need for digital signal filters in some new slaves, but > that could also be implemented in a DSP. > > My guess is that if it wasn't for the buffers, it could probably fit > inside a CPLD. > > Any insights in what is the best FPGA for this (and other) > application? What is the major difference, are the differences, > between Altera and Xilinx? >Article: 122260
the pullup's value is 2K, 3.3V the PHY is a DP83865 from NSC. (thank's for the help).Article: 122261
On Jul 24, 11:24 am, "jacob...@xilinx.com" <naude.j...@gmail.com> wrote: > On Jul 23, 9:56 pm, bgelb.mit....@gmail.com wrote: > > > > > Hello - > > > I am trying to use the Xilinx MIG version 1.72 to generate a working > > interface for the DDR2 memory on the Xilinx ML501 eval board. I am > > having a bit of trouble. > > > I am able to simulate the controller and testbench just fine using > > ModelSim, but seem to be having issues getting it to work in hardware. > > At the moment, I am simply checking the output of the phy_init_done > > signal, which does not go high at any point, which indicates a problem > > to me. I have not yet been able to delve much deeper into where things > > are getting stuck. > > > I plan to use ChipScope to try to see what is going on, but I wonder > > before I get too far, if anybody else has tried a similar > > configuration? What experiences (good/bad) have people had with the > > MIG and Virtex-5 DDR2 designs? It would make me feel better if > > somebody out there had gotten it to work - it sounds like - from > > reading this group at least, that there are no shortage of issues with > > this stuff. > > > Thanks, > > Ben > > Did you do a behavioral simulation? Do a post-PAR simulation and check > if the initialization still completes. > > Also did you change the controller to work with the ML501? The ML501 > has a SODIMM device on it. Check the following link on information on > how to change the controller to work with a SODIMM memory:http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountry... > > Jaco Hi Jacob, Thanks for the reply. I did see the notes on using SODIMMs and believe I have followed it correctly. I also appropriately modified the testbench provided with the MIG output - 4 memory modules with 16-bit datawidth, etc. I had not run a simulation beyond behavioral. I ran a post-PAR sim this afternoon and it seems to still simulate correctly (i.e. phy_init_done) is asserted after ~42us. I did see some error messages in the modelsim terminal window though: # ** Error: /afs/csail.mit.edu/proj/redsocs/ISE9.1/verilog/mti_se/ simprims_ver/simprims_ver_source.v(102504): $setup( posedge DI[45] &&& (wren_enable == 1):3407202 ps, posedge WRCLKL:3407664 ps, 465 ps ); ...and later on... # ** Error: /afs/csail.mit.edu/proj/redsocs/ISE9.1/verilog/mti_se/ simprims_ver/simprims_ver_source.v(100215): $setup( negedge DDLY: 49680022 ps, posedge CLKB:49680321 ps, 305 ps ); # Time: 49680321 ps Iteration: 0 Instance: /ddr2_test_tb/uut_top/ \mint/u_ddr2_top_0/u_mem_if_top_0/u_phy_top_0/u_phy_io_0/ gen_dq[54].u_iob_dq/u_iserdes_dq\ Not sure if these indicate the simulation isn't running properly or what, but perhaps you can inform me faster than I can figure it out. Any sense on where to go now? Is there a design that is known to work on the ML501? I don't really want to use the EDK. Thanks, BenArticle: 122262
In comp.arch.fpga, Matthew Hicks <mdhicks2@uiuc.edu> wrote: > For low-end projects that need things like ethernet or other high-end macros > I would look at Lattice. I haven't had the opportunity to use any of their > hardware or software but it seems that they offer more to lower-end customers. Lattice! How could I forget? Used their CPLDs (isp1032?) some ten years ago. It indeed looks like they have some nice devices and tools seem comparable although the free version is only for evaluation (no sim?). Payed tools seem a bit cheaper than actel/xilinx though. Any experiences with device and tools here? -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)Article: 122263
Andrea05 <cispa@email.it> writes: > Is it possible in to define something like Xint32 but for 64bit? Maybe #include <stdint.h> and use uint64_t? I far prefer using ISO standard types over vendor-specific types. > I know that the underlying architecture is 32bit wide but some > compilers give the opportunity to declare 64bit variables and manage > them (as two 32bit variables) in a transparent way to the developer. That's called open-coding it. GCC normally does that when needed. > Is it possible to do it in EDK? I haven't tried, but I suspect it should work. > P.S. is it possible (also in assembler) to access to the 64bit > register used by the processor for the result of the multiplication of > two 32bit operands? You get either the low or the high part, depending on whether you use the mul or mulh instructions. If you want both parts, use both instructions.Article: 122264
Stef wrote: > For a new project we will need an FPGA and need to select one, so the > question is: Altera or Xilinx? > At least, it is my impression that those two are the major fpga > companies today. Or did I mis something? No, those are the two big fish. There are other smaller FPGA vendors such as Lattice and Actel. > I have searched this group and have called distributors for both, but > there seems te be not much difference between them. Not in devices, > EV-kits, free tools or price of the payed tools. How long is a piece of string? Should I buy Intel or AMD processors? A GM, Ford, or Toyota car? At the end of the day, it doesn't matter which you use as long as it gets the job done and is cost effective. If you really think that all else is equal, decide on the basis of price. It seems unlikely that there is no difference in price between the smallest devices that meet your requirements. EricArticle: 122265
On Jul 24, 11:24 am, "jacob...@xilinx.com" <naude.j...@gmail.com> wrote: > On Jul 23, 9:56 pm, bgelb.mit....@gmail.com wrote: > > > > > Hello - > > > I am trying to use the Xilinx MIG version 1.72 to generate a working > > interface for the DDR2 memory on the Xilinx ML501 eval board. I am > > having a bit of trouble. > > > I am able to simulate the controller and testbench just fine using > > ModelSim, but seem to be having issues getting it to work in hardware. > > At the moment, I am simply checking the output of the phy_init_done > > signal, which does not go high at any point, which indicates a problem > > to me. I have not yet been able to delve much deeper into where things > > are getting stuck. > > > I plan to use ChipScope to try to see what is going on, but I wonder > > before I get too far, if anybody else has tried a similar > > configuration? What experiences (good/bad) have people had with the > > MIG and Virtex-5 DDR2 designs? It would make me feel better if > > somebody out there had gotten it to work - it sounds like - from > > reading this group at least, that there are no shortage of issues with > > this stuff. > > > Thanks, > > Ben > > Did you do a behavioral simulation? Do a post-PAR simulation and check > if the initialization still completes. > > Also did you change the controller to work with the ML501? The ML501 > has a SODIMM device on it. Check the following link on information on > how to change the controller to work with a SODIMM memory:http://www.xilinx.com/xlnx/xil_ans_display.jsp?iLanguageID=1&iCountry... > > Jaco After my post-PAR simulation checked out I decided to check my sanity and try loading my bitfile on another eval board. It worked! (or at least phy_init_done gets asserted). Then I reseated the DIMM on the board I'd been using and it works too. So I guess things are solved for the moment. Thanks for the help. BenArticle: 122266
"Gabor" <gabor@alacron.com> wrote in message news:1185308366.265115.156820@m3g2000hsh.googlegroups.com... > On Jul 24, 9:39 am, John_H <newsgr...@johnhandwork.com> wrote: >> devices wrote: >> > "Jim Granville" <no.s...@designtools.maps.co.nz> wrote in message >> >news:46a51c8d$1@clear.net.nz... >> >> >> Serial EE proms, have chosen a polling system for their 'wait' >> >> requirements. >> >> >> -jg >> >> > Yeah, i notice the Ack polling in Microchip's seeproms. >> >> > By the way, are royalties still due to Philips? Or have the copyrights >> > expired. Just curious, i read something about it time ago. >> >> > bye, Jim >> >> If you limit yourself to 400 kHz and 10 bit addressing, no royalties. >> Our company contacted the Philips legal folks a couple years ago to >> clear it up for ourselves. > > > Do you mean no more than 400 KHz and no more than 10 bits? Or > should there be royalties for 100 KHz and 7 bit addressing? > The last time I talked with Philips they said it was okay to > use I2C if there were Philips chips on the bus. In our case > this is generally true. There are I2C implementations that exceed 400 kHz (1.6 MHz?) and/or have greater than 10-bit addressing. It's these items which are still covered by Philips patents. 100 kHz and 7 bit is fine according to what we got directly from the patent holders.Article: 122267
Symon wrote: > There's a bloke (John Adair) that posts on here whose company sells stuff > like that. > http://www.enterpoint.co.uk/component_replacements/craignell.html Looks like it may be suitable. It's disconcerting that the "Shop" link goes to a web store that doesn't appear to actually offer the product. I'll send them email.Article: 122268
Just another case of several nice people trying to answer an incomplete and confusing question. We recently have had too many of this type. Peter Alfke On Jul 24, 2:20 pm, Matthew Hicks <mdhic...@uiuc.edu> wrote: > Then he would only need to add at 15.3 MHz which should be pretty easy to do. > > ---Matthew Hicks > > > On Jul 24, 1:32 pm, Peter Alfke <pe...@xilinx.com> wrote: > > >> We still do not know the width of the adder. > >> If it's a bit-serial 3-input adder, that takes only 4 LUTs plus two > >> flip-flops, and the combinatorial chain is only through two LUTs, so > >> it should easily meet the speed requirements. > >> Peter Alfke, Xilinx Applications > >> On Jul 24, 7:18 am, skyworld <chenyong20...@gmail.com> wrote: > > >>> On 7 24 , 9 48 , John_H <newsgr...@johnhandwork.com> wrote: > > >>>> skyworld wrote: > > >>>>> Hi, > > >>>>> I have to design with 3 input adder, i.e. D = A + B + C, in > >>>>> Spartan 3E. The addition has to be finished in one 153.6MHz clock. > >>>>> When I do PAR, I met timing violations. Can anybody give me some > >>>>> advices on how to implement this design? (I can't upgrade to other > >>>>> device because of cost). Thanks very much. > > >>>>> best regards > > >>>>> skyworld > > >>>> How large are the vectors you're adding? > > >>>> Have you looked at the timing analysis of your path to sanity-check > >>>> the timing violations? If you have long routing delays, that can > >>>> be accommodated with relative placements to keep the > >>>> register-to-adder and adder-to-adder routing delays down. Getting > >>>> on and off the carry chain may limit you at this speed. > > >>>> You may have to ask yourself if your requirement is *really* three > >>>> adds in one cycle. What do you do with the data after the clock? > >>>> Comparing to a constant, for instance, would allow you to take the > >>>> difference of the constant with A in the first cycle and compare to > >>>> a B+C result rather than a direct comparison to A+B+C. If the > >>>> logic generating any two vectors is simple enough, the values could > >>>> be generated and the difference taken before the first register. > > >>>> I do know that a divider that needed to completely daisy-chain four > >>>> 14-bit add/subtract stages per cycle was only happy at 66 MHz with > >>>> some RLOC constraints. Your situation is a little better since > >>>> you're not MSB carry-out to LSB, but not much. The time to get on > >>>> and off that carry chain may swamp your results. > > >>>> - John_H > > >>> Hi John, > > >>> in fact this design is for sigme-delta transmission modulator. I > >>> need a filter to transform 10 bit parallel input data (15.36MHz) to > >>> one bit output stream (153.6MHz). The filter are composed by 3 stage > >>> adders. Each adder has three inputs, i.e., what I have mentioned D = > >>> A + B + C. Every adder has to finish A + B + C within one 153.6MHz > >>> clock so that 153.6Mbps data stream works well. I have tried to use > >>> pipeline adder, but for this structure failed. So I am searching a > >>> way for "fast adder algorithm", or "fast three input adder > >>> algorithm", which could be implemented in Spartan 3E and runs fast > >>> enough. Thanks very much. > > >>> skyworld > > > In the OP's second post he did say: "I need a filter to transform 10 > > bit parallel input data (15.36MHz) to one bit output stream > > (153.6MHz)." So I assumed that he meant 10-bits parallel data is > > input, then multipled and added, and then the ten-bit result is > > shifted out 1-bit at a time. > > -Dave PollumArticle: 122269
On Tue, 24 Jul 2007 12:07:50 -0700, Eric Smith <eric@brouhaha.com> wrote: >Does anyone sell a very tiny board with a Spartan 3 (or 3E, 3A, 3AN) >and regulators to run from a 3.3V supply? I only need a handful of >3.3V CMOS I/O pins, but the whole module needs to be really tiny, so I can >cram it into an existing device that has little room to spare. At most, >it could be about 50 mm square, and should be very low profile. > >If nothing like that is available, I'll design one using an XC3S400-4TQ144 >(or perhaps XC3S250E-4TQ144), but I'd like to avoid spending time on that if >possible. > >Thanks! >Eric How about these... http://www.oho-elektronik.de/index.php?c=1&s=product1Article: 122270
Stef wrote:
> Any insights in what is the best FPGA for this (and other) application?
> What is the major difference, are the differences, between Altera and
> Xilinx?
If your local distributors are really equivalent,
then the only significant difference
to me is vhdl synthesis.
I prefer Rob Dekker's vhdl front end
to brand X. The numeric_std library
also gets better coverage in the docs
and the rtl viewer is cleaner.
However,
if I preferred verilog,
or synopsys style vhdl,
or if I just wanted to
wire up some cores,
then it would still be a wash.
-- Mike Treseler
Article: 122271Mike Harrison wrote: > How about these... > http://www.oho-elektronik.de/index.php?c=1&s=product1 Looks good. I'll just have to remove the connectors to get the low profile I need. Thanks! EricArticle: 122272
On Tue, 24 Jul 2007 13:25:33 -0700, Chris Carlen <crcarleRemoveThis@BOGUSsandia.gov> wrote: >Petter Gustad wrote: >> Chris Carlen <crcarleRemoveThis@BOGUSsandia.gov> writes: >> >>>Is there something wrong with my .vcd file, or Gtkwave? > >Thanks for the reply. > >> Did you try to: >> >> click on the + in the SST window > >What is the SST window? Do you mean the zoom-in? Let's get some layout decided. At the top left there is a window which says "VCD loaded succesfully[12] facilities..." right? You're also seeing a window which has a title "Signals" and the content "Time" at this point from what you're describing. Now below "VCD loaded ..." window and to the left of "Signals" window, you should see a window which has SST in its title with a '+' to the left of SST string. If you see this click on the '+' and you should see your hierarchy. If you don't see the SST window, it's possible that your GTK+ setup is broken and you don't the right GTK+ installed.Article: 122273
Eric, although it is a Germany based company http://www.siphec.com/ may be worthwhile to have a look at Best regards Ulrich Bangert "Eric Smith" <eric@brouhaha.com> schrieb im Newsbeitrag news:m3ps2haad5.fsf@donnybrook.brouhaha.com... > Does anyone sell a very tiny board with a Spartan 3 (or 3E, 3A, 3AN) > and regulators to run from a 3.3V supply? I only need a handful of > 3.3V CMOS I/O pins, but the whole module needs to be really tiny, so I can > cram it into an existing device that has little room to spare. At most, > it could be about 50 mm square, and should be very low profile. > > If nothing like that is available, I'll design one using an XC3S400-4TQ144 > (or perhaps XC3S250E-4TQ144), but I'd like to avoid spending time on that if > possible. > > Thanks! > EricArticle: 122274
These are very precious information:)Thank you very much Fatih Gunes
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