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PSEN will go high a little bit AFTER the rising edge of the clock. The next rising edge of the clock presumably sets the signal to 0. It will actually be 0 a little time AFTER the rising edge of the clock. The time between those two events is one clock cycle.Article: 120826
On 16 Jun, 23:18, "Andrew Holme" <and...@nospam.com> wrote: > <rob.dim...@gmail.com> wrote in message > > news:1181925467.941552.286330@n2g2000hse.googlegroups.com... > > > Hi, > > > I have a vague memory that Xilinx used to provide excel spreadsheets > > that showed the graphical pinout of each FPGA package using coloured > > cells to represent each pin. > > I couldn't find any reference after much googling and searching of the > > Xilinx site. Does anyone have a pointer to these spreadsheets, if > > indeed they still (or ever) existed? > > > Rob > > They have an Excel spreadsheet for the Spartan 3 - I Googled "spartan 3 > datasheets" and went straight to it - but I could only see ASCII text files > for Virtex 4 e.t.c. Maybe they don't do it for BGA packages. Historically, the xilinx documentation assumed you wanted a certain amount of logic and gave you the pinouts for each package for a given density in each table. This was inherently not usefull, the truth being that you need a certain amount of IO which dictates the package. About three years ago I had spent several rediculous hours making sure I could place different densities of virtex in the same pcb footprint and posted my irritance here. The guy responsible for the Spartan documentation emailed me wanting to know what I thought of the docs he had created for spartan. Turned out he had created what we all needed. He apologised (in so many words) that he was not responsible for how the virtex pinouts were presented. The virtex documentation these days w.r.t. pinout is much better, but they are different. ColinArticle: 120827
"morphiend" <morphiend@gmail.com> wrote in message news:1181942772.110622.228360@q66g2000hsg.googlegroups.com... > > For the clock report generated by the error, we can't find a clock > region that would have too many clocks in it. In fact, the most the > report shows is 4 (or 5) out of 8 global clocks in a region. > Try locking down some of the BUFGs. Also. MPMC might have a problem placing IDELAYs, which might lead to clock routing issues, and sometime to non-working MPMC as well. There is an Answer Record showing how to modify the MPMC code to have them placed explicitly. And, in FX60 it makes sense to lock which TEMAC and which PPC are used, strangely enough the tools tend to use PPC and TEMAC, which are far away, which again leads to clock routing issues... /MikhailArticle: 120828
> When you said "define clock corectly", you meant define them in timing > analyzer. Am I right? Yes, all clocks need to be correctly defined in the Timing Analyzer > I did that and I found which paths have "Hold > Violation". But I don't know what to do now. What should I do to get > rid of this "Non operational path". In your case, I would continue focusing on why you have clock skew. A clean design should not have any clock skew to beging with, so changes in your HDL will likely be needed. As I said before, try doing a "List path" operation (use button-2 mouse on Hold Clock panel), and expand the clock skew message to get the detail path of both the source clock and the destination clock. You can locate to the chip planner and/or tech map viewer to visualize the path. Check specifically for combinational logic in your clock path, and if you find it, try to change your HDL to get rid of it (e.g. use the register's clock enable instead on an AND gate in your clock path). The other thing you want to check is your global clock utilization. Check the "Global Signals" under the "Resource Section" in the fitter report and confirm you are not running out of global signals, and that the clock in question has access to global resources. Also, take a look at the "Timing Optimization Advisor" and read http://www.altera.com/literature/hb/qts/qts_qii52005.pdf and http://www.altera.com/literature/hb/qts/qts_qii5v1_02.pdf for more ideas. Good luck. -David Karchmer AlteraArticle: 120829
Hi, Brian Thanks for all the valuable suggestion. Chaining is certainly not a good idea. Finally, we resolve this problem by shifting phase to certain degree of the DCM on FPGA B. The amount to shift is from experiment, which may not be perfect, but at least it passed stress test. Thanks Brian Drummond wrote: > On Fri, 15 Jun 2007 09:33:59 -0500, "Chris@Austin" <ggkuo@yahoo.com> > wrote: > >> On FPGA A, >> 1. A clock, APP_CLK (200 MHz), comes out of a DCM, which is used to >> mange the receiving clock from off-chip DDR2 DIMM. >> >> 2. APP_CLK drives another DCM for clock synthesis of 100 MHz and 50 MHz. >> The feedback of this DCM is from the output of DCM itself, which may be >> an issue. >> >> 3. Takes the 100 MHz clock to an ODDR primitive (Dedicated IOB double >> data rate output registers). This is suggested by Xilinx Vitex-5 User >> Guide. >> >> 4. forward this clock to FPGA B. >> >> on FPGA B, >> >> 1. use IBUG, DCM and BUFG to generate the synchronous clock. > > That's 3 DCMs in series, which is generally reckoned to be a bad idea, > because of jitter accumulation. > > (1) Can you not simply use IBUFG on the second FPGA? > If the DCM is just generating a copy of the incoming clock with no phase > shift, try without it. > > You have some tools in the IOBs to control signal timings between the > FPGAs, without adjusting clock phase in FPGA2; alternatively you may > have 90/180/270 degree phase shifts available on the 100MHz clock in > FPGA1. > > (2) Can you use CLKX2, CLK and CLKDV from a single DCM in the first > FPGA? (Alternatively, get both 100 and 200MHz from one DCM and use the > second DCM for only the 50MHz clock) > > Either of these will reduce the chain of DCMs down to the recommended > max of 2. Both will eliminate chaining DCMs altogether. > > (3) You could divide the 200MHz clock in a FF in FPGA1, to feed to > FPGA2, if you need the DCM in FPGA2. Take care to analyse the delay > introduced by the FF. > > Brian > >Article: 120830
Gabor, Let me know if it is a bug. AustinArticle: 120831
Kuo, If you move the phase shift to find the earliest point, and latest point, you then know the margin (and also know the center, or best setting). If the margin is at least 50% of the period, you are theoretically "perfect." A margin greater than 25% of the period may be perfectly good over process, voltage and temperature, as the DCM is unaffected largely by these effects. If you also look at your system jitter, peak to peak, you can see how much the jitter reduces your margins. AustinArticle: 120832
Ankit wrote:
> A few days back I installed xilinx ISE webpack 91i on fedora core 6
> everything worked out fine but i have not been able to simulate the
> testbench using the simulator provided by xilinx..whenever i double
> click on simulate behavioral model nothing happens..guys do help me
> out i am in a fix..
Two choices:
1. Load the windows version of ISE
2. Buy a modelsim SE floating license.
-- Mike Treseler
Article: 120833On Jun 18, 7:10 am, Laurent Pinchart <laurent.pinch...@skynet.be> wrote: > Hi everybody, > > I'm having trouble simulating a state machine withISEsimulator(ISE > 9.1.03i on Linux). At this point I'm not sure if the issue is in thesimulatoritself or in the waveform viewer (isimwave). > > The following signal type isn't displayed correctly in isimwave : > > type cmd_state_t is ( > STATE_IDLE, > STATE_START, > STATE_INDEX, > STATE_ARGUMENT, > STATE_CRC, > STATE_STOP, > STATE_WAIT, > STATE_RINDEX, > STATE_RARGUMENT, > STATE_RCRC > ); > > signal cmd_state : cmd_state_t; > > The process transitions from STATE_RINDEX to STATE_RARGUMENT, and then to > STATE_RCRC. The waveform viewer shows a transition from STATE_RINDEX to > STATE_IDLE, and then to STATE_START. As STATE_RARGUMENT and STATE_RCRC are > the 9th and 10th states, I suspect thesimulatoror the wave viewer > (probably the later) to use the 3 least significant bits only. > > When replacing the enumerated type with an integer, isimwave displays the > correct values : > > constant STATE_IDLE : integer := 0; > constant STATE_START : integer := 1; > constant STATE_INDEX : integer := 2; > constant STATE_ARGUMENT : integer := 3; > constant STATE_CRC : integer := 4; > constant STATE_STOP : integer := 5; > constant STATE_WAIT : integer := 6; > constant STATE_RINDEX : integer := 7; > constant STATE_RARGUMENT : integer := 8; > constant STATE_RCRC : integer := 9; > > signal cmd_state : integer; > > Has anyone run into the same problem ? Is there any workaround other than > switching to a non-enumerated type ? Any patch available ? > > Best regards, > > Laurent Pinchart HI Laurent, Please open a case with Xilinx Support on this issue. I think this might be fixed in 9.2i, that will be coming out soon, although we would need to have the testcase in house to confim. Thanks DuthArticle: 120834
sorry we dont have this problem. the applications actually synthesizes close to 50-55 MhZ in EDK. it was a wrong numerical calculation that made us worry. hence we can see that edk import peripheral works fine and the overall frequency might reduce by little compared to ur ise synthesis report. hope this will help others. regards, Mahalingam On Jun 14, 11:10 pm, "mahaling...@gmail.com" <mahaling...@gmail.com> wrote: > Dear all, > > I am a graduate student at USF. I am working with XILINX XUPV2P board > and i am usingedkto interface memory and my RTL code (using import peripheral). > > the RTL code synthesizes at 70 Mhz andEDKddr memory access works in > 100 Mhz. > > However when i connect RTL toEDKusing import peripheral, the design > only passes implementation, place and route in 1 MHz, it fails to > implement even in 25 Mhz. > > my application requires ddr memory access and data transfer fromedk > to rtl and so on. > > i really appreciate all ur suggestions. thanks for all ur help. > > sincerely, > MahalingamArticle: 120835
On Jun 17, 3:33 pm, Ankit <ankitanand1...@gmail.com> wrote: > Hi guys.. > > A few days back I installed xilinxISEwebpack 91i on fedora core 6 > everything worked out fine but i have not been able to simulate the > testbench using thesimulatorprovided by xilinx..whenever i double > click on simulate behavioral model nothing happens..guys do help me > out i am in a fix.. > > Regards > Ankit Hi Ankit, I am afraid that Fedora 6 is not a supported OS for Xilinx SW. Although since you are able to get all the other SW to work fine and it is only ISE Simulator that is giving you trouble, let us see if we can come up with a fix. Thanks DuthArticle: 120836
Hello, I am new to the embedded world and I am having a problem getting a Xilinx ML403 board to output any info while it is booting. I am using EDK 9.1 from Xilinx to create the bit stream for the ML403 board. I configured the software to use linux 2.6 and generated the libraries and BSPs. I had to change the xparameters.h file to include the xparameters_ml40x.h file. I am using Linux-2.6.22-rc1-gfaa8b6c3- dirty. I think this is a modified Montavista kernel. I downloaded the zImage.elf version of the kernel using the 'dow' command in 'xmd'. 'xmd' is a command console provided by Xilinx. When I type the 'run' command, I get the following output from the serial port. pb address: 00000000 loaded at: 00400000 004FA124 board data at: 00000400 0000047C relocated to: 0040405C 004040D8 zimage at: 00404F39 004F79A3 avail ram: 004FB000 7D7143A6 Linux/PPC load: console=ttyS0,9600 ip=on root=/dev/xsysace2 rw Uncompressing Linux...done. Now booting the kernel I get nothing after the 'Now booting the kernel' message is printed. Why does the serail port work while linux is loading, but it stops when the kernel starts to boot? If anyone can help me I would appreciate it!Article: 120837
On 14 Giu, 03:57, motty <mottobla...@yahoo.com> wrote:
> Sorry. Formatting screwed up : )
>
> Here's the code without comments.
>
> // implement slave modelregister(s)
> always @( posedge Bus2IP_Clk )
> begin: SLAVE_REG_WRITE_PROC
>
> if ( Bus2IP_Reset == 1 )
> begin
> slv_reg0 <= 0;
> end
> else if (push_frame_count_out_i == 1)
> begin
> slv_reg0 <= {16'b0, frame_count_out_i};
> end
> else
thank you Motty,
it works!!
Simple and clear!
Thanks, again.
A.
Article: 120838"Al" <alessandro.basili@cern.ch> wrote in message news:f52tma$dcc$1@cernne03.cern.ch... > Hi everyone, I have a strange behaviour in my implementation even if the > design is pretty simple (even if it's very dense!). > I have a decoding block which gets "address" to write data into several > registers. The decoding block is such that it will produce an enable > signal for each single register. Then a "write" signal is distributed > with some latency such that propagation delays are taken into account. > What I find is that for postsynthesis simulation everything is fine, but > in my postlayout I have some addresses which are enabled even if the > address is another one, turning out that I write two registers at once. > I can't really understand why! > > Here is a sketch of my vhdl code: > > > -- decoding signals > > p_signal1 <= '1' when addr = x"123" else > > '0'; > > p_signal2 <= '1' when addr = x"456" else > > '0'; > > > > > > -- writing process > > > > process (clk, nrst) > > begin > > if nrst = '0' then > > signal1 <= '0'; > > signal2 <= '0'; > > elsif rising_edge (clk) then > > if wr = '1' then > > if p_signal1 = '1' then > > signal1 <= data; > > elsif p_signal2 = '1' then > > signal2 <= data; > > ... > > end process; > > So it happens that writing to addr = x"123" it will change signal2 as > well...how can it be possible??? > > I did prefer to have "p_signals" and not use directly the "addr" in the > process just because in the very beginning I thought about latching the > "p_signals" to have them stable, but then I realized it wouldn't have > fit in the logic (I have already an occupancy of 84% and I have more > than 300 addresses to decode). > Do you have any explanation of this behaviour? Hi Alessandro, What do you mean with postsynthesis and postlayout? Gatelevel with and without timing? Also, what did you do with your write signal? Normally, you wouldn't have to delay it in a synchronous environment. Your code seems ok, even though I would replace the elsif p_signal2 by regular ifs: the reason is that you're now describing a priority decoded block, whik this is unnescessary. Regards, Alvin.Article: 120839
On Jun 18, 12:58 pm, Duth <premd...@gmail.com> wrote: > On Jun 18, 7:10 am, Laurent Pinchart <laurent.pinch...@skynet.be> > wrote: > > > > > Hi everybody, > > > I'm having trouble simulating a state machine withISEsimulator(ISE > > 9.1.03i on Linux). At this point I'm not sure if the issue is in thesimulatoritself or in the waveform viewer (isimwave). > > > The following signal type isn't displayed correctly in isimwave : > > > type cmd_state_t is ( > > STATE_IDLE, > > STATE_START, > > STATE_INDEX, > > STATE_ARGUMENT, > > STATE_CRC, > > STATE_STOP, > > STATE_WAIT, > > STATE_RINDEX, > > STATE_RARGUMENT, > > STATE_RCRC > > ); > > > signal cmd_state : cmd_state_t; > > > The process transitions from STATE_RINDEX to STATE_RARGUMENT, and then to > > STATE_RCRC. The waveform viewer shows a transition from STATE_RINDEX to > > STATE_IDLE, and then to STATE_START. As STATE_RARGUMENT and STATE_RCRC are > > the 9th and 10th states, I suspect thesimulatoror the wave viewer > > (probably the later) to use the 3 least significant bits only. > > > When replacing the enumerated type with an integer, isimwave displays the > > correct values : > > > constant STATE_IDLE : integer := 0; > > constant STATE_START : integer := 1; > > constant STATE_INDEX : integer := 2; > > constant STATE_ARGUMENT : integer := 3; > > constant STATE_CRC : integer := 4; > > constant STATE_STOP : integer := 5; > > constant STATE_WAIT : integer := 6; > > constant STATE_RINDEX : integer := 7; > > constant STATE_RARGUMENT : integer := 8; > > constant STATE_RCRC : integer := 9; > > > signal cmd_state : integer; > > > Has anyone run into the same problem ? Is there any workaround other than > > switching to a non-enumerated type ? Any patch available ? > > > Best regards, > > > Laurent Pinchart > > HI Laurent, > > Please open a case with Xilinx Support on this issue. I think this > might be fixed in 9.2i, that will be coming out soon, although we > would need to have the testcase in house to confim. > > Thanks > Duth Hi Laurent, This issue should be fixed in ISE 9.2i SP1. That will be released at the end of this month. Thanks DuthArticle: 120840
On Jun 18, 1:45 pm, Duth <premd...@gmail.com> wrote: > On Jun 17, 3:33 pm, Ankit <ankitanand1...@gmail.com> wrote: > > > Hi guys.. > > > A few days back I installed xilinxISEwebpack 91i on fedora core 6 > > everything worked out fine but i have not been able to simulate the > > testbench using thesimulatorprovided by xilinx..whenever i double > > click on simulate behavioral model nothing happens..guys do help me > > out i am in a fix.. > > > Regards > > Ankit > > Hi Ankit, > > I am afraid that Fedora 6 is not a supported OS for Xilinx SW. > Although since you are able to get all the other SW to work fine and > it is onlyISESimulatorthat is giving you trouble, let us see if we > can come up with a fix. > > Thanks > Duth Hi Ankit, We might have something that could work. Can you try the following: mv $XILINX/gnu/gcc/3.2.3/lin/bin/ld $XILINX/gnu/gcc/3.2.3/lin/bin/ ld.old ln -s /usr/bin/ld $XILINX/gnu/gcc/3.2.3/lin/bin mv $XILINX/gcc/3.2.3/lin/i686-pc-linux-gnu/bin/ld $XILINX/gcc/ 3.2.3/lin/i686-pc-linux-gnu/bin/ld.old ln -s /usr/bin/ld $XILINX/gcc/3.2.3/lin/i686-pc-linux-gnu/bin If this is a 64 bit machine, please use lin64 instead of lin for the path. Please let me know if this does not work. We might have to do the same for collect2 as well. Thanks DuthArticle: 120841
Hey Folks , I face a strange problem of adding my custom IP to the EDK project . My custom IP has two parts : a Small FSM and a Fifo Generated using coregenerator ( This was generated as EDN and the HDL is verilog) . I added my Custom IP to the Base System which has a ppc. I went into /pcores/mY_IP/hdl/Verilog and put my design. created /pcores/mY_IP/netlist and put all the EDN Files Then I defined my Black box Definition And added the various other options such as OPTION STYLE = mix, OPTION Ngc_build = true etc,. I get this weird problem If I click Generate netlist :. ERROR:MDT - File not found in any repository 'Fifo_test_v1_00_a/hdl/vhdl/simpl_tx.vhd' It defaultly goes and searches in the vhdl directory instead of verilog directory . Can anyone give me pointers abt this problem ? Is there any workaround that I synthesize the design in ISE and ask the EDK to use the NGC which would give me more flexibility ?Article: 120842
Hi all, I've been debugging my Active phase shift controller for so long and I think it's time to ask for help. If you have done this and would like to make some money, please reply me and let me know how much do you want for it. What I need is the state machine that control the DCM's psen, psclk, psdone and locked.... please help. sincerely,Article: 120843
On Jun 15, 9:37 am, Pablo <pbantu...@gmail.com> wrote: > On 15 jun, 16:10, "MM" <m...@yahoo.com> wrote: > > > "Pablo" <pbantu...@gmail.com> wrote in message > I have probed this method on a Spartan 3E starter kit ( another board > used for testing) and works fine. At the moment the custom board > doesn't work, but it is possible that exists this few skew. Is it a > method to apply a phase to a plb_ddr core? > > Pablo Would you mind to share the code you used on the spartan 3e kit ?Article: 120844
On Jun 18, 3:36 pm, "cutemonster" <ckh...@hotmail.com> wrote: > Hi all, I've been debugging my Active phase shift controller for so long > and I think it's time to ask for help. If you have done this and would > like to make some money, please reply me and let me know how much do you > want for it. > > What I need is the state machine that control the DCM's psen, psclk, > psdone and locked.... > > please help. > sincerely, What types of problems are you having? You may want to try posting some code here to get some help. You may also want to mention which part you're using. I've used the phase control on V4 and V2Pro parts and it doesn't seem to be all that hard to get to work. John ProvidenzaArticle: 120845
I have a Xilinx design that uses mainly verilog RTL and some .xco file for coregen FIFOs and such. I am using vcs compiler from synopsys. This compiler does not recgonize the xco files. Is there any way I can convert .xco file into verilog file using Xilinx coregen? I do not know why this shareware design does not provide the verilog file for coregen fifo and instead it has the .xco file. Is there any advantage in doing so? It will be great if I can convert the .xco file into .v for vcs verilog simulation. vcs compiler is able to compile the xilinx primitves .v files provided by Xilinx. Thanks for your help. MaverickArticle: 120846
I am trying to simulate the V5 GTP in ModelSim SE and am having trouble. I have compiled the sim libraries, followed the directions in the GTP user guide, followed the directions in the Synthesis and Simulation guide, and checked all the environment variables. Everything compiles and looks OK. However, when I invoke the simulation I get this warning: ** Warning: (vsim-PLI-3003) c:/xilinx_sim_libs/unisims_ver/ unisims_ver_SmartWrapper_source.v(22571): [TOFD] - System task or function '$lm_model' is not defined. # Region: /digrf3g_receiver_tf/DUT/digrf3g_gtp_top/ rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/ gtp_dual_swift_1/I1 The simulation does not work. Obviously, it has something to do with the swift model for the GTP, but I can't figure it out. I am using the 9.1 tools here. And I invoke the simulator by using: vsim -L unisims_ver -L XilinxCoreLib_ver -voptargs="+acc" digrf3g_receiver_tf glbl Any help would be much appreciated. I used to sim the V4 MGT with no problem. It seems like everything I try with the new tools doesn't work right away : )Article: 120847
Is your pao file implemented correctly? That's the first thing that popped into my head. So is the simpl_tx (that is how you spelled it above - maybe that's the problem?) a verilog file? As far as I know, the pao needs to specify that in the analyze order. There's no reason that you can't have a FIFO core ngc and HDL files in the same IP.Article: 120848
Yeah, post some code. This shouldn't be very hard. No offense, of course : ) I haven't used the dynamic phase shifting of the DCM, but I've used the DRP for the idelays and the MGT with no problems.Article: 120849
On Jun 19, 6:56 am, motty <mottobla...@yahoo.com> wrote: > I am trying to simulate the V5 GTP in ModelSim SE and am having > trouble. I have compiled the sim libraries, followed the directions > in the GTP user guide, followed the directions in the Synthesis and > Simulation guide, and checked all the environment variables. > Everything compiles and looks OK. However, when I invoke the > simulation I get this warning: > > ** Warning: (vsim-PLI-3003) c:/xilinx_sim_libs/unisims_ver/ > unisims_ver_SmartWrapper_source.v(22571): [TOFD] - System task or > function '$lm_model' is not defined. > # Region: /digrf3g_receiver_tf/DUT/digrf3g_gtp_top/ > rocketio_wrapper_i/tile0_rocketio_wrapper_i/gtp_dual_i/ > gtp_dual_swift_1/I1 > > The simulation does not work. Obviously, it has something to do with > the swift model for the GTP, but I can't figure it out. I am using > the 9.1 tools here. And I invoke the simulator by using: > > vsim -L unisims_ver -L XilinxCoreLib_ver -voptargs="+acc" > digrf3g_receiver_tf glbl > > Any help would be much appreciated. I used to sim the V4 MGT with no > problem. It seems like everything I try with the new tools doesn't > work right away : ) This is propably because you have not properly configured your modelsim.ini You need to double check whether you have pointed the "Veriuser" variable in "modelsim.ini" to the "libswiftpli.sl" and "mtipli.so" correctly Anand
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