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<jonyt@eng.tau.ac.il> wrote in message news:1182070630.512339.182370@g4g2000hsf.googlegroups.com... > hi, > > I need to design and implement a very simple FPGA. There will be 34 > TTL inputs. One (and only one) will be tripped every few seconds. I > need the FPGA to report on which one was tripped. So the output will > be six bits outputted via either RS232 or USB, whichever is easier to > implement. > > At this stage I need only one unit and I don't know anyone who'll make > such a small quantity. Designing it on my own is not really an option > because I'm a mechanical engineer :-) > > Can anyone recommend someone who can do this for me? > > thanks, > Yoni. > Hi Yoni, I guess you're at Tel Aviv university from your email address. I have good news, it would appear that your university has an electrical engineering school. Why don't you wander down the corridor with some bagels and see if someone will help you out? ;-) HTH, Syms.Article: 120801
jonyt@eng.tau.ac.il wrote: > I need to design and implement a very simple FPGA. There will be 34 > TTL inputs. One (and only one) will be tripped every few seconds. I > need the FPGA to report on which one was tripped. How long is the pulse? How long is the minimum time between 2 pulses? If the pulse has a length of some microseconds and if there is at least the time needed to send one byte to RS232 between two pulses, then you should use a microcontroller. If you need only one unit, you could try e.g. a header board for the LPC2148, like this one: http://www.sparkfun.com/commerce/product_info.php?products_id=676 You can download the free GNU C compiler for it, or try some trial versions of commercial compilers for it. With a JTAG interface you can even debug the C programs on board, but for your task the program would be less than 10 lines, including RS232 communication, which is implemented in hardware on the microcontroller. Could be done in some minutes, when starting with some of the sample projects. > So the output will > be six bits outputted via either RS232 or USB, whichever is easier to > implement. Of course, USB is much easier than RS232 :-) If you don't need USB, the LPC2148 is overkill for your project and you could use a PIC: http://www.microchip.com/ A small one, for less than 5 Euro would do it. If you have very short pulses or small pauses between the pulses, so that new pulses can arrive while transfering, a FPGA or CPLD would be better. If you don't need to cache many pulses or additional information, a CPLD should work. -- Frank Buss, fb@frank-buss.de http://www.frank-buss.de, http://www.it4-systems.deArticle: 120802
On Jun 16, 4:19 pm, John_H <newsgr...@johnhandwork.com> wrote: > fpgabuilder wrote: > > On Jun 15, 10:18 am, "John_H" <newsgr...@johnhandwork.com> wrote: > >> "cutemonster" <ckh...@hotmail.com> wrote in message > > >>news:CuOdneSaAIBJXO_b4p2dnAA@giganews.com... > > >> Whatever you do, please don't use the DCM to generate the clock for the ADC > >> since it could raise the noise floor of the ADC output significantly. > >> Instead, use the clean clock that feeds the ADC to run the FPGA. > > >> - John_H > > > I am curious as to know the reason behind not using fpga generated > > clock to drive the adc. Is it because they have higher amount of > > jitter? I am in the process of designing a datapath from adc to the > > fpga. > > > Thanks. > > -sanjay > > The jitter is the problem. For a high speed ADC, the error from jitter > can approach the ratio of the jitter to the clock period for a properly > band-limited input signal. For a direct IF sampling system, the error > can exceed that ratio. If you think of the voltage slewing on the ADC > input, the error in the sample point corresponds directly in a voltage > error; if the sample was ideally zero volts, the jitter makes the actual > sample further up or down that rapidly changing voltage. > > The noise floor will be noticeably raised in a fast system. The > cleanest way to work with an FPGA/ADC system is to use the clean clock > to drive the ADC and the FPGA, no daisy chaining. If you *must* use an > FPGA to drive the clock (if you're doing phase modulation of the > sampling, for instance) then a cleanup PLL is required to get the noise > down to an acceptable level. > > FPGAs are superb for logic. They are not designed to function as analog > elements. The DCMs are well specified and perform very well for even > the most demanding logic. But DCMs are not analog quality. Treat them > as analog noise sources! The jitter is the biggest issue. > > - John_H Thanks John for this insight. Very helpful. But this has raised some questions in my mind. Xilinx uses DCMs and they add jitter to the clocks. On the other hand Altera uses PLLs and they actually filter out the jitter. So in this case it would be good to go with an Altera device and drive the clocks to ADC? Or do you see some other problems as well. Thanks. -sanjayArticle: 120803
Al wrote:
> So it happens that writing to addr = x"123" it will change signal2 as
> well...how can it be possible???
Maybe addr is not synchronized to clk.
-- Mike Treseler
Article: 120804fpgabuilder wrote: > > Thanks John for this insight. Very helpful. But this has raised some > questions in my mind. Xilinx uses DCMs and they add jitter to the > clocks. On the other hand Altera uses PLLs and they actually filter > out the jitter. So in this case it would be good to go with an Altera > device and drive the clocks to ADC? Or do you see some other problems > as well. > > Thanks. > -sanjay The use of a PLL will help your situation. But keep in mind that FPGAs are ALL concerned with digital signals and are NOT designed as analog devices! Although the Altera device has significantly less jitter than the Xilinx DCM output, the output will be contaminated by other FPGA characteristics. Just having other I/O switching on the same bank is enough to generate noise in the output clock. Your best bet is to NEVER drive the ADC directly from your FPGA independent of the brand. But you can get by without the cleanup PLL (the dedicated, external analog device) *if* you do an error analysis to determine how much jitter is tolerable on your ADC clock. If, for instance, you have an audio stream used for communications (14 bits or fewer at 8 kS/s, encoded to 8 bits) then your worries are pretty limited. If you have a 16-bit ADC running at 400 MHz, you're in a world of hurt without extreme design constraints for a clean sampling timebase. You will ALWAYS benefit from having a fixed sampling clock fed to the ADC from the oscillator rather than from the FPGA. If that clock topology is impractical, you have to decide how much error or noise floor is acceptable for your application and guarantee that your logic device won't degrade the clock beyond your acceptable level. While the Altera solution *may* be better than the Xilinx solution by 20 dB, I would suspect the improvement is more on the order of 12-14 dB without extreme care in the power supply and I/O activity for the Altera alternative. I don't have evidence to support my numbers, just expectations in raw performance. - John_HArticle: 120805
Hi everyone, We are a group of Computer Science students working on a project on the XUP board's PowerPC processor core to run an image processing algorithm and communicate back and forth with a PC across an Ethernet connection. We are having a bit of trouble configuring the board to be able to run our code or any example code properly. We would really appreciate any help since we are nowhere near experienced with the hardware configuration and terminology. Here's the current system we're trying to work on: - XUP V2Pro board fitted with 512 DDR Ram - EDK 9.1i and ISE 9.1i So far we have found out that we would need to use the light weight IP (lwIP) library in Socket API mode, but we are totally lost in terms of how to configure the project in EDK properly to allow such thing. Should we use the "standalone" OS or "xilkernel"? And how do we configure the linker script for the software project so that we can utilize the 512MB RAM correctly? We would really Really appreciate it if anyone can provide step-by- step information on how to configure the project, starting from the BSB wizard and until the project is ready to build successfully. We have tried following several tutorials and whitepapers from Xilinx and otherwise, but most of them either work for a different EDK version or a different development board, so the configuration doesn't apply and it ends up not working. Thank you in advance for any help! Best Regards, Islam OssamaArticle: 120806
"Fred" <fred@n0spam.com> wrote in message news:4673db4e$0$30318$fa0fcedb@news.zen.co.uk... > Is there a method of using external RAM (Generic external Memory) > where the data, heap and stack can be located? Ideally the code would > remain in BRAM so not to require additional external non-volatile > memory. > > I've tried altering the loader script to indicate a different address > range for the data side but I come up with: > WARNING:MDT - Elf file TestApp_Memory/executable.elf does not reside > completely within BRAM memory of processor microblaze_0. > > Is there an example I can use as a starting point - if one exists! I don't know this CPU/toolset, but there are, with most modern CPUs I've dealt with, plenty of ways of confusing the "code" and "data" segments such that the separation is not as total as you'd expect. By which I mean that perhaps your linker script is nonetheless attempting to store constant data/code somewhere other than code memory. Just a thought... Steve http://www.fivetrees.comArticle: 120807
I have and odd question. As a final year student at EE course (thesis is a complex FPGA project) I am starting to get concerned about future job. I would like to ask, whether someone can present his opinion about job market when it comes to FPGA designers in Europe (getting USA visa is difficult, probably not worth trying). I have found several job offers for senior ( >7 years of experience) engineers, but few to none for graduates or juniors. Most universities don't teach ASIC design, and that's also very common job requirement. While teaching yourself software developement is relatively easy, self- studying ASIC and very advanced FPGA design is almost impossible without good mentor/practice/real-life-experience. Can anyone relate to this? Were this studies big mistake?Article: 120808
Hi guys.. A few days back I installed xilinx ISE webpack 91i on fedora core 6 everything worked out fine but i have not been able to simulate the testbench using the simulator provided by xilinx..whenever i double click on simulate behavioral model nothing happens..guys do help me out i am in a fix.. Regards AnkitArticle: 120809
I'm running into the following error message when I run Xpower on a Spartan 3A design: WARNING:Power:738 - Vccint <1.200> not in recommended range [0.940..1.060]V. However from the datasheet DS529.pdf I see recommended operating voltage (min) (typ) (max): VCCINT Internal supply voltage 1.140 1.200 1.260 V So what is the real core supply voltage for Spartan 3A? Anyone? Xilinx? :) Regards, GaborArticle: 120810
freeplatypus, Generally, FPGA design is a marketable skill. Many companies have abandoned ASIC's as being far too expensive. For example, the major telecom wired, and wireless suppliers can not afford a 2 million $ mask, and have embraced FPGAs almost to the exclusion of developing their own ASICs. Are ASIC's completely dead? No, of course not. Cell Phones, game consoles, and basically anything that can afford the capital investment, still will use an ASIC. But, more and more ASIC designers are finding themselves surplus. Xilinx still hires ASIC designers, but we definitely have our choice of hiring only the finest at present (a buyer's market). ASSP devices have had a renaissance of sorts, as if there is a specific chip that does the job, it is often preferable to developing an ASIC, and often is less expensive than a FPGA. The issue with an ASSP, is that anyone can buy and use it, so you are automatically facing competition (and low margins). Myself, I prefer an employer that enjoys 60%+ margins: clean restrooms, garbage pickup, a nice cafeteria must come from somewhere (after all, it isn't free), and 40% margin companies enjoy none of that... Although it is discouraging to see job listings that all require experience, the smart student has already been employed as a summer intern, and has that experience. If you go to school, and expect people to hire you when you get out, with never having used any of your skills (summer job, intern, etc), you will be at a disadvantage, regardless of skill set. AustinArticle: 120811
1.20 volts, + or - 5%. AustinArticle: 120812
On Jun 17, 9:02 pm, austin <aus...@xilinx.com> wrote: > 1.20 volts, + or - 5%. > > Austin Austin, Thanks. By the way I'm running 9.1i sp3, but I guess I would almost have to for Spartan 3A. Regards, GaborArticle: 120813
leevv wrote: > There is a way (at least Xilinx descibe it somewhere) to load cache > through the USER_ACCESS_REGISTER. Software(bootloader) portion is > appended to the configuration data portion of FPGA. After FPGA is > configured, your proceeed with sending software portion of data to > the FPGA. Inside FPGA, special hardware block converts your data > stream to JTAG commands for PPC. These commands put your software > into the cache and run it. xapp719 has the secret information. Thanks for the tip, leevv.Article: 120814
We are one company that do such things. It may be possible that one of our standard development boards may satisfy your hardware requirements and the FPGA description does not sound at all complex. John Adair Enterpoint Ltd. www.enterpoint.co.uk On 17 Jun, 09:57, j...@eng.tau.ac.il wrote: > hi, > > I need to design and implement a very simple FPGA. There will be 34 > TTL inputs. One (and only one) will be tripped every few seconds. I > need the FPGA to report on which one was tripped. So the output will > be six bits outputted via either RS232 or USB, whichever is easier to > implement. > > At this stage I need only one unit and I don't know anyone who'll make > such a small quantity. Designing it on my own is not really an option > because I'm a mechanical engineer :-) > > Can anyone recommend someone who can do this for me? > > thanks, > Yoni.Article: 120815
jonyt@eng.tau.ac.il wrote: > hi, > > I need to design and implement a very simple FPGA. There will be 34 > TTL inputs. One (and only one) will be tripped every few seconds. I > need the FPGA to report on which one was tripped. So the output will > be six bits outputted via either RS232 or USB, whichever is easier to > implement. > > At this stage I need only one unit and I don't know anyone who'll make > such a small quantity. Designing it on my own is not really an option > because I'm a mechanical engineer :-) > > Can anyone recommend someone who can do this for me? If the trip rate is so low, this is probably a better microcontroller problem than a FPGA problem. If the trip was in the Microsecond domain, then FPGA makes sense. All you need is a microcontroller PCB with 34 IO lines, that can interrupt, and queue the channel ID, to a serial transmit. Probably an undergraduate project, or a student looking for a real-world problem to hone their skills on ? -jgArticle: 120816
Hi all
In the datasheet, psen has to be asserted before rising edge of psclk for
one clock. How can I implement this? Should I use the clock to drive
psclk as the clock of my state machine? If so, then
-------------------------------------------
always @ (posedge PSCLK_clk)
begin
// other logics....
PSEN <= 1;
end
-------------------------------------------
But PSEN will be asserted during the rising edge of PSCLK. And it may not
meet the setup time. What is the correct way to drive this?
Is this the problem that make my dynamic phase alignment don't work?
Please advice,
sincerely,
Article: 120817Mike Treseler wrote: > Al wrote: > >> So it happens that writing to addr = x"123" it will change signal2 as >> well...how can it be possible??? > > > Maybe addr is not synchronized to clk. unfortunately it is synchronized with clk and so it is the wr signal. The Designer shows a lot of timing problems but with multicycle path i managed to solve those problems (even if those constraints are not used to optimize the path, only to check timing constraints). I tried to synchronize even the p_signal (getting to the 98% of occupancy) but it didn't help. I'm still puzzled! Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 120818
On Jun 17, 10:57 am, j...@eng.tau.ac.il wrote: > hi, > > I need to design and implement a very simple FPGA. There will be 34 > TTL inputs. One (and only one) will be tripped every few seconds. I > need the FPGA to report on which one was tripped. So the output will > be six bits outputted via either RS232 or USB, whichever is easier to > implement. You can buy a single chip solution that is very easy to use. http://www.ftdichip.com/Products/FT245BM.htm If you search around you can finde various low cost products that use that chip and can be used for your application. (Like uC or FPGA download/debug cables, low end usb logic analyzers, etc.) Kolja SulimmaArticle: 120819
Thanks, it worked. In reallity I discovered it alone about 10 minutes after I posted the question, but thanks anyway by your fast and acurate response :)Article: 120820
Al wrote: > Mike Treseler wrote: > >> Al wrote: >> >>> So it happens that writing to addr = x"123" it will change signal2 as >>> well...how can it be possible??? >> >> >> >> Maybe addr is not synchronized to clk. > > > unfortunately it is synchronized with clk and so it is the wr signal. > The Designer shows a lot of timing problems but with multicycle path i > managed to solve those problems (even if those constraints are not used > to optimize the path, only to check timing constraints). > I tried to synchronize even the p_signal (getting to the 98% of > occupancy) but it didn't help. > I'm still puzzled! > I've decided not to wait longer and program the chip regardless of the simulation problem. I found that the chip shows no such problems in the registers but I should test it within the temperature range and see if it will work correctly. I still don't know why the simulation doesn't end correctly. By the way, some collegues of mine told me that Sinplify implements two registers when these are read/write registers and one is used for read and both are used for write. This is due to the fact that the second register may be internally used for some other logic which will need to access to this register. Is it possible? Will this behaviour lead to the problem I described in this thread? Thanks all, Al -- Alessandro Basili CERN, PH/UGC Hardware DesignerArticle: 120821
On 13 Jun., 16:52, "Amontec, Larry" <laurent.ga...@ANTI- SPAMamontec.com> wrote: > ON NEXT MONDAY : 17-JUNE-2006 > > Amontec will provide the 'how-to' program via a XILINX VIRTEX XC4VLX25 > 7.9Mbits bit stream) at 2.8 seconds using the Amontec JTAGkey ! > > On next Monday, your Amontec JTAG key will be close to the speed of a > Xilinx Platform Cable USB for programming any FPGA and CPLD vendors > (Altera Xilinx Lattice Cypress ...) > > Come back next Monday onhttp://www.amontec.com! > > Laurent Hi Laurent, I assumed you meant next monday, as "monday next week" from current day, this would then be TODAY but on your website it reads: "ON NEXT MONDAY : 17-JUNE-2006" this is monday a year ago?? so where is this 2.8 second HOWTO "coming next monday" is it going to be online today ? or was it online year ago? if it was year ago then its really old news. hm.. ok, the monday is almos over, in japan its way past working hours already, and the HOWTO is not yet available, hm should we all look your website in june 2006 ?? ah, maybe I should use webarchive.org to fetch the old pages? Antti is still hoping to see how amontec FS device works faster then HS USB from XilinxArticle: 120822
MikeJ wrote: >> Seriously, the file had generate loops to start with, but I couldn't >> find a way to control the assignment of instance names so that I could >> use the LOC constraints in a deterministic way. Is there a trick, or >> a convention as to how the loop index gets added to the name? >> > Earlier XST versions were a bit broken in this regard, but 9.1 is more > consistent. Have a read of the XST users guide it explains it. Many thanks for the help! I'll come back to this once I make the shift to 9.1 -- I've been holding off because I'm in the middle of a project. -- DaveArticle: 120823
Hi everybody,
I'm having trouble simulating a state machine with ISE simulator (ISE
9.1.03i on Linux). At this point I'm not sure if the issue is in the
simulator itself or in the waveform viewer (isimwave).
The following signal type isn't displayed correctly in isimwave :
type cmd_state_t is (
STATE_IDLE,
STATE_START,
STATE_INDEX,
STATE_ARGUMENT,
STATE_CRC,
STATE_STOP,
STATE_WAIT,
STATE_RINDEX,
STATE_RARGUMENT,
STATE_RCRC
);
signal cmd_state : cmd_state_t;
The process transitions from STATE_RINDEX to STATE_RARGUMENT, and then to
STATE_RCRC. The waveform viewer shows a transition from STATE_RINDEX to
STATE_IDLE, and then to STATE_START. As STATE_RARGUMENT and STATE_RCRC are
the 9th and 10th states, I suspect the simulator or the wave viewer
(probably the later) to use the 3 least significant bits only.
When replacing the enumerated type with an integer, isimwave displays the
correct values :
constant STATE_IDLE : integer := 0;
constant STATE_START : integer := 1;
constant STATE_INDEX : integer := 2;
constant STATE_ARGUMENT : integer := 3;
constant STATE_CRC : integer := 4;
constant STATE_STOP : integer := 5;
constant STATE_WAIT : integer := 6;
constant STATE_RINDEX : integer := 7;
constant STATE_RARGUMENT : integer := 8;
constant STATE_RCRC : integer := 9;
signal cmd_state : integer;
Has anyone run into the same problem ? Is there any workaround other than
switching to a non-enumerated type ? Any patch available ?
Best regards,
Laurent Pinchart
Article: 120824On Jun 15, 1:54 pm, Sean Durkin <news_ju...@durkin.de> wrote: > Symon wrote: > > Hi Rob, > > Try partgen -v device_name at the DOS prompt. > > Or try Jim Wu's ADEPT:http://home.comcast.net/~jimwu88/tools/adept/ > > It has a similar functionality built in. Or maybe it calls partgen and > displays tne result in Excel? Dunno, but very handy tool nevertheless. Yes, ADEPT runs partgen and several other ISE tools in the background. The goal is to present the information in ways that make more sense to users. Cheers, Jim
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Compare FPGA features and resources
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