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> If I use Synplify tool for synthesis and select v4 fpga what will > happen if I select the v5 in the ISE during the Mapping. Does it will > select the resource that's available only in the v5? I dont know how exactly the tool will behave. But in the synthesized output obtained from the synplify there will surely be some components which belongs to v4 only. This will generate an error in the mapping stage of the V5 based flow. In the synplify what they do is convert the behaviour model to some macros (or large functional units) first in the synthesize stage. Try some mux it will simply put a large mux there. Then in the mapping stage it will get mapped to specific LUTs or FFs etc. These selection of component is strictly deveice specific. In the ISE also i guess similar kind of flow. In my experiance several times i have mapped a design which is synthesized for v4lx60 to v4lx100 and 200 devices without any error. In this case there is no mismatch of component but no: of components only matter.Article: 120226
On 2007-06-04, Mark McDougall <markm@vl.com.au> wrote: > > I should clarify - you simply need to instantiate the SFL mega-function in > your design. I thought the point of the megafunction was to add the SFL programming function to your image, so that you would not have to halt your device and send the "stub" image over while programming the serial. That way the JIC programming would be transparent to the application until the next reset. With the programmer insisting on sending the shim, there seems to be no point to putting the SFL megafunction into your own design, since it will not be used. (Well, unless you were using it for direct serial access, but if it can't program via SFL you might as well use ASMI instead!) -- Ben Jackson AD7GD <ben@ben.com> http://www.ben.com/Article: 120227
Ben Jackson wrote: > I thought the point of the megafunction was to add the SFL programming > function to your image, so that you would not have to halt your device > and send the "stub" image over while programming the serial. That way > the JIC programming would be transparent to the application until the > next reset. I've never used it like that so I'm not sure. Regards, -- Mark McDougall, Engineer Virtual Logic Pty Ltd, <http://www.vl.com.au> 21-25 King St, Rockdale, 2216 Ph: +612-9599-3255 Fax: +612-9599-3266Article: 120228
I am running Ubuntu 7.04 in VMware on my MacBook. Here is how a solved the problem with connecting to the ML403 board using the USB cable. See my blog: http://svenand.blogdrive.com/archive/55.html SvenArticle: 120229
I am writing a blog about "FPGA design from scratch", where I use a Xilinx ML403 board to design an embedded system. You can read more here : http//www.fpgafromscratch.com SvenArticle: 120230
Hi, You can read my blog: www.fpgafromscratch.com SvenArticle: 120231
Hi, I am running Ubuntu Linux 7.04 in VMware Fusion on my MacBook. I have described the whole process of installing and using Xilinx ISE/EDK 9.1 software on the ML403 evaluation board. See my blog: www.fpgafromscratch.com SvenArticle: 120232
I'm student at Chemnitz University of Technology, Germany. I'm interested in purchasing an xupv2p-board from digilent inc as a academic customer (299$). Has anyone done this before (as a student from Germany) and can share his/her gained experiences. Is it possible at all? Thanks. L. SchreiberArticle: 120233
On Jun 4, 2:22 am, Koustav <kousta...@gmail.com> wrote: > Hello everybody, > > I am trying to interface my user logic ip_inv through the OPB in EDK > using a register like this: > > the c code in my test_application to access the ipcore is : > > IP_INV_mWriteReg(0x00000010, 0, read_val); > read_val2=IP_INV_mReadReg(0x00000010, 0); > > My user logic is just a not operation. How do we make sure that the > value is written from the IPIF register into the user logic and then > back to the IPIF register ? I am expecting a inverted value in > "read_value2" but I am getting the same value as "read_value". > > Thanks, > KOustav why don`t you implement a sum operator?. It is simplest and it provides you that information.Article: 120234
Hi finally !!! XP2 was scheduled for september 2006 so with a little less than 12 months delay its finally announced!! http://www.latticesemi.com/products/fpga/xp2/index.cfm?jsessionid=ba307e710623P$5F$3F$ AnttiArticle: 120235
Hi, ISE's map report states a "Total equivalent gate count for design". Can this equivalent gate count be used to compare roughly and very approximate to an equivalent ASIC implementation? Thanks, SimonArticle: 120236
Thanks you Neil. I read that, but I am using the Slave Serial configuration mode, which shouldn't disable the ICAP. We are still investigating the board/FPGA configuration to see if it could be related to something else. Fabien On Jun 2, 1:07 am, Neil Steiner <neil.stei...@vt.edu> wrote: > > I read somewhere, there may be a conflict when using ICAP and JTAG. > > Do anybody have any information about this? > > That is correct. Read the "Important Note" paragraph on page 3 ofhttp://www.xilinx.com/bvdocs/ipcenter/data_sheet/opb_hwicap.pdf(actual > page number is 70): > > "Important Note: The HWICAP core uses the ICAP found inside Virtex IITM > and Virtex-II ProTM devices. The ICAP port interface is similar to the > SelectMAP interface, but is accessible from general interconnects rather > than the device pins. The JTAG or "Boundary Scan" configuration mode pin > setting (M2:M0 = 101) will disable the ICAP interface. Therefore, when > using the HWICAP core, another mode pin setting must be used. If JTAG > will be used as the primary configuration method, select another mode > pin setting to avoid disabling the ICAP interface. JTAG configuration > will still be available because it overrides other means of > configuration, and the HWICAP core will function as intended." > > "Besides being disabled with the Boundary Scan mode pin setting, the > ICAP will be disabled if the persist bit in the device configuration > logic's control register is set. When using bitgen one must make sure > that the Persist option is set to No, which is the default. This option > is generally specified in the bitgen.ut file in the etc subdirectory of > the EDK project."Article: 120237
Antti wrote: > Hi > > finally !!! > XP2 was scheduled for september 2006 so with a little less than 12 > months delay its finally announced!! Maybe that's because Lattice only announces devices when you can actually buy them and not 12 months before a "normal" customer can get his hands on some engineering samples? :) cu, Sean -- My email address is only valid until the end of the month. Try figuring out what the address is going to be after that...Article: 120238
On 4 Jun., 11:09, Sean Durkin <news_ju...@durkin.de> wrote: > Antti wrote: > > Hi > > > finally !!! > > XP2 was scheduled for september 2006 so with a little less than 12 > > months delay its finally announced!! > > Maybe that's because Lattice only announces devices when you can > actually buy them and not 12 months before a "normal" customer can get > his hands on some engineering samples? :) > > cu, > Sean > > -- LOL actually yes. I have just looked at Xilinx website online shop and all distributors there is ABSOLUTLY no deliver information for ANY spartan-3A or 3AN device yet. And S3A is not new anymore. Even S3AN is out for some time, still NO BUYING options, nothing nothing nothing. Xilinx has really mis-understood the meaning of "online shop"... lets hope XP2 devices are readily available, the RAM to flash transfer seems nice feature, also there are again nice small foot print package options offered XP and S3AN have no good package options, so XP2 fills the gap here AnttiArticle: 120239
Antti <Antti.Lukats@googlemail.com> wrote: > options, nothing nothing nothing. Xilinx has really mis-understood the > meaning of > "online shop"... Another example: Look in the online shop of the XC3S500E in hand solderable PS2008. Nill, Zilch, Nada... Then go to digikey.: On stock ... > lets hope XP2 devices are readily available, the RAM to flash transfer > seems nice IS XP2 in some online shop, with online pricing? -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 120240
> > Where do you find the package internal trace lengths documented, so that > you can allow for them in your PCB trace length calculations? > For V2: Download the HSPICE models, unzip, then look in the v2_pkg_flight subdirectory, which has excel files for each package. BrianArticle: 120241
Uwe If you like something hand solderable for XC3S500E have a look at out Craignell modules http://www.enterpoint.co.uk/component_replacements/craignell.html. We also have a new version coming that will allow operation down to 3V and going up to 5.5V supply and IO. These new versions are a few weeks away yet. As usual educational and bulk order discounts available and they will be in our on-line shop when the new batch are available. If you need something more advanced we have Darnaw1 as well. John Adair Enterpoint Ltd. On 4 Jun, 12:20, Uwe Bonnes <b...@hertz.ikp.physik.tu-darmstadt.de> wrote: > Antti <Antti.Luk...@googlemail.com> wrote: > > options, nothing nothing nothing. Xilinx has really mis-understood the > > meaning of > > "online shop"... > > Another example: > > Look in the online shop of the XC3S500E in hand solderable PS2008. Nill, > Zilch, Nada... > > Then go to digikey.: On stock ... > > > lets hope XP2 devices are readily available, the RAM to flash transfer > > seems nice > > IS XP2 in some online shop, with online pricing? > > -- > Uwe Bonnes b...@elektron.ikp.physik.tu-darmstadt.de > > Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt > --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------Article: 120242
On Apr 24, 8:07 pm, Mike Treseler <mike_trese...@comcast.net> wrote: > ferorcuewrote: > > hello, thank you for answering but i am not able to solve my problem > > yet. > > > the generic C_BUS_WIDHT has a default of 1, and the upper levels are > > using the or_gate.vhd file with the same generic. > > > What make me angry is that i cannot modify this files, because they > > are cores from XILINX, that means that i have not modified them, and > > it should work. > > The alternative is to enter the design > directly in vhdl or verilog for synthesis. > > This way, I still find frustrations, > but I can simulate and edit the code as well > as swear at it :) > > -- Mike Treseler Hi friends, I think that I have the solution, I found it in a xilinx webcase. in system_setup.do change: "vsim -novopt -t ps system_conf; set xcmds 1;" Source: 9.1i EDK ModelSim - Error message: "logic.vhd(359): (vopt-1144) Value 0 is out of std.standard.natural range 1 to 32" 04/24/07 11:14:13 Problem Description: Keywords: optimization, -vopt, -novopt I am trying to simulate my EDK system. When I run the simulation in ModelSim 6.2b, I receive an error message similar to the following during the optimization phase: "Error Message: --------------------------------------- D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_v20_v1_10_c/hdl/vhdl/ opb_v20. vhd(550): (vopt-1144) Value 0 is out of std.standard.natural range 1 to 32. # ** Error: D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/ park _lock_logic.vhd(359): (vopt-1144) Value 0 is out of std.standard.natural range 1 to 32. # ** Error: D:/EDK/hw/XilinxProcessorIPLib/pcores/opb_arbiter_v1_02_e/hdl/vhdl/ park _lock_logic.vhd(429): (vopt-1144) Value 0 is out of std.standard.natural range 1 to 32. # Optimization failed # Error loading design # Error: Error loading design # Pausing macro execution" I was able to simulate this same design using a previous version of ModelSim (for example, 6.0a and 6.2a). The previous version of ModelSim did not include this optimization phase. What could be the problem? Solution 1: The problem is that in the later version of ModelSim, it is automatically inserting the -vopt command by default, which clashes with the EDK IP files for the EDK cores. This command performs global optimization on Verilog and mixed-HDL designs after they are compiled, which is not necessary for the EDK IP models. You can work around this issue by inserting the -novopt command in the "do file" that you are using to run the simulation. Alternatively, you can work around this issue by setting the "modelsim.ini" variable "VoptFlow" to 0 (zero). The "modelsim.ini" files are located in the c: \<modelsim>\, c:\<ise_compiled_libraries> and c: \<edk_compiled_libraries> directoriesArticle: 120243
On Jun 4, 12:09 am, javaguy11...@gmail.com wrote: > I have a project where I am trying to use modular design flow. When I > do synthesis of one of my modules I see the message in the log. > > Number of TBUFs: 61 out of 0 (*) > > I think this is causing me problems when I try to do the assemble, > because those modules get dropped from the design. > > Any suggestions on what I am doing wrong or how to work around it. Which device are you using? Spartan, XL, II, IIe have TBUF in hardware. Spartan 3, 3e, 3a, 3an, ... do not. Normally synthesis can replace internal tri-state buses with LUTs, but if you try to instantiate TBUF's in a part that doesn't have any you will "overmap" the device as shown in your report. HTH, GaborArticle: 120244
Hi all, I have a SOC with a Power PC running on a Virtex II pro. On FPGA configuration, the PPC firmware runs correctly, heap reservation on firmware initialisation is correct. When I reset the SOC with the reset controller, the PPC restarts correctly, but when it tries to use the heap to initialize some dynamic variables, I get a fail on the malloc. It seem that on the reset the power PC context is not reinitialized. I guess we have to add something in the boot sequence of the PPC to reset the heap pointer. I'm I right ? It is something that must be standard in the power PC world, does someone have an exemple how to do this ?? Thanks. Stéphane.Article: 120245
Hello again, I got it working! I manually set up the JTAG chain for which the ACE file is to be generated. Used the bsd files for the XCF and the XC95144 device which I found in the ISE directory. Is there any other way to set up the chain? And: Where (in which manual) is mentioned how to proceed? Best regards, Philipp :-)Article: 120246
L. Schreiber wrote: > I'm student at Chemnitz University of Technology, Germany. I'm > interested in purchasing an xupv2p-board from digilent inc as a academic > customer (299$). > > Has anyone done this before (as a student from Germany) and can share > his/her gained experiences. Is it possible at all? > > Thanks. > L. Schreiber It is certainly worth the money. I use it all the time for development work. I usually use to prototype an idea. Digilent has been very nice to work with. I remember when I first got the XUP board was having serious problems with it. I called Digilent on a Holiday (Memorial day or something like that) and the head of the company asnwered and helped me through the problem. Turns out it was a bad power supply circuit. He made sure to get me a new one right away.Article: 120247
On Jun 1, 9:33 am, "Linas Petras" <x...@xx.xx> wrote: > Has anyone seen an issue with the CoreGenerater that when I try and generate > some of the cores I get a "corrupted" dialog box. By this I mean the "image" > in the left of the dialog box is jumbled so that you can't recognize it as a > image. As I see just "blank" tabs across the top of the dialog box. > > I running 9.1SP3. I'm totally at a lose as to what is causing the problem. > > Linas What OS are you running? This kind of problem usually comes from the display driver. I'm running ISE9.1sp3 with no such problems. Are you using a display adapter with accelleration? Something like a video game display adapter? Does the problem persist if you re-size the window? Can you fix it by changing display resolution (possibly bits per pixel i.e. number of colors will affect it?). Did you try the standard Xilinx fix of re-installing ISE? HTH, GaborArticle: 120248
hey motty, i tried connecting it the port myclk to a temproary signal and then to the fabtric, did not work. secondly. tried placing a bufg component in between port myclk and mynewclk and the error is still the same thanks a lot for your help newayz. still breaking my head on it regards, Mahalingam On Jun 3, 12:24 pm, motty <mottobla...@yahoo.com> wrote: > > ERROR:NgdBuild:924 - input pad net 'myclk' is driving non-buffer > > primitives: > > pin C on block my_user_command_register_1 with type FDE, > > I think it looks like your clock input it directly connected from the > input pad to logic. You need to first connect it to some type of > global clock buffer or other clock resource before using it in the > fabric. > > And it looks like you have placed constraints incorrectly for the > led_error_output. It should be an ouput signal at your top level. > Then the syntax in the UCF is: > > NET "led_error_output" LOC = "whatever" | IOSTANDARD = "whatever" ;Article: 120249
I am also using the same board for my project. the board is good i guess and lot of support is targeted towards its use with edk. if ur using ise then go for some ml400 series if budget is not a problem but defnitely worth the money. On Jun 4, 8:44 am, Eli Hughes <emh...@psu.edu> wrote: > L. Schreiber wrote: > > I'm student at Chemnitz University of Technology, Germany. I'm > > interested in purchasing an xupv2p-board from digilent inc as a academic > > customer (299$). > > > Has anyone done this before (as a student from Germany) and can share > > his/her gained experiences. Is it possible at all? > > > Thanks. > > L. Schreiber > > It is certainly worth the money. I use it all the time for development > work. I usually use to prototype an idea. > > Digilent has been very nice to work with. I remember when I first got > the XUP board was having serious problems with it. I called Digilent on > a Holiday (Memorial day or something like that) and the head of the > company asnwered and helped me through the problem. Turns out it was a > bad power supply circuit. He made sure to get me a new one right away.
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