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Hi Claire, The information you are looking for is at: http://www.xilinx.com/ise/products/webpack_config.htm The link is on the WebPack page, but not obvious that it would reveal the supported devices... Eric "Antti" <Antti.Lukats@googlemail.com> wrote in message news:1180520946.288647.288270@p77g2000hsh.googlegroups.com... > On 30 Mai, 11:11, "Claire Murphy" <clairemurphs...@hotmail.com> wrote: >> Thanks for that Eric ! >> >> Anyone know if there is a list of what Xilinx chips work with what >> versions of ISE ? I am becoming more and more frustrated >> withwww.xilinx.com, now I find myself using google and site search to >> find things I need. >> >> Anyway, I would like to find out if I can use the LX50T with the free 9.1 >> version or the 8.x version. >> >> Also downloading a package of 1.5GB and the same size again for an update >> it pretty annoying ! >> >> Thanks ! claire > > no you can not use free tools. > so your initial investment to use ML505 is > > 3200 USD (ISE+ED) > > AnttiArticle: 120001
hi just a quick question: i saw that there is one x-fest in vienna on june 21. i am a student. can i register and attend aswell? and is it really free? thanks UrbanArticle: 120002
Hi, i have been reading the VHDL language over the last week and now i want to put what i have learned so far into practice but don't know really from where to start. As such, i am just wondering if there is any lab book or a web based tutorials that help a newbie like me to gradually get a grip on vhdl design techniques on FPGA. I am seeking any series of recommended labs to proceed through (one after one) Many thanksArticle: 120003
On May 30, 3:08 pm, "u_stad...@yahoo.de" <u_stad...@yahoo.de> wrote: > hi > > just a quick question: i saw that there is one x-fest in vienna on > june 21. > i am a student. can i register and attend aswell? and is it really > free? > > thanks > Urban The answer is: Yes, yes, and yes. The earlier engineers/students become familiar with our parts, the better. Herzlich willkommen. Es ist nie zu frueh, mit FPGAs vertraut zu werden. PeterArticle: 120004
On May 30, 4:14 pm, "dscol...@rcn.com" <dscol...@rcn.com> wrote: > Pablo, > > I was also wondering if you fixed the issues with the assembler that I > wrote to you about last June? > > >From email sent to you. > Hello Dave. Yes, these issues have been fixed. The assembler now accepts bounded '()' tokens; just as a visual convenience since they are converted to regular arguments. The default format is now hexadecimal. If a name is not found in the environment, and if that word is a valid hex number, it gets converted to the latter. It's a shame the kcpsm assembler treats numbers these way, it is not the default format of most assemblers, and usually numbers in a different radix are decorated in some way to avoid confusion or a clash with valid labels. KCAsm supports binary (%) octal (@), decimal (&), and hexadecimal ($) modifiers. KCAsm still accepts names only in valid C format - the identifiers can't start with a number or symbol different to the underscore (_). Please tell me if you find other issues. Best regards. -- PabloBleyerKocik /"But what... is it good for?" pablo / -- 1968 Engineer at IBM's Advanced Computing @bleyer.org / Systems Division, commenting on the microchipArticle: 120005
Hi all, Has anybody done that before? Thanks a lot ! tylx_wuArticle: 120006
We have an application where I need to feed 160 differential data inputs and 20 differential clock inputs to the high end V5 FPGA. There is one differential clock for every 8 differtnial data inputs. I would like to use LVPECL inputs for this. 160 differential data inputs will be running at 800Mbps 20 Differenital clock inputs will be running at 400MHz. In order to provide DDR clock for 160 data channels. Inside the FPGA we would like to use 1:4 demux and convert the data bus to 640 bits wide running at 200MHz so the FPGA fabric can handle it. Then the data will be fed to either 640 bits wide internal FIFO (as deep as I can get) or if I had a choice then feed the 640 bits wide bus running at 200MHz to external high density FIFO. This may require need for another FPGA. I have seen Xilinx application note for supporting such configuration. But in our application we need a lot more data inputs. I would like to get your input on this. Is this possible using high end V5 FPGA? Thanks.Article: 120007
DGerimi@googlemail.com wrote: > Hi, > i have been reading the VHDL language over the last week and now i > want to put what i have learned so far into practice but don't know > really from where to start. As such, i am just wondering if there is > any lab book or a web based tutorials that help a newbie like me to > gradually get a grip on vhdl design techniques on FPGA. I am seeking > any series of recommended labs to proceed through (one after one) > > Many thanks > I would suggest downloading the modelsim xilinx starter edition (XSE) from the xilinx website. Then you can try things and simulate them and see the result. You could also download the xilinx webpack tools so you can synthesize your designs to see how big/fast they are. I think there are tutorials/examples that come with webpack but I could be wrong.Article: 120008
Many schools offer courses that cover HDL based hardware design. Many of these courses make the material, including the labs, public. Off the top of my head, check MIT open courseware. ---Matthew Hicks > Hi, > i have been reading the VHDL language over the last week and now i > want to put what i have learned so far into practice but don't know > really from where to start. As such, i am just wondering if there is > any lab book or a web based tutorials that help a newbie like me to > gradually get a grip on vhdl design techniques on FPGA. I am seeking > any series of recommended labs to proceed through (one after one) > Many thanks >Article: 120009
MM wrote: > Hi all linux users there, > > I was wondering if the ISE/EDK linux installation scripts are supposed to > create desktop icons and/or create appropriate entries in the program menu? > I have installed both tools on a Kubuntu system and none of these were > created... > > > Thanks, > /Mikhail > > Nope, you have to do all that yourself. Depending what version of Kubuntu you're running, you may have other troubles. For example, if you get errors referencing GLIBC you need to set the environment variable LD_ASSUME_KERNEL=2.4.7 (this is not a problem in recent releases of ISE/EDK). Getting a download cable to work is also a treat. I recommend ignoring the Xilinx drivers and use the userspace driver from: http://www.rmdir.de/~michael/xilinx/ I have it working for impact, chipscope analyzer, and XMD, at least in all modes I actually use. I can elaborate further all the fun I had getting it to work on a 64-bit system, if that's something you'll need (post here but CC my email to be sure I see it; I don't check every day). In any case, it works great on my Linux boxen which is a relief since EDK does not get along with my laptop at all (multiple applications built on top of Cygwin are not playing nice at all). Good luck, and drop me a note if you need more help. kenArticle: 120010
On 30 mayo, 12:55, Andreas Ehliar <ehl...@lysator.liu.se> wrote: > On 2007-05-30, raxpe...@gmail.com <raxpe...@gmail.com> wrote: > > > Dear Folks ! > > > I'm hvin a rather outdated XS40 board, which I'm planning to start > > experiment with. Unfortunately, I don't have the Parallel Download > > cable for it. > > > Is there any circuitry inside the cable or is it just pin-to-pin > > connection ?? Can anybody clarify this for me ? > > From what I remember [1] it is just a straight pin-to-pin connection.www.= xess.comdo have old manuals available, you could always take > a look there if in doubt. > > BTW, do you have software available which can handle the FPGA > on it? There hasn't been any support for the XC4K fpga for quite a > long time now in ISE... > > Good luck with your experimentation! > > /Andreas > > [1] I have rather fond memories of this board since it was the > prototype board which introduced me to FPGAs a number of years > ago. Hi. Yes, it's a straight pin-to-pin parallel cable. You can use Xilinx ISE 4 tools to design for that board and Xess XSTools to upload the configuration bit file to the board. I used this board to design an Atmel 89c51 programmer (VHDL design + xs40 board + 2 transistors + 4 resistors + 1 Voltage regulator) and a simple software in the PC. Maybe we can share some ideas. Cheers, Hern=E1n S=E1nchezArticle: 120011
John_H wrote: > > If it's important to not have reflections, the R-only equivalent > termination is superb. > > If it's important to have the high slew rate, the standard > termination with the associated pin capacitance is the way to go > because the reflection *will* be absorbed by the transmitter's > impedance if it's properly matched. > As an aside, if you're feeling bold, and have board space to spare, a T-coil termination network theoretically could both peak the load AND terminate the line all in one fell swoop. I posted about this on the si-list last year, and one of the Teraspeed guys provided some more T-coil references: http://www.freelists.org/archives/si-list/03-2006/msg00153.html http://www.freelists.org/archives/si-list/03-2006/msg00162.html I've considered this impractical at the board level with wide LVDS buses, but the T-coil papers make for fun reading nonetheless! > > If it's important to have the high slew rate, the standard > termination with the associated pin capacitance is the way to go > because the reflection *will* be absorbed by the transmitter's > impedance if it's properly matched. > At the 1 Gbps rates claimed by Xilinx, the typical Rx Cin of ~10 pf (single ended) [Note 1] often presents difficulties that need to be addressed during the board design phase, particularly when using fast drivers from other logic families. IIRC, the 500 Mbps 1995 ANSI LVDS spec called out: output swing: 250 mV min differential source impedance: 40-140 ohm single ended termination impedance: 90-110 ohms differential driver rise/fall time: 300 ps min, 500 ps max Even within the range of allowed values for this old, slow spec, a 300 ps edge WILL reflect off of the 10 pF Cin (single ended) of a Xilinx pin, and then subsequently re-reflect off any 80-280 ohm (differential) impedance mismatch at the driver. Later, faster specs such as HyperTransport tighten these requirements even more to help deal with the faster edges of a 1 Gbps driver. Despite newsgroup claims that Xilinx parts "meet all specs and standards", they do not in fact meet many of the Cin, Rdiff, rise/fall, and even Vod (in S3) of the relevant standards for the claimed input data rates. Xilinx _DT input terminations are 100 ohm +/-20%, or worse, depending upon family and common mode input voltage [Note 2]. Brian Note 1: Cin (single ended) vs. Cin (differential) If the input signal is perfectly differential, the reflections will be IDENTICAL regardless of whether input C is modeled as two 10 pf shunt Cin (as specified in both the datasheet and the IBIS models) or as one 5 pf Cdiff. Calling it 5 pF doesn't make the parts work any better. If the input signal is NOT perfectly differential, the 10 + 10 = 5 simplification does not apply. Note 2: The _DT terminators seem to be implemented using FETs, producing a bowed termination curve that is near 100 ohms only when Vicm is somewhere near the output driver's specified Vocm. The actual Rdt value varies family to family, and changes with VCCO and Vicm. Measurements of a sample-of-one FX12 LVDS_25_DT, at nominal 2.5V VCCO supply, at room temp: Vicm Rdt ----------------------- 0.50 V ~ 74 ohms 0.75 V ~ 78 ohms 1.00 V ~ 94 ohms 1.25 V ~ 125 ohms 1.50 V ~ 157 ohms using a 7CT1N curve tracer with two 100 ohm series R's to reduce Vdiff to about Vin/3 Sweeping Vin 0-3V => Vicm 0-1.5V : : 7CT1N + ----/\/\----- : 100 | : / : Vin \ Rdt : / : | : 7CT1N - ----/\/\----- : 100Article: 120012
Forgive the top posting, please. Brian, I always appreciate a well-considered discussion and hope to look at the T-coil references. Beyond these references I don't know that the rest of the discussion does much more than stir the bees nest though I do also appreciate the perspective from the curve tracer. Austin, I'm sure you want to retort. Could you let this one go by without a response? It's feeling old. - John_H Brian Davis wrote: > John_H wrote: >> If it's important to not have reflections, the R-only equivalent >> termination is superb. >> >> If it's important to have the high slew rate, the standard >> termination with the associated pin capacitance is the way to go >> because the reflection *will* be absorbed by the transmitter's >> impedance if it's properly matched. >> > As an aside, if you're feeling bold, and have board space to spare, > a T-coil termination network theoretically could both peak the load > AND terminate the line all in one fell swoop. > > I posted about this on the si-list last year, and one of the > Teraspeed guys provided some more T-coil references: > > http://www.freelists.org/archives/si-list/03-2006/msg00153.html > http://www.freelists.org/archives/si-list/03-2006/msg00162.html > > I've considered this impractical at the board level with wide > LVDS buses, but the T-coil papers make for fun reading nonetheless! > >> If it's important to have the high slew rate, the standard >> termination with the associated pin capacitance is the way to go >> because the reflection *will* be absorbed by the transmitter's >> impedance if it's properly matched. >> > At the 1 Gbps rates claimed by Xilinx, the typical Rx Cin of > ~10 pf (single ended) [Note 1] often presents difficulties that > need to be addressed during the board design phase, particularly > when using fast drivers from other logic families. > > IIRC, the 500 Mbps 1995 ANSI LVDS spec called out: > output swing: 250 mV min differential > source impedance: 40-140 ohm single ended > termination impedance: 90-110 ohms differential > driver rise/fall time: 300 ps min, 500 ps max > > Even within the range of allowed values for this old, slow spec, > a 300 ps edge WILL reflect off of the 10 pF Cin (single ended) > of a Xilinx pin, and then subsequently re-reflect off any > 80-280 ohm (differential) impedance mismatch at the driver. > > Later, faster specs such as HyperTransport tighten these > requirements even more to help deal with the faster edges > of a 1 Gbps driver. > > Despite newsgroup claims that Xilinx parts "meet all specs > and standards", they do not in fact meet many of the Cin, Rdiff, > rise/fall, and even Vod (in S3) of the relevant standards for > the claimed input data rates. > > Xilinx _DT input terminations are 100 ohm +/-20%, or worse, > depending upon family and common mode input voltage [Note 2]. > > > Brian > > > Note 1: Cin (single ended) vs. Cin (differential) > > If the input signal is perfectly differential, the reflections > will be IDENTICAL regardless of whether input C is modeled as > two 10 pf shunt Cin (as specified in both the datasheet and > the IBIS models) or as one 5 pf Cdiff. > > Calling it 5 pF doesn't make the parts work any better. > > If the input signal is NOT perfectly differential, the > 10 + 10 = 5 simplification does not apply. > > > Note 2: > > The _DT terminators seem to be implemented using FETs, > producing a bowed termination curve that is near 100 ohms > only when Vicm is somewhere near the output driver's > specified Vocm. > > The actual Rdt value varies family to family, and changes > with VCCO and Vicm. > > Measurements of a sample-of-one FX12 LVDS_25_DT, > at nominal 2.5V VCCO supply, at room temp: > > Vicm Rdt > ----------------------- > 0.50 V ~ 74 ohms > 0.75 V ~ 78 ohms > 1.00 V ~ 94 ohms > 1.25 V ~ 125 ohms > 1.50 V ~ 157 ohms > > using a 7CT1N curve tracer with two 100 ohm > series R's to reduce Vdiff to about Vin/3 > > Sweeping Vin 0-3V => Vicm 0-1.5V > > : > : 7CT1N + ----/\/\----- > : 100 | > : / > : Vin \ Rdt > : / > : | > : 7CT1N - ----/\/\----- > : 100Article: 120013
On May 30, 12:00 pm, Guru <ales.gor...@email.si> wrote: > On May 25, 12:20 pm, Pablo <pbantu...@gmail.com> wrote: > > > I have a SMT338 board. This is a FPGA module and now I want to add a > > DDR SDRAM to my system. I have the ucf file provided by the company > > but in this file I don't find ddr_feedback clock. What it means?. I > > suppose that this pin is neccesary, but there is no pin called > > "feedback" or "clk_fb" or "clk_ddr". I only see the clock signal "ck" > > y "ckn" but these signals are used by the fpga to the ddr. > > > Has anyone the solution?. > > > Regards > > The extra pin is used for DCM feedback which compensates logic delay. > It is connected to the same DDR in as clk. For more info about > clocking variations see the OPB_DDR (or PLB_DDR) datasheet. > > Cheers, > > guru So, are you telling me that these two entries (of the ucf file used by edk) are the same? Net fpga_0_MT46V16M16TG_DDR_CLK_FB LOC=; Net fpga_0_Micron_DDR_MT46V16M16TG_75_DDR_Clk_pin LOC=; And this means that I have to change the following line (of the mhs file; hardware description) and put "DIR = IO " (because dcm needs a feedback signal). PORT fpga_0_Micron_DDR_MT46V16M16TG_75_DDR_Clk_pin = fpga_0_Micron_DDR_MT46V16M16TG_75_DDR_Clk, DIR = OArticle: 120014
On May 30, 6:56 pm, "John_H" <newsgr...@johnhandwork.com> wrote: > ... > http://www.xilinx.com/xlnx/xebiz/designResources/ip_product_details.j... > > used that same board. > - John_H John, I know the "Spartan-3E 1600E MicroBlaze Development Kit" use the same board ...but I don't need EDK... thanks anyway SandroArticle: 120015
"Symon" <symon_brewer@hotmail.com> wrote in message news:f3jq5a$q5f$1@aioe.org... >> Tool, >> Connect the LOCKED signal from the first DCM to the reset of the next DCM >> via an inverter. >> HTH, Syms. > BTW, I'm not sure that cascading DCMs, especially when you're using the > CLKFX output of the first DCM, is such a bright idea. Try searching the > CAF archive for more info. Include 'jitter' in your keywords. If you post > your specific application, someone clever/experienced will probably > suggest an alternative that'll save you from a world of hurt. > Syms. Thank you Symin and Gabor. I will do that. And I added a BUFGMUX to the output of the second DCM. This is for generating a very special frequency from a 30MHz input clock.Article: 120016
On May 30, 4:31 am, bngguy <bng...@gmail.com> wrote: > Hi, > I'm working on implementing an FIR Filter on a FPGA (Spartan 3E), > here's what i want to accomplish --> > > The FIR Filter coefficients are generated on a host system using > LabView, these coefficients are written to a RAM / PROM on a DSP > card , the number of taps is constant but other parameters like > sampling frequency and cut off frequencies can change according to > requirements. > > The FPGA reads these coefficients from the RAM / PROM and implements > the FIR Filter.There should be a single bit file that is downloaded to > configure the FPGA. > > Any pointers in the right direction would be appreciated. > > Thanks > Tim Hi Tim, Use the core generator in ISE and select Distributed Arithmetic FIR. This core enables to modify coefficients on the fly - during operation. You just need to have some kind of interface to download this coefficients (serial, parallel, SPI...). Cheers, GuruArticle: 120017
On 30 Maj, 21:32, msn...@gmail.com wrote: > Hello, > > I'm trying to use a slightly unconventional way of configuring a > Xilinx Virtex4 FPGA that as far as I can tell should work, but > doesn't. The plan involves using a microcontroller to place an atmel > serial flash into continuous read mode, and then relinquish control of > the flash's clock and data output lines to the FPGA, and finally > release INIT. The FPGA, set to Master Serial mode, then begins > clocking the data out of the flash as if it were clocking out of a > xilinx PROM. > > It all seems to work the way it should -- the right data appears on > the data line -- but DONE never goes high, it just keeps clocking as > if it's not getting any data. The one difference between the flash and > a xilinx PROM is that the flash outputs data on the falling edge of > the clock, while the PROM outputs on the rising edge. And indeed, if I > place an inverter in line with CCLK, the configuration works fine. > > I don't understand why the clock polarity is causing a problem given > that the FPGA supposedly samples on the rise of CCLK. On the rise of > CCLK, the data out of the flash has been stable for a full cycle, > having changed on the fall of CCLK. > > Anyone know what I'm missing? Hi, So, use the inverter :) It could be configuration requirement of FPGA, I mean setup and hold time. Maybe you'll find usefull information in AC requirement in FPGA's datasheet. Best regards, Jerzy GburArticle: 120018
Hi there, I'm thinking about implementing some data compression algorithms on an FPGA (Xilinx Virtex-II) using VHDL. Because speed and FPGA utilization are very important in this respect, I'd like to get some basic idea about complexity and achieveable speed before starting. Does anyone know about existing FPGA- implementations of - Run-Length-Encoding (RLE) - RLE with Burrows-Wheeler Transformation (BWT) - JBIG - Lempel-Ziv LZ77 and the achieved throughput und device utilization? Maybe some details about existing ASIC implementations of the above mentioned methods may also help...? Thanks in advance. Regards GeroArticle: 120019
Hi, I am very interesting in how could I use ISE to create a PowerPC model. I know that there is a Export to Project Navigator, but it doesn't seem to work fine. First, I use EDK to create my PowerPC model with peripheral, dcm_modules,... Then I open ISE and add the system.xmp from EDK. Then I instantate and I get the system_stub.vhd which I save at the project navigator folder and I add to the project, so my solution is: system_stub.vhd system.xmp system.ucf But I cannot see the complete vhdl code. For example I cannot see the code from the dcm_module, the code from the util_vector_module, etc. I know that quite a lot designers use this ISE Flow, but how can they see the complete project in vhdl. Thanks, and Regards PabloArticle: 120020
On 31 Mai, 12:11, "Geronimo Stempovski" <geronimo.stempov...@arcor.de> wrote: > Does anyone know about existing FPGA- implementations of > > - Run-Length-Encoding (RLE) We did a schematic implementation of an RLE coder for the XC3100A family. It achieved around 85MHz. Later we implemented a 150MHz Huffman encoder in Spartan-II. Both were rather simple projects. Kolja SulimmaArticle: 120021
"Symon" <symon_brewer@hotmail.com> wrote in message news:f3jq5a$q5f$1@aioe.org... >> Connect the LOCKED signal from the first DCM to the reset of the next DCM >> via an inverter. The inverter method didn't work in simulation. I put an BUFGMUX there also.Article: 120022
On Tue, 29 May 2007 23:04:14 +0200, Frank Buss <fb@frank-buss.de> wrote: >Brian Drummond wrote: > >> "it is not thought wise to design for higher speeds than this as yet" >> http://www.alanturing.net/turing_archive/archive/p/p01/P01-001.html >> (from 1945) >The interesting thing is the instruction set, but it is very difficult to >extract it from the document, because it is a mix of proposals and detailed >descriptions of which registers to use for which arithmetic operations. Is >there any documentation of the actually running system? If possible, as a >modern, pure functional, description, without describing the problems and >architecture of mercury delay lines :-) http://www.alanturing.net/turing_archive/archive/index/aceindex.html contains the full archive. Some documents from 1951 contain information on the final machine. http://www.alanturing.net/turing_archive/archive/l/l22/L22-001.html "Report on the Pilot Model" http://www.alanturing.net/turing_archive/archive/l/l13/L13-001.html "Programming and Coding for the pilot model" http://www.alanturing.net/turing_archive/archive/l/l11/L11-001.html appendix describing 1954 modifications, inc. drum store. The first of these refers to the 1948 "Progress Report" http://www.alanturing.net/turing_archive/archive/l/l10/L10-001.html which defines the terms and symbols used. - BrianArticle: 120023
thanks for the fast response, what about complexity, i.e. equivalent gate count?Article: 120024
On 31 Mai, 13:05, "Geronimo Stempovski" <geronimo.stempov...@arcor.de> wrote: > thanks for the fast response, what about complexity, i.e. equivalent gate > count? Next to nothing for the RLE (40 LUTs???). A barrel shifter, a BRAM and some logic for the Huffmann. Kolja Sulimma
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